Semiconductor coated chip

Abstract

The utility model relates to the technical field of semiconductors, in particular to a semiconductor coated chip, which comprises a P surface gold-plated film, a substrate P surface, an active area, a substrate N surface, an N surface gold-plated film and at least one gold-tin film group, the P surface gold-plated film is arranged on the substrate P surface, and the gold-tin film group is arranged on the substrate N surface. The utility model provides a semiconductor coated chip, at least one film group containing various materials is alternately generated on the surface of the chip, on one hand, evaporation coating equipment can be fully utilized in the manufacturing process of the semiconductor coated chip, gold-tin films deposited on the surface of a heat sink again in the technological process are reduced, and the manufacturing period is saved; and on the other hand, the semiconductor coating chip is directly bonded with the heat sink carrier, so that the welding process flow of the chip and the carrier can be simplified, the voidage can be reduced, the performance of the chip is improved, and the service life of the chip is prolonged.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a semiconductor coated chip. Background Art

[0002] With the continuous development and application of the integrated circuit industry, chip design has become increasingly complex, the integration degree has become higher and higher, and the difficulty of chip welding and packaging has become greater and greater. The current common process is to prefabricate gold-tin on a heat sink or use a gold-tin solder sheet to perform welding bonding on a chip and a heat sink carrier. However, this method usually has voids formed by the oxide film, dust particles, and bubbles not discharged during melting on the surface of the solder. The film formed by the oxide will hinder the mutual penetration of the bonding parts on the metallized surface, and the remaining gaps will form voids after cooling and condensation. The voids formed during welding will reduce the reliability of the device, increase the possibility of IC fracture, increase the operating temperature of the device, weaken the bonding ability of the die, and also affect the grounding effect and other electrical properties. In some power semiconductor modules (such as high-voltage IGBT modules, etc.), when using paste solder or press-formed sheet solder to weld components to a substrate, various problems in chip package welding are brought about due to the poor solder layer uniformity and flux residue of the paste solder, the lack of adhesiveness of the sheet solder, and the low welding positioning accuracy of easy relative movement with components and carriers. Therefore, it is necessary to provide a new type of semiconductor chip. Summary of the Invention

[0003] The purpose of the utility model is to provide a semiconductor coated chip, thereby at least to a certain extent overcoming the above problems existing in the prior art.

[0004] According to one aspect of the utility model, there is provided a semiconductor coated chip, which successively includes: a gold-plated film on the P side, the P side of the substrate, an active region, the N side of the substrate, a gold-plated film on the N side, and at least one gold-tin film group. The gold-plated film on the P side is disposed on the P side of the substrate, and the gold-tin film group is disposed on the N side of the substrate.

[0005] In an exemplary embodiment, the mass ratio of the gold material to the tin material in the film group is 1:9 to 9:1.

[0006] In an exemplary embodiment, the plating technology of the film group is electron beam evaporation coating technology, thermal resistance evaporation coating technology, and / or magnetron sputtering coating technology.

[0007] In an exemplary embodiment, the substrate is a diamond material or a gallium nitride material.

[0008] In an exemplary embodiment, the thicknesses of the gold-plated film on the P side and the gold-plated film on the N side are both 0.1 to 5 μm.

[0009] In an exemplary embodiment, the semiconductor coated chip further includes: a blue light epitaxial layer, a red light epitaxial layer, and a green light epitaxial layer.

[0010] In an exemplary embodiment, an electrode is provided on the P-side gold-plated film.

[0011] In an exemplary embodiment, the semiconductor coated chip further includes: a chip carrier and at least one gold-tin film group disposed on the carrier.

[0012] In an exemplary embodiment, the chip carrier is made of copper diamond material or copper graphene material.

[0013] The present utility model provides a semiconductor coated chip, on the surface of which at least one film group containing various materials is alternately formed. On the one hand, in the manufacturing process of the semiconductor coated chip, an evaporation coating device can be fully utilized, and the manufacturing cycle can be saved by reducing the deposition of gold-tin films on the surface of the heat sink again in the process flow; on the other hand, the direct bonding of the semiconductor coated chip to the heat sink carrier can simplify the chip-carrier welding process flow and reduce the void ratio, thereby improving the performance and service life of the chip. Description of the Drawings

[0014] Figure 1 is a schematic structural diagram of a semiconductor coated chip in an embodiment of the present utility model;

[0015] Figure 2 is a schematic structural diagram of a chip carrier in an embodiment of the present utility model. Detailed Embodiments

[0016] To make the objectives, features, and advantages of the present utility model more obvious and understandable, the technical solutions in the embodiments and implementation manners of the present utility model will be clearly and completely described below with reference to the drawings. However, the exemplary embodiments and examples can be implemented in various forms and should not be construed as limited to the examples described herein; on the contrary, these embodiments and examples are provided so that the present utility model will be more comprehensive and complete, and the concepts of the exemplary embodiments and examples will be fully conveyed to those skilled in the art. The features, structures, or characteristics described in the present utility model can be combined in any suitable manner in one or more embodiments and examples. In the following description, many specific details are provided to give a full understanding of the embodiments and examples of the present utility model. However, those skilled in the art will realize that the technical solutions of the present utility model can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be used. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring the various aspects of the present utility model.

[0017] In addition, the accompanying drawings are only schematic illustrations of the present utility model and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus the repeated description thereof will be omitted. Although the steps of the method in the present utility model are described in a specific order in the accompanying drawings, however, this does not require or imply that these steps must be executed in this specific order, or that all the steps shown must be executed to achieve the desired result. The flowcharts shown in the accompanying drawings are only illustrative and not all steps must be included. For example, some steps can be decomposed, while some steps can be combined or partially combined, so the actual execution order may change according to the actual situation. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0018] An exemplary embodiment of the present utility model provides a semiconductor coating chip. Figure 1 It is a schematic structural diagram of a semiconductor coating chip in an embodiment of the present utility model. As Figure 1 shown, the semiconductor coating chip includes: a P-side gold-plated film, a substrate P-side, an active region, a substrate N-side, an N-side gold-plated film, and at least one gold-tin film group. The P-side gold-plated film is disposed on the substrate P-side, and the gold-tin film group is disposed on the substrate N-side.

[0019] Specifically, the chip is fabricated on a semiconductor material through circuit design, wafer manufacturing, packaging manufacturing, cost testing, etc. Its steps are as follows: First is chip design, that is, generating a "pattern" according to design requirements. The raw material of the chip, the silicon wafer, is made of silicon refined from quartz sand, and pure silicon is made into a silicon ingot to become the material for manufacturing the quartz semiconductor of integrated circuits. It is sliced into wafers specifically required for chip manufacturing. The thinner the wafer, the lower the production cost, but the higher the requirement for the process. The wafer coating can resist oxidation and has heat resistance, and its material is a type of photoresist. In the wafer lithography, development, and etching process, chemicals sensitive to ultraviolet light are used, that is, they become soft when exposed to ultraviolet light. By controlling the position of the light-shielding object, the shape of the chip can be obtained. A photoresist is coated on the silicon wafer, making it dissolve when exposed to ultraviolet light. And through the first light-shielding object, the part directly irradiated by ultraviolet light can be dissolved, and this dissolved part can then be washed away with a solvent, and the remaining part is the same as the shape of the light-shielding object, thus obtaining the silicon dioxide layer we need. Doping impurities implants ions into the wafer to generate corresponding P-type and N-type semiconductors. The specific process is to put a chemical ion mixture into the exposed area on the silicon wafer. This process will change the conduction mode of the doped area, enabling each transistor to conduct, cut off, or carry data. Simple chips can use only one layer, but complex chips usually have many layers, and different layers can be connected by opening windows. More complex chips may require multiple silicon dioxide layers, and at this time, it is achieved by repeating lithography and the above processes to form a three-dimensional structure. Wafer testing After the above several processes, individual grid-shaped die are formed.

[0020] The electrical characteristics of each die are detected by probing. Generally, the number of die in each chip is huge, and organizing a probing test mode is a very complex process. Therefore, during production, it is preferably to produce a large quantity of chips of the same chip specification structure model. The larger the quantity, the lower the relative cost. Packaging Fixes and bonds the pins of the manufactured wafer and makes various different packaging forms according to requirements. This is why the same chip core can have different packaging forms. For example: DIP, QFP, PLCC, QFN, etc. The last process of chip manufacturing is testing, which can be further divided into general testing and special testing. The former is to place the packaged chip in various environments to test its electrical characteristics, such as power consumption, operating speed, breakdown voltage, etc. The tested chips are classified into different grades according to their electrical characteristics. Special testing is to take out some chips from those with similar parameter specifications and varieties according to the technical parameters required by customers and conduct targeted special testing to see if they can meet the special needs of customers, so as to decide whether to design a dedicated chip for customers.

[0021] In this exemplary embodiment, a circuit such as a transistor is fabricated in a P-type region of a semiconductor material by the above method, and the area outside the circuit region is a substrate, and the area between the P-side and the N-side of the substrate is an active region, which is an area on a silicon wafer where active devices are made. For MOS devices, different doping can form an n-type or p-type active region, and the active region is divided into a source region and a drain region.

[0022] In an exemplary embodiment, the thin film material can be alloy solders such as AuGu, AuGe, AuSn, AuSi, Snln, SnAg, SnBi, etc. Various solders can be suitable for different welding scenarios due to their respective characteristics. For example, silver-containing solder SnAg is easy to bond with the silver-containing end face of the coating, and gold-containing and indium-containing alloy solders are easy to bond with the gold-containing end face of the coating. The following takes the generation of a gold-tin film and the formation of a gold-tin alloy as an example to exemplify the various steps of the present invention. A gold material film is plated on the circuit area surface and the N side of the substrate of the semiconductor coating chip to form metal interconnects and improve the fusion degree of the re-coating. The multilayer gold-tin film is plated on the N side of the substrate. For example, the gold-tin film can be formed on the chip by electron beam evaporation, thermal resistance evaporation, magnetron sputtering, or any one or more of these methods. Generally speaking, at least 2 to 99 groups of gold / tin thin films are generated, and the thickness of the thin films can be 0.3um to 10um, so that each group of thin films can diffuse with each other in the subsequent annealing process to form a more uniform gold-tin alloy material; illustratively, the chip can include a P-side gold-plated layer with a thickness of 0.1-5um, a Si / InP / GaN / GaAs / diamond substrate P-side, an active area or gain area, a Si / InP / GaN / GaAs / diamond substrate N-side and a N-side gold-plated layer with a thickness of 0.1-5um from top to bottom. In an exemplary embodiment, the semiconductor film-coated chip also includes: a blue light epitaxial layer, a red light epitaxial layer and a green light epitaxial layer. In an exemplary embodiment, an electrode is provided on the P-side gold-plated film.

[0023] In an exemplary embodiment, the P side and N side of the semiconductor coated chip are formed with titanium-gold, nickel-gold, chromium-gold layers or titanium-platinum-gold thin film layers by electroplating or electroless plating, and a gold thin film layer with a thickness of 0.05 - 5 μm is formed. Among them, the surface of the chip is the side opposite to the side where the integrated circuit is fabricated on the chip. The P side and N side of the chip are formed according to the material of the semiconductor for fabricating the chip. In some embodiments, if electronic devices such as integrated circuits are fabricated on the P side of the semiconductor chip, then the thin film is formed on the N side of the semiconductor chip. Among them, the ratio of the gold / tin thin film obtains the eutectic point of the gold-tin binary phase diagram of 8:2 and 1:9 of the gold-tin binary eutectic alloy according to the mass ratio of gold to tin of 1:9 - 9:1. In an exemplary embodiment, the P side of the semiconductor chip is provided with an integrated circuit, and both the P side and N side are prepared with titanium-gold, nickel-gold, chromium-gold layers or titanium-platinum-gold layers, and a 0.05 - 5 μm gold-plated thin film by electroplating or chemical coating. In one embodiment, a carrier such as Figure 2 as shown, at least one gold-tin thin film group is provided on the chip carrier for welding with the above-mentioned semiconductor coated chip. The chip carrier can be a copper-diamond material or a copper-graphene material.

[0024] A semiconductor coated chip provided by the present utility model can solve the problem that it is difficult for the traditional heat sink surface flatness and coating materials to reach the roughness and flatness of the current chip. By virtue of the characteristics of low roughness and good flatness of the N side of the semiconductor chip, thin film preparation can be realized; the N side of the chip has good roughness and flatness, and the surface roughness of the heat sink can be relaxed during the bonding process, which can be relaxed from 0.4 to below 1.0, thereby reducing the processing difficulty of the processing industry and controlling the material cost at the same time; after the gold-tin is prepared on the N side of the chip and bonded with the heat sink, the solder at the lower end of the chip can more fully dissipate heat for the chip, improving the performance and lifespan; the P side of the traditional chip is under compressive stress, resulting in a positive chip smile. If the N side of the chip is plated with gold-tin, the strength of the chip can be improved, and at the same time, the compressive stress of the P side can be corrected to tend to decrease, so that the performance of the bonded product is better; the manufacturing process of chip manufacturers is complex and has many processes, about nearly a hundred processes. Among them, grinding and polishing can easily achieve low roughness and high flatness, and there is also coating equipment as a part of the process. If a chip with a weldable N side can be prepared by a one-time process in the chip manufacturing process and directly used for the packaging and bonding of the optoelectronic device industry, this can greatly save the manufacturing cycle of the heat sink machining industry and save the production cycle.

[0025] The basic principles of the present utility model have been described in connection with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present utility model are merely examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present utility model. Additionally, the specific details disclosed above are only for illustrative and facilitating understanding purposes and not for limitation. These details do not limit the present utility model to necessarily adopt such specific details for implementation.

[0026] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present utility model are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open-ended terms meaning "including but not limited to" and can be used interchangeably with each other. The word "or" and "and" used herein refer to the phrase "and / or" and can be used interchangeably with it, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to" and can be used interchangeably with it.

[0027] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present utility model. The present utility model is intended to cover any variations, uses, or adaptations of the present utility model that follow the general principles of the present utility model and include common general knowledge or conventional technical means in the technical field not disclosed in the present utility model. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present utility model are pointed out by the following claims.

[0028] It should be understood that the present utility model is not limited to the exact structures already described and shown in the drawings and can be modified and changed without departing from its scope. The scope of the present utility model is only limited by the appended claims.

Claims

1. A semiconductor coated chip, characterized in that , The semiconductor coated chip sequentially includes: a P-side gold-plated film, a substrate P-side, an active region, a substrate N-side, an N-side gold-plated film, and at least one gold-tin film group. The P-side gold-plated film is disposed on the substrate P-side, and the gold-tin film group is disposed on the substrate N-side.

2. The semiconductor coating chip according to claim 1, wherein , In the film group, the eutectic film group of gold material and tin material is combined with the N-side gold-plated film.

3. The semiconductor coating chip according to claim 1, characterized in that , The coating technique of the film group is electron beam evaporation coating technique, thermal resistance evaporation coating technique, and / or magnetron sputtering coating technique.

4. The semiconductor coating chip according to claim 1, wherein , The substrate is a diamond material or a gallium nitride material.

5. The semiconductor coating chip according to claim 1, wherein , The thicknesses of both the P-side gold-plated film and the N-side gold-plated film are 0.1 to 5 μm.

6. The semiconductor coating chip according to claim 1, wherein , It further includes: a blue light epitaxial layer, a red light epitaxial layer, and a green light epitaxial layer.

7. The semiconductor coating chip according to claim 1, wherein , Electrodes are disposed on the P-side gold-plated film.

8. The semiconductor coating chip according to any one of claims 1-7, characterized in that , The semiconductor coated chip further includes: a chip carrier and at least one gold-tin film group disposed on the carrier.

9. The semiconductor coating chip according to claim 8, characterized in that , The chip carrier is a copper diamond material or a copper graphene material.

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