Semiconductor structure

Abstract

One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes first and second active regions, a metal gate structure, an insulating structure, a source / drain contact, and a feed-through hole. The first and second active regions extend longitudinally along a first direction. The metal gate structure is located over the channels of the first and second active regions and longitudinally extends along a second direction perpendicular to the first direction. The insulating structure cuts through the metal gate structure and is disposed between the first and second active regions along the second direction. Source / drain contacts are over the insulating structure and the source / drain features of the first and second active regions and extend longitudinally along the second direction. A feed-through hole contacts a bottom surface of the source / drain contact and penetrates a portion of the insulating structure. The insulating structure surrounds the feed-through hole and isolates the feed-through hole from the metal gate structure.

Description

Technical Field

[0001] Embodiments of the present utility model relate to semiconductor technology, and more particularly to semiconductor structures. Background Art

[0002] The electronics industry has experienced a continuous growing demand for smaller and faster electronic devices, which at the same time need to support a greater number of increasingly complex and sophisticated functions. To meet these demands, there is a continuous trend in the integrated circuit (IC) industry to fabricate low-cost, high-performance, and low-power-consuming ICs. To date, these goals have been largely achieved by reducing the size of ICs (e.g., the minimum IC component size), thereby increasing production efficiency and reducing associated costs. However, this miniaturization has increased the complexity of IC manufacturing processes. Therefore, to achieve continuous progress in IC devices and their performance requirements, similar progress in IC manufacturing processes and technologies is needed.

[0003] One advancement is the use of vias to connect signals from the front side of a wafer to the back side of the wafer. This allows for flexibility in forming semiconductor components on the front and back sides of a semiconductor structure. In one example, a via can electrically connect a front-side source / drain component to a back-side power rail. However, since vias take up space, the cost of forming vias is typically high. For example, vias are formed inside a feedthrough cell isolated from an adjacent active region. In these cases, vias are formed between passive regions, which take up additional space in a circuit layout. This in turn increases the pitch between active regions and reduces the functional density. To more effectively integrate vias and save space, vias can be formed directly between active regions without the need for dedicated non-active feedthrough cells. However, this may pose a risk of short circuits between vias and other active metal structures such as metal gates.

[0004] Therefore, while existing methods for forming vias are generally sufficient for their intended purposes, they are not entirely satisfactory in every aspect. Summary of the Utility Model

[0005] The purpose of the present disclosure is to propose a semiconductor structure to solve at least one of the above problems.

[0006] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first active region, a second active region, a plurality of metal gate structures, an insulating structure, a plurality of source / drain contacts, and a feedthrough via. The first active region and the second active region extend longitudinally along a first direction. The plurality of metal gate structures are located over a plurality of channels of the first active region and the second active region and extend longitudinally along a second direction perpendicular to the first direction. The insulating structure cuts through the plurality of metal gate structures and extends longitudinally along the first direction, and the insulating structure is disposed between the first active region and the second active region along the second direction. The plurality of source / drain contacts are located over the insulating structure and a plurality of source / drain components of the first active region and the second active region and extend longitudinally along the second direction. The feedthrough via contacts a bottom surface of the plurality of source / drain contacts and penetrates through a portion of the insulating structure. Wherein, the insulating structure surrounds the feedthrough via and isolates the feedthrough via from the plurality of metal gate structures.

[0007] According to one embodiment of the present disclosure, it further includes: an isolation structure that separates the first active region from the second active region along the second direction; and an interlayer dielectric layer located over the isolation structure, wherein the insulating structure cuts through the isolation structure and the interlayer dielectric layer.

[0008] According to one embodiment of the present disclosure, along the second direction, the insulating structure directly contacts the feedthrough via and the interlayer dielectric layer and is directly located between the feedthrough via and the interlayer dielectric layer, and along the second direction, the insulating structure directly contacts the feedthrough via and the isolation structure and is directly located between the feedthrough via and the isolation structure.

[0009] According to one embodiment of the present disclosure, each of the plurality of source / drain contacts lands on a top surface and a side surface of the plurality of source / drain components

[0010] According to one embodiment of the present disclosure, the insulating structure has a first width along the second direction, the feedthrough via has a second width along the second direction, and the first width is greater than the second width.

[0011] Another aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first active region, a second active region, an isolation structure, a metal gate structure, an insulating structure, and a feed-through via. The first active region has a plurality of first semiconductor channels and a plurality of first source / drain components adjacent to the plurality of first semiconductor channels. The second active region has a plurality of second semiconductor channels and a plurality of second source / drain components adjacent to the plurality of second semiconductor channels. The isolation structure is located between the first active region and the second active region. The metal gate structure is located over the plurality of first semiconductor channels and the plurality of second semiconductor channels. The insulating structure penetrates through the metal gate structure and the isolation structure. The feed-through via is located under the insulating structure and has a through portion that penetrates through a part of the insulating structure. Wherein, the insulating structure isolates the through portion of the feed-through via from the metal gate structure.

[0012] According to one embodiment of the present disclosure, it further includes: a source / drain contact, located over the plurality of first source / drain components and the plurality of second source / drain components, and directly contacting the plurality of first source / drain components and the plurality of second source / drain components.

[0013] According to one embodiment of the present disclosure, the feed-through via is located under the source / drain contact and directly contacts the source / drain contact.

[0014] According to one embodiment of the present disclosure, the source / drain contact is disposed along the top surface and the side surfaces of the plurality of first source / drain components and the plurality of second source / drain components.

[0015] According to one embodiment of the present disclosure, the first active region includes a plurality of third source / drain components, and the second active region includes a plurality of fourth source / drain components. The semiconductor structure further includes: a second source / drain contact, located over the plurality of third source / drain components and the plurality of fourth source / drain components, and directly contacting the plurality of third source / drain components and the plurality of fourth source / drain components, wherein the feed-through via is also located under the second source / drain contact and directly contacts the second source / drain contact. Description of the Drawings

[0016] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practices, various components are not drawn to scale and are only used for illustration. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention.

[0017] Figure 1A semiconductor structure having a feedthrough hole surrounded by a cut-metal-gate structure is shown according to one embodiment of the present disclosure.

[0018] Figure 2 The invention is a flow chart showing a method for forming a semiconductor structure having a feedthrough hole surrounded by a cut metal gate structure according to an embodiment of the present invention.

[0019] Figure 3 The present invention is a flowchart showing a method for forming a feedthrough hole surrounded by a cut metal gate structure according to an embodiment of the present invention.

[0020] Figures 4A to 4D , Figures 5A to 5D , Figures 6A to 6D , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9C , Figures 10A to 10C , Figure 10A-1 , Figure 10B-1 , Figure 10C-1 , Figure 11A , Figure 11A-1 , Figures 11B to 11D ,and Figures 12A to 12C According to one embodiment of the present disclosure, different top views and cross-sectional views of a semiconductor structure are shown, wherein the semiconductor structure is at an intermediate stage of manufacturing and is based on Figure 2 The formation method is processed.

[0021] Figures 13A to 13C The semiconductor structure of the embodiment is shown along Figure 11A A cross-sectional view taken by line segment BB', line segment CC' and line segment DD'.

[0022] Figures 14A to 14C Another embodiment of the semiconductor structure is shown along Figure 11A A cross-sectional view taken by line segment BB', line segment CC' and line segment DD'.

[0023] The reference numerals are as follows:

[0024] 100:Semiconductor structure

[0025] 102:Substrate

[0026] 103: Isolation Structure

[0027] 106: Active area

[0028] 106a: Source / drain component

[0029] 106b: Semiconductor Channel

[0030] 107,109: Interlayer dielectric layer

[0031] 108: Metal gate structure

[0032] 110, 110a: Cut metal gate structure

[0033] 111, 113: Film layer

[0034] 112: Source / drain contact

[0035] 114: Feedthrough hole

[0036] 120: Backside metal structure

[0037] 200: Method

[0038] 202~212: Operations

[0039] 210-1~210-6: Steps

[0040] 402: Second substrate

[0041] 415: Feedthrough hole trench

[0042] 500: Interconnect layer

[0043] B-B’, C-C’, D-D’: Line segments

[0044] s1: Spacing

[0045] y1, y2: Widths Detailed implementation manners

[0046] The following disclosure provides different embodiments or examples for implementing different components of the provided subject matter. Specific examples of each component and its configuration are described below to simplify the description of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present disclosure. For example, if it is mentioned in the description that the first component is formed on the second component, it may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components are formed between the first and second components such that they are not in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and is not used to represent the relationship between different embodiments and / or configurations discussed.

[0047] This document may use spatial relative terms, such as "beneath", "under", "below", "lower", "above", "upper", etc., to facilitate the description of the relationship between one or more elements or components in the drawings. Spatial relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatial relative descriptions used herein can also be interpreted according to the turned orientation.

[0048] In addition, when using terms such as "about" or "approximate" to describe a number or a range of numbers, this term is intended to cover numbers within a reasonable range, such as within + / - 10% of the stated number, or other values recognized by those skilled in the art. For example, the term "about 5 nm" can cover a size range from 4.5 nm to 5.5 nm.

[0049] The present disclosure relates to a semiconductor structure having a feedthrough hole directly formed between active regions. No additional dummy structure is formed between the feedthrough hole and the active regions, thereby reducing the pitch between the active regions. To ensure proper isolation between the feedthrough hole and the active metal gate, the feedthrough hole is formed within a cut-metal-gate structure, and the cut-metal-gate structure surrounds the feedthrough hole. The cut-metal-gate component can cut through not only the active metal gate but also the interlayer dielectric (ILD) layer and the isolation structure (or a part thereof). By properly patterning and forming the cut-metal-gate structure, the feedthrough hole is seamlessly integrated with the active regions. Since no feedthrough hole is formed in the isolation unit, the feedthrough hole can directly contact the source / drain contact. The source / drain contact can be a slot source / drain contact that contacts a plurality of source / drain components. This provides a direct vertical route for signals to move from the back side of the semiconductor structure to the source / drain components. It should be noted that the cut-metal-gate structure also isolates adjacent source / drain contacts.

[0050] Figure 1 A semiconductor structure 100 is shown, which has a feedthrough hole 114 surrounded by a cut-metal-gate (CMG) structure 110. The semiconductor structure 100 includes active regions 106 that extend longitudinally along the x direction. The active regions 106 include a channel region (the region under the metal gate structure 108) and source / drain (S / D) regions adjacent to the channel region. The active regions 106 can be from a substrate (e.g., Figures 4B to 4DA fin-shaped active region protruding from the substrate 102) in it. Each channel region may include a stack of semiconductor channels for a gate-all-around semiconductor device. Alternatively, each channel region may include a single fin-shaped channel for a fin semiconductor device. The S / D regions adjacent to the channel regions include epitaxial S / D components.

[0051] Continuing to refer to Figure 1 , the semiconductor structure 100 includes a metal gate structure 108 that extends longitudinally along the y direction and is disposed over the channel regions of the active regions 106. For a gate-all-around semiconductor device, each metal gate structure 108 wraps around the stack of semiconductor channels in the channel region. For a fin semiconductor device, each metal gate structure 108 wraps around the top and sides of the fin-shaped channel protruding from the substrate.

[0052] Continuing to refer to Figure 1 , the semiconductor structure 100 includes a cut metal gate (CMG) structure 110 that cuts through the metal gate structure 108 and extends longitudinally along the x direction. The CMG structure 110 is a dielectric component, and it cuts the plurality of metal gate structures 108 into smaller gate portions. The CMG structure 110 may also be referred to as the insulating structure 110. Although several CMG structures 110 are shown, the present disclosure relates to the central CMG structure 110a formed between adjacent active regions 106. Since the CMG structure 110a is formed between adjacent active regions 106, the CMG structure 110a has a width y2 that is less than the pitch s1 between adjacent active regions 106. In one embodiment, the pitch s1 is about 100 nm.

[0053] Continuing to refer to Figure 1 , the semiconductor structure 100 includes S / D contacts 112 that are formed over the CMG structure 110a and over the epitaxial S / D components of the active regions 106. As shown, the S / D contacts 112 may be trench-shaped S / Ds that extend longitudinally along the y direction. The S / D contacts 112 land on the S / D components of the active regions 106. In some embodiments, as shown in the embodiment, a single S / D contact 112 may land on the S / D components in a plurality of active regions 106.

[0054] Continuing to refer to Figure 1 , the semiconductor structure 100 includes feedthrough vias 114 that contact the bottom surface of the S / D contacts 112 and penetrate through a portion of the CMG structure 110a. The feedthrough vias 114 are formed on the back side of the semiconductor structure 100 and are disposed below the S / D contacts 112 and the non-penetrated portion of the CMG structure 110a. The feedthrough vias 114 electrically couple the S / D components in the S / D regions to back-side metal lines (not shown).

[0055] Continuing to refer to Figure 1 , the CMG structure 110a surrounds the feedthrough 114 and isolates the feedthrough 114 from the metal gate structure 108. To ensure proper isolation, the width y2 of the CMG structure 110a must be sufficiently greater than the width y1 of the feedthrough 114. In one embodiment, the CMG structure 110a extends beyond the feedthrough 114 by at least 10 nm on either side of the feedthrough 114. Thus, the width y2 is at least 20 nm greater than the width y1. If the CMG structure 110a does not extend far enough (e.g., less than 8 nm on either side of the feedthrough), there is a risk of shorting of the metal gate structure 108. On the other hand, the width y2 of the CMG structure 110a cannot be too large, which risks cutting into the gate portion of the metal gate structure 108, where the metal gate structure 108 is directly above the channel region of the active region 106. In one embodiment, the CMG structure 110a extends beyond the feedthrough 114 by at most 20 nm in width on either side of the feedthrough 114. Thus, the width y2 is at most 40 nm greater than the width y1. If the CMG structure 110a extends too far (e.g., greater than 45 nm on either side of the feedthrough), there is a risk of cutting through the channel region of the active region 106. To leave sufficient space in the y-direction in the CMG structure 110a, which must be large enough to surround the feedthrough 114, the spacing s1 between adjacent active regions should be greater than twice the width y1 of the feedthrough 114. In one embodiment, the width y1 is between 20 nm and 50 nm, and the spacing s1 is approximately 100 nm. In some embodiments, the ratio of s1 / y2 is between 2 and 5, and the ratio of y2 / y1 is between 1.4 and 3.

[0056] Figure 2 is a flowchart of a method 200 for forming a semiconductor structure 100 having a feedthrough 114 surrounded by a cut metal gate structure 110a. The following refers to Figures 4A to 12C to describe the method 200, which shows different top views and cross-sectional views of the semiconductor structure 100, where the semiconductor structure 100 is in an intermediate stage of manufacture and is processed according to the method 200. Additional operations may be provided before, during, and after the method 200, and some of the described operations may be moved, replaced, or omitted for additional embodiments of the method 200.

[0057] Figure 4A shows a top view of the semiconductor structure 100. Figures 4B to 4D shows Figure 4A cross-sectional views of the semiconductor structure 100 in Figure 4A, Method 200 receives a workpiece at operation 202, which has an active region 106 longitudinally extending along the x-direction. Figure 4A Shows two active regions 106 separated by an interlayer dielectric (ILD) layer 107. Continuing with reference to Figure 4A , Method 200 forms a metal gate structure 108 over the channel region of the active region 106 at operation 204. The metal gate structure 108 longitudinally extends along the y-direction. The metal gate structure 108 is separated by the ILD layer 107. The ILD layer 107 (and other ILD layers described herein) may include an oxide formed from tetraethylorthosilicate, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluoride-doped silica glass (FSG), phosphosilicate glass (PSG), boron doped siliconglass (BSG), low dielectric constant (low-k) dielectric material, other suitable dielectric materials, or a combination thereof. In one embodiment, the ILD layer 107 is formed of a low-k dielectric material having a silicon nitride liner (not shown).

[0058] Now referring to Figures 4B to 4D , The active region 106 is disposed over the substrate 102. The substrate 102 may be a silicon (Si) substrate, or a substrate having other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. In one embodiment, the active region 106 is a protruding portion of the substrate 102. Figure 4C Shows a cross-sectional view of the source / drain (S / D) region of the active region 106, and Figure 4D shows a cross-sectional view of the channel region of the active region 106. In both cases, an isolation structure 103 is disposed over the substrate 102, and the isolation structure 103 isolates adjacent active regions 106 from each other. The isolation structure 103 may be a shallow trench isolation (STI) structure having a dielectric material such as silicon oxide, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric, a combination thereof, and / or other suitable materials. In one embodiment, the isolation structure 103 is formed of silicon oxide. In Figure 4BIn the cross-sectional view, a plurality of metal gate structures 108 are located on the isolation structure 103. An ILD layer 107 is formed on the isolation structure 103, where the ILD layer 107 separates the metal gate structures 108, and the ILD layer 107 also lies on the isolation structure 103.

[0059] Now referring to Figure 4C , an S / D component 106a is formed on the S / D regions of the active region 106. The S / D component 106a may include an n-type epitaxial S / D component corresponding to an n-type S / D region or a p-type epitaxial S / D component corresponding to a p-type S / D region. Adjacent S / D components 106a are separated by the ILD layer 107 formed on the isolation structure 103.

[0060] Now referring to Figure 4D , a semiconductor channel 106b is formed on the channel region of the active region 106. The illustrated embodiment relates to a fully wrapped gate semiconductor device having a stack of semiconductor channels 106b on each channel region. Alternatively, for a fin-type semiconductor device, a single fin-shaped channel may be provided on the channel region. A metal gate structure 108 is disposed on the semiconductor channel 106b and wraps around the semiconductor channel 106b. Metal gate structures 108 are provided on multiple channel regions.

[0061] Now referring to Figure 5A (which shows a top view), method 200 forms a cut metal gate (CMG) structure 110a at operation 206 between two active regions 106 (i.e., the illustrated active regions). The CMG structure 110a extends longitudinally along a first direction and cuts through a plurality of metal gate structures. The CMG structure 110a can be formed by first forming a CMG trench that passes through the metal gate structure 108, the ILD layer 107, and a portion of the isolation structure 103, and then filling the CMG trench with a CMG dielectric material. The CMG trench is formed by a suitable patterning process and a lithography process, and the CMG dielectric material may include silicon oxide, silicon oxynitride, fluorinated silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. It should be noted that, as shown, additional CMG structures 110 may be formed, and they may extend longer in the x direction than the CMG structure 110a. These CMG structures 110 isolate the gate region from other gate regions.

[0062] Figures 5B to 5D Showing Figure 5A the cross-sections of the semiconductor structure 100 in [[]] taken along line segments B-B’, C-C’, and D-D’ respectively. Now referring to Figures 5B to 5D, the CMG structure 110a cuts through the metal gate structure 108, the ILD layer 107, and the isolation structure 103 to directly contact the substrate 102. In this embodiment, the CMG structure 110a is formed to completely penetrate the isolation structure 103. In another embodiment, the CMG structure 110a is formed to partially penetrate the isolation structure 103. And in yet another embodiment, the CMG structure 110a is formed to further penetrate into a part of the substrate 102. In all cases, the CMG structure 110a must penetrate the isolation structure 103 to a sufficient depth to prepare for the formation of the feedthrough via, as explained in more detail below.

[0063] Referring to Figure 5B , the CMG structure 110a longitudinally spans over the substrate 102 along the x direction, thereby replacing Figure 4B the isolation structure 103, the ILD layer 107, and the metal gate structure 108 shown. Referring to Figure 5C , the CMG structure 110a penetrates through the ILD layer 107 and the isolation structure 103 to land on the substrate 102. However, a part of the ILD layer 107 and the isolation structure 103 is still retained. The remaining part of the ILD layer 107 isolates the CMG structure 110a from the S / D components 106a along the y direction. The remaining part of the isolation structure 103 isolates the CMG structure 110a from the S / D regions of the active region 106 along the y direction. Referring to Figure 5D , the CMG structure 110a penetrates through one of the metal gate structures 108 and through the isolation structure 103 to land on the substrate 102. The CMG structure 110a divides the metal gate structure 108 into two parts. The remaining part of the isolation structure 103 isolates the CMG structure 110a from the channel region of the active region 106 along the y direction.

[0064] Now referring to Figure 6A (showing a top view), the method 200 forms source / drain (S / D) contacts 112 on the CMG structure 110a and on the S / D regions of the first active region 106 and the second active region 106 at operation 208. As shown, the S / D contacts 112 can be groove-shaped contacts that longitudinally extend between the metal gate structures 108 along the second direction. The S / D contacts directly contact the CMG structure 110a and directly contact the S / D components 106a on the S / D regions of the active region 106.

[0065] Figures 6B to 6D Showing Figure 6A the cross-sectional views of the semiconductor structure 100 in Figures 6B to 6D, the S / D contact 112 can be formed by first forming the ILD layer 109 over the workpiece (i.e., over the CMG structure 110a, the S / D device 106a, and the metal gate structure 108). Then, an S / D trench is formed through the ILD layer 109 and a portion of the CMG structure 110a. Then, the S / D trench is filled with a metal material to form the S / D contact 112. The workpiece can then be planarized by a CMP process. The S / D trench is formed by a suitable patterning process and a lithography process, and the metal material for the S / D contact 112 can include any suitable metal, such as tungsten or cobalt. In some embodiments, the S / D contact 112 can additionally include a barrier layer, such as titanium and titanium nitride.

[0066] Referring to Figure 6B , the S / D contact 112 extends partially into the CMG structure 110a. As shown, multiple S / D contacts 112 are isolated from each other along the x direction by the CMG structure 110a and the ILD layer 109. Referring to Figure 6C , the same S / D contact 112 can land on multiple S / D devices 106a. In one embodiment, the S / D contact 112 lands on the top surface and the side surface of the S / D device 106a. In this case, the S / D contact 112 is formed to further penetrate into the CMG structure 110a and into the ILD layer 107. In this way, there is more surface contact between the S / D contact 112 and the S / D device 106a to achieve a lower contact resistance. Referring to Figure 6D , after the S / D contact 112 is formed, the ILD layer 109 is retained over the metal gate structure 108 and the CMG structure 110a. Referring to Figures 6B to 6D , after the planarization process, the top surface of the ILD layer 109 is coplanar with the top surface of the S / D contact 112.

[0067] Now referring to Figures 7A to 7C, Method 200 may perform additional operations to form interconnects (or interconnect layer 500) over the workpiece. Interconnect 500 includes components electrically coupled to S / D contacts 112 and metal gate structure 108 such that various devices and / or components can operate as specified by the design requirements. Interconnect layer 500 includes a combination of dielectric layers and conductive layers (e.g., metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect components and / or horizontal interconnect components, where vertical interconnect components such as device-level contacts and / or vias, and horizontal interconnect components such as wires. Vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the interconnect layer. During operation, interconnect layer 500 is configured to route signals between devices and / or components of semiconductor structure 100, and / or distribute signals (e.g., timing signals, voltage signals, and / or ground signals) to devices and / or components of semiconductor structure 100.

[0068] Jump to Figure 11A (which shows a top view), Method 200 forms a feedthrough via 114 at operation 210 that contacts the bottom surface of S / D contact 112 and penetrates a portion of CMG structure 110a. Feedthrough via 114 is formed within CMG structure 110a and is surrounded by CMG structure 110a. CMG structure 110a isolates feedthrough via 114 from metal gate structure 108. Feedthrough via 114 extends longitudinally along the x direction to contact one or more S / D contacts 112. The details of the formation of feedthrough via 114 will be described hereinafter with reference to Figure 3 to describe the formation details of feedthrough via 114. Figure 3 A flowchart showing the method of forming feedthrough via 114. This method splits operation 210 into further steps 210-1 to step 210-6.

[0069] Now refer to Figures 8A to 8C , At step 210-1 of operation 210, a bonding process is performed. The bonding process includes flipping the workpiece of semiconductor structure 100 and bonding it to a second substrate 402. In this orientation, the z direction is now facing up. Continuing to refer to Figures 8A to 8C , At step 210-2 of operation 210, a thinning process is performed to expose CMG structure 110a. The thinning process can be a CMP process, a debonding process, or other suitable process. In the illustrated embodiment, the thinning process removes substrate 102 to expose CMG structure 110a.

[0070] Now refer to Figures 9A to 9C, Operation 210 forms a hard mask layer on the exposed CMG structure 110a at step 210-3. As shown, according to some embodiments, the hard mask layer may include a silicon nitride layer (i.e., film layer 111) and a silicon oxide layer (i.e., film layer 113). These film layers are formed by any suitable deposition technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), remote plasma chemical vapor deposition (RPCVD), plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), atmospheric pressure chemical vapor deposition (APCVD), electroplating, other suitable methods, or a combination thereof.

[0071] Now referring to Figures 10A to 10C , Operation 210 forms a via trench 415 at step 210-4, which passes through the hard mask layer and the CMG structure 110a. The hard mask layer (i.e., film layer 111 and film layer 113) can be patterned to form an opening by first performing a lithography process and an etching process, and then the via trench 415 passing through the CMG structure 110a is formed by etching using the patterned hard mask layer as an etching mask. As Figure 10A shown, the via trench 415 (shown by the dashed box) exposes the top surface of the S / D contact 112 and the top surface of the CMG structure 110a. In this view, the top surface of the S / D contact 112 may be coplanar with the top horizontal surface of the CMG structure 110a. As Figure 10BAs shown, the via trench 415 exposes the side surfaces of the hard mask layers (i.e., the film layers 111 and 113), the side surface of the CMG structure 110a, and the horizontal surface of the S / D contact 112. In this view, the via trench 415 completely penetrates the CMG structure 110a to expose the S / D contact 112. As Figure 10C As shown, the via trench 415 exposes the side surfaces of the hard mask layers (i.e., the film layers 111 and 113), the side surface of the CMG structure 110a, and the horizontal surface of the CMG structure 110a. In this view, the via trench 415 only partially penetrates the CMG structure 110a. The via trench 415 is formed such that no part of the metal gate structure 108 is exposed.

[0072] Now referring to Figures 10A-1 to 10C-1 , which shows another embodiment of forming the via trench 415. Specifically referring to FIG. 10A-1, the CMG structure 110a can be patterned (by selective patterning of the hard mask film layers 111 and 113) and etched such that some of the S / D contacts 112 are exposed and other S / D contacts 112 remain covered. As shown, the CMG structure 110a can then isolate the covered S / D contacts from the exposed S / D contacts. In this embodiment, multiple via trenches 415 can be formed.

[0073] Now referring to Figure 11A (which shows a top view), operation 210 deposits a metal material into the via trench 415 at step 210-5 as Figures 10A to 10C shown to form the via 114. Figure 11A Similar to Figure 1 , and for the sake of brevity will not be described again Figure 11A . Now referring to Figure 11A-1 , in another embodiment, multiple vias 114 are formed. This follows the embodiment shown in Figures 10A-1 to 10C-1 . In this case, the multiple vias 114 are isolated by the CMG structure 110a.

[0074] Figures 11B to 11D Shows Figure 11A cross-sectional views of the semiconductor structure 100 in Figures 11B to 11D taken along line B-B', line C-C', and line D-D', respectively. Referring to Figures 11B to 11D , operation 210 performs a planarization process (e.g., CMP) at step 210-6 to planarize the via 114 such that the top surface of the via 114 is coplanar with the top surface of the hard mask layers (i.e., the film layers 111 and 113). In another embodiment, the hard mask film layers 111 and 113 are removed, and the planarization process can planarize the via 114 such that the top surface of the via 114 is coplanar with the top surface of the active region 106.

[0075] Referring to Figure 11B , the feedthrough via 114 lands on the top surface of the S / D contact 112 and the top surface of the CMG structure 110a, and directly contacts the top surface of the S / D contact 112 and the top surface of the CMG structure 110a. In the illustrated embodiment, the feedthrough via 114 lands on multiple S / D contacts 112 simultaneously and is coupled to the multiple S / D contacts 112. In other embodiments, when forming the feedthrough via trench 415, only some of the S / D contacts 112 are exposed while maintaining other S / D contacts 112 covered (referring to Figure 10A-1 ), the feedthrough via 114 can land on some of the S / D contacts 112 and be isolated from other S / D contacts 112 by the CMG structure 110a. Referring to Figure 11C , the feedthrough via 114 penetrates through and directly contacts the side surfaces of the hard mask layers (i.e., the film layers 111 and 113), the side surface of the CMG structure 110a, and the horizontal surface of the S / D contact 112. In this view, a portion of the CMG structure 110a is retained midway between the feedthrough via 114 and the ILD layer 107 and midway between the feedthrough via 114 and the isolation structure 103. Referring to Figure 11D , the feedthrough via 114 penetrates through and directly contacts the side surfaces of the hard mask layers (i.e., the film layers 111 and 113), the side surface of the CMG structure 110a, and the horizontal surface of the CMG structure 110a. In this view, a portion of the CMG structure 110a is retained midway between the feedthrough via 114 and the isolation structure 103. Continuing to refer to Figure 11D , the feedthrough via 114 is embedded within the CMG structure 110a and surrounded by the CMG structure 110a such that the feedthrough via 114 is isolated from the metal gate structure 108. To this end, the CMG structure 110a should be wider in the y direction than the portion of the feedthrough via 114 that penetrates the CMG structure 110a.

[0076] Now referring to Figures 12A to 12C , method 200 forms a backside metal structure 120 at operation 212 that contacts the feedthrough via 114. The backside metal structure 120 can include a backside power rail or other metal lines and interconnects to couple to the S / D contacts 112 from the backside of the workpiece. Method 200 can perform further steps to complete the fabrication of the semiconductor structure 100. Additional operations can be provided before, during, and after method 200, and some of the described operations can be moved, replaced, or removed for additional embodiments of method 200.

[0077] Figures 13A to 13C Shows the same as Figures 12A to 12CThe semiconductor structure 100 shown, but for purposes of explanation, the semiconductor structure 100 is flipped back to the positive z - direction. In this orientation, vias 114 are formed below the bottom surface of the S / D contact 112 and below a portion of the CMG structure 110a (i.e., the portion that is not penetrated). The vias 114 are formed such that they are surrounded by the inner surface of the CMG structure 110a along the y - direction. The CMG structure 110a directly contacts the S / D contact 112, the ILD layer 107, the isolation structure 103, the metal gate structure 108, and the ILD layer 109. In this embodiment, the CMG structure 110a completely penetrates the isolation structure, and the CMG structure 110a can also isolate the vias 114 to prevent them from contacting the isolation structure 103.

[0078] Figures 14A to 14C Another embodiment showing the semiconductor structure 100 is presented, which has vias 114 surrounded by the CMG structure 110a. Figures 14A to 14C Similar to Figures 13A to 13C , except that the CMG structure 110a only partially penetrates the isolation structure 103. As previously mentioned, as long as the CMG structure 110a penetrates into the isolation structure 103 to a sufficient depth (i.e., a depth that cuts through the metal gate structure and isolates the vias 114), the CMG structure 110a does not need to completely penetrate the isolation structure 103. In one embodiment, the penetration depth should be at least half of the height of the isolation structure 103. For the case where the CMG structure 110a only partially penetrates the isolation structure 103, the vias 114 can further directly contact the inner surface of the isolation structure 103.

[0079] The isolation structure 103, the ILD layer 107, the ILD layer 109, and the CMG structure 110a have been described as including various dielectric materials. In one embodiment, the isolation structure 103, the ILD layer 107, the ILD layer 109, and the CMG structure 110a have different dielectric materials for etch selectivity. For example, the isolation structure 103 includes silicon oxide, the ILD layers 107 and 109 include low - k dielectric materials lined with an etch - stop nitride layer, and the CMG structure 110a includes silicon oxynitride. The different materials allow for etch selectivity during the etching process to form the different trenches described herein (e.g., CMG trenches, S / D trenches, and via trenches). If there is an overlay shift, the different compositions and etch selectivities will confine the etching within the CMG structure 110a.

[0080] While not limiting, the present disclosure provides advantageous effects of semiconductor structures having feedthrough vias. One example advantageous effect is forming the feedthrough vias directly between adjacent active regions rather than in a separate feedthrough cell region, thereby saving space. Another example advantageous effect is forming the feedthrough vias within a cut metal gate structure and surrounding the feedthrough vias with the cut metal gate structure, where the cut metal gate structure isolates the feedthrough vias from the metal gates. Another example advantageous effect is having the feedthrough vias directly contact source / drain contacts to provide a direct signal routing from the backside of the semiconductor structure to the source / drain components. Another example advantageous effect is that the cut metal gate structure can also isolate adjacent source / drain contacts for selectively coupling the feedthrough vias to the source / drain contacts.

[0081] One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first active region and a second active region longitudinally extending along a first direction, and a plurality of metal gate structures located over a plurality of channels of the first active region and the second active region. The plurality of metal gate structures longitudinally extend along a second direction perpendicular to the first direction. The semiconductor structure includes an insulating structure cutting through the plurality of metal gate structures and longitudinally extending along the first direction. The insulating structure is disposed between the first active region and the second active region along the second direction. The semiconductor structure includes a plurality of source / drain contacts located over the insulating structure and the plurality of source / drain components of the first active region and the second active region. The plurality of source / drain contacts longitudinally extend along the second direction. The semiconductor structure includes a feedthrough via contacting a bottom surface of the plurality of source / drain contacts and penetrating through a portion of the insulating structure. The insulating structure surrounds the feedthrough via and isolates the feedthrough via from the plurality of metal gate structures.

[0082] In one embodiment, an isolation structure separates the first active region from the second active region along the second direction, and an interlayer dielectric layer is located over the isolation structure. The insulating structure cuts through the isolation structure and the interlayer dielectric layer. In another embodiment, along the second direction, the insulating structure directly contacts the feedthrough via and the interlayer dielectric layer and is directly located between the feedthrough via and the interlayer dielectric layer; and along the second direction, the insulating structure directly contacts the feedthrough via and the isolation structure and is directly located between the feedthrough via and the isolation structure.

[0083] In one embodiment, each of the plurality of source / drain contacts lands on a top surface and a side surface of the plurality of source / drain components. In one embodiment, along the second direction, the insulating structure extends beyond the feedthrough via on either side of the feedthrough via by at least 10 nm. In one embodiment, along the second direction, the insulating structure extends beyond the feedthrough via on either side of the feedthrough via by at most 20 nm.

[0084] In one embodiment, the insulating structure has a first width along a second direction, the feed-through hole has a second width along the second direction, and the first width is greater than the second width. In another embodiment, the first width is at least 20 nm greater than the second width. In yet another embodiment, the spacing between the first active region and the second active region is greater than twice the second width. In yet another embodiment, the spacing between the first active region and the second active region is approximately 100 nm. In yet another embodiment, the second width is between 20 nm and 50 nm.

[0085] Another aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first active region having a plurality of first semiconductor channels and a plurality of first source / drain components adjacent to the plurality of first semiconductor channels. The semiconductor structure includes a second active region having a plurality of second semiconductor channels and a plurality of second source / drain components adjacent to the plurality of second semiconductor channels. The semiconductor structure includes an isolation structure located between the first active region and the second active region. The semiconductor structure includes a metal gate structure located over the plurality of first semiconductor channels and the plurality of second semiconductor channels. The semiconductor structure includes an insulating structure that cuts through the metal gate structure and the isolation structure. The semiconductor structure includes a feed-through hole located under the insulating structure. The feed-through hole has a through portion that penetrates a part of the insulating structure, and the insulating structure isolates the through portion of the feed-through hole from the metal gate structure.

[0086] In one embodiment, the semiconductor structure further includes source / drain contacts. The source / drain contacts are located over the plurality of first source / drain components and the plurality of second source / drain components and directly contact the plurality of first source / drain components and the plurality of second source / drain components. In another embodiment, the feed-through hole is located under the source / drain contacts and directly contacts the source / drain contacts. In one embodiment, the source / drain contacts are disposed along the top surface and the side surfaces of the plurality of first source / drain components and the plurality of second source / drain components. In one embodiment, the first active region includes a plurality of third source / drain components, and the second active region includes a plurality of fourth source / drain components. The semiconductor structure further includes second source / drain contacts. The second source / drain contacts are located over the plurality of third source / drain components and the plurality of fourth source / drain components and directly contact the plurality of third source / drain components and the plurality of fourth source / drain components. Wherein the feed-through hole is also located under the second source / drain contacts and directly contacts the second source / drain contacts.

[0087] Another aspect of the present disclosure relates to a method of forming a semiconductor structure. The method of forming the semiconductor structure includes receiving a workpiece, where the workpiece has a plurality of active regions located above a substrate and isolation structures separating the plurality of active regions, and the plurality of active regions extend longitudinally along a first direction. The method of forming the semiconductor structure includes forming a plurality of metal gate structures above a plurality of channel regions of the plurality of active regions, where the plurality of metal gate structures extend longitudinally along a second direction perpendicular to the first direction. The method of forming the semiconductor structure includes forming an insulating structure between two of the plurality of active regions, where the insulating structure extends longitudinally along the first direction and cuts through a plurality of the plurality of metal gate structures to separate a plurality of first portions of the plurality of metal gate structures from a plurality of second portions of the plurality of metal gate structures. The method of forming the semiconductor structure includes forming a plurality of source / drain contacts above the insulating structure and the plurality of source / drain regions of a first active region and a second active region, where the plurality of source / drain contacts extend longitudinally along the second direction. The method of forming the semiconductor structure includes forming a feedthrough via, where the feedthrough via contacts a bottom surface of the plurality of source / drain contacts and penetrates a portion of the insulating structure. The insulating structure surrounds the feedthrough via and isolates the feedthrough via from the plurality of metal gate structures.

[0088] In one embodiment, the plurality of source / drain contacts are slot source / drain contacts separated from each other by the insulating structure, and each of the plurality of source / drain contacts lands on a plurality of source / drain components of the plurality of source / drain regions.

[0089] In one embodiment, the step of forming the feedthrough via further includes: performing an etching process on the insulating structure to form a feedthrough via trench in the insulating structure such that the plurality of source / drain contacts are exposed within the feedthrough via trench; depositing a conductive material in the feedthrough via trench; and performing a planarization process to form the feedthrough via.

[0090] In one embodiment, after forming the feedthrough via, a portion of the insulating structure remains between the feedthrough via and the isolation structure along the second direction.

[0091] The above outlines the components of several embodiments so that those skilled in the art to which the present invention pertains can more easily understand the viewpoints of the embodiments of the present invention. Those skilled in the art to which the present invention pertains should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as those introduced herein. Those skilled in the art to which the present invention pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, Comprising: A first active region and a second active region, longitudinally extending along a first direction; A plurality of metal gate structures, located above a plurality of channels of the first active region and the second active region, wherein the plurality of metal gate structures longitudinally extend along a second direction perpendicular to the first direction; An insulating structure, cutting through the plurality of metal gate structures and longitudinally extending along the first direction, wherein the insulating structure is disposed between the first active region and the second active region along the second direction; A plurality of source / drain contact members, located above the insulating structure and a plurality of source / drain components of the first active region and the second active region, wherein the plurality of source / drain contact members longitudinally extend along the second direction; and A feed through hole, contacting a bottom surface of the plurality of source / drain contact members and penetrating through a part of the insulating structure, wherein the insulating structure surrounds the feed through hole and isolates the feed through hole from the plurality of metal gate structures.

2. The semiconductor structure according to claim 1, wherein, Further comprising: An isolation structure, separating the first active region from the second active region along the second direction; And An interlayer dielectric layer, located above the isolation structure, wherein the insulating structure cuts through the isolation structure and the interlayer dielectric layer.

3. The semiconductor structure according to claim 2, wherein, along the second direction, the insulating structure directly contacts the feed through hole and the interlayer dielectric layer, and is directly located between the feed through hole and the interlayer dielectric layer, and along the second direction, the insulating structure directly contacts the feed through hole and the isolation structure, and is directly located between the feed through hole and the isolation structure.

4. The semiconductor structure according to claim 1, wherein, Each of the plurality of source / drain contact members lands on a top surface and a side surface of the plurality of source / drain components.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The insulating structure has a first width along the second direction, the feed through hole has a second width along the second direction, and the first width is greater than the second width.

6. A semiconductor structure, characterized in that, Comprising: A first active region, having a plurality of first semiconductor channels and a plurality of first source / drain components adjacent to the plurality of first semiconductor channels; A second active region, having a plurality of second semiconductor channels and a plurality of second source / drain components adjacent to the plurality of second semiconductor channels; An isolation structure, located between the first active region and the second active region; A metal gate structure, located above the plurality of first semiconductor channels and the plurality of second semiconductor channels; An insulating structure, cutting through the metal gate structure and the isolation structure; and A feed through hole, located below the insulating structure, wherein the feed through hole has a through portion penetrating through a part of the insulating structure, and the insulating structure isolates the through portion of the feed through hole from the metal gate structure.

7. The semiconductor structure as described in claim 6, wherein Further comprising: A source / drain contact member, located above the plurality of first source / drain components and the plurality of second source / drain components, and directly contacting the plurality of first source / drain components and the plurality of second source / drain components.

8. The semiconductor structure according to claim 7, wherein The feed through hole is located below the source / drain contact member and directly contacts the source / drain contact member.

9. The semiconductor structure according to claim 7, wherein, The source / drain contact is disposed along top surfaces and side surfaces of the plurality of first source / drain components and the plurality of second source / drain components.

10. The semiconductor structure according to claim 7, wherein, The first active region includes a plurality of third source / drain components, and the second active region includes a plurality of fourth source / drain components. The semiconductor structure further includes: A second source / drain contact located over the plurality of third source / drain components and the plurality of fourth source / drain components and directly contacting the plurality of third source / drain components and the plurality of fourth source / drain components, wherein the feed-through via is also located under the second source / drain contact and directly contacts the second source / drain contact.

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