Airborne radar signal processing and beam electronic stabilizing device

Abstract

The utility model discloses an airborne radar signal processing and wave beam electronic stabilizing device, which comprises a network port unit, an RS422 serial port unit, an echo AD unit, a servo AD unit, a DSP unit and an FPGA unit, the DSP unit comprises a DSP wave beam stabilizing unit and a DSP signal processing unit, the FPGA unit comprises an FPGA wave beam stabilizing unit and an FPGA signal processing unit, and the DSP wave beam stabilizing unit and the FPGA signal processing unit are respectively connected with the DSP wave beam stabilizing unit and the FPGA signal processing unit. The input end of the DSP signal processing unit is connected to the output end of the FPGA signal processing unit through SRIO. And the output end of the DSP signal processing unit is connected to the internal input end of the network port through a network. According to the utility model, the radar signal processing device and the wave beam stabilizing device are integrated together, through hardware multiplexing, the number of hardware equipment is greatly reduced, connecting lines between the equipment are reduced, the research and development cost and the design complexity are reduced, and the functions of processing radar dual-channel echo signals and electronically stabilizing two-dimensional wave beams in pitching and orientation can be realized; therefore, the three-axis stable platform which is heavy and large in size can be replaced, and the size and the weight are greatly reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of airborne phased array radars, and particularly relates to an airborne radar signal processing and beam electronic stabilization device. Background Technique

[0002] As one of the core sensors of contemporary aviation platforms, airborne radar systems play a crucial role in fields such as target detection and tracking, terrain mapping, and even combat command, due to their excellent maneuverability and the ability to overcome terrain limitations to provide a wider surveillance range. Nowadays, with technological progress and demand upgrades, airborne radar systems are developing towards the directions of miniaturization, high performance, high integration, and low cost.

[0003] Radar signal processing is a core element of modern radar systems, and its performance directly affects the improvement of radar effectiveness and the successful execution of its tasks. It is a key technical support for realizing reliable target detection and tracking, information and data fusion, and information-based and intelligent combat.

[0004] Compared with land-based fixed platforms, airborne radars are extremely prone to causing the antenna beam to deviate from the target area due to frequent changes in aircraft attitudes such as yaw, roll, dive, climb, or motion states such as turning and hovering, thus reducing the radar measurement accuracy or even resulting in target loss. Traditional solutions usually use a three-axis hardware stabilization platform to isolate the radar antenna motion and the aircraft motion, and make the antenna beam direction unaffected by the aircraft attitude through a servo closed-loop circuit; however, this method has problems such as large volume, heavy mass, and high cost. Therefore, there is an urgent need to develop an antenna beam electronic stabilization device.

[0005] Integrating airborne radar signal processing and an electronic beam stabilization system aims to comprehensively improve the working efficiency of the aviation platform and its ability to adapt to future complex scenarios by optimizing the radar system performance, increasing the response speed, enhancing the reliability, and improving the flexibility. This is an important trend in modern avionics system design, which is mainly reflected in the following three aspects:

[0006] 1. Improve system performance: The integrated design can ensure the tight coupling and efficient collaborative work between signal processing and beam control. This helps to adjust the direction and shape of the radar beam in real time to cope with flight attitude changes, airflow disturbances, or target dynamics, thereby improving the radar's target capture rate, tracking accuracy, and data update rate.

[0007] 2. Reduce latency and increase the response speed: After integration, the physical and logical distances between signal processing and beam control are shortened, the signal transmission latency is reduced, and the system's response speed to environmental changes is increased. This is particularly important for fast-moving airborne platforms and can make decisions faster in the rapidly changing combat environment.

[0008] 3. Optimize resources and enhance reliability: After integration, computing resources and data paths are shared, redundant components are reduced, thereby reducing weight and system complexity. At the same time, the integrated design simplifies the system architecture, reduces the number of interfaces, decreases the failure points, and improves the reliability and maintainability of the system.

[0009] In summary, it has become particularly urgent and important to develop a miniaturized, high-performance, highly reliable radar signal processing and electronic beam stabilization system whose volume and weight meet the payload requirements and whose hardware can be reused. Summary of the Invention

[0010] The object of the present invention is to provide an airborne radar signal processing and beam electronic stabilization device that can simultaneously realize the processing of radar dual-channel echo signals and the electronic stabilization function of two-dimensional beams in pitch and azimuth.

[0011] The technical solution adopted by the present invention is as follows:

[0012] An airborne radar signal processing and beam electronic stabilization device includes an Ethernet port unit and an RS422 serial port unit, an echo AD unit and a servo AD unit, a DSP unit, and an FPGA unit, wherein:

[0013] The DSP unit includes a DSP beam stabilization unit and a DSP signal processing unit. The input end of the DSP beam stabilization unit is connected to the output end of the internal Ethernet port pair, and is used to receive the control instruction information sent by the display and control computer, realize the transformation from the beam pointing angle in the geographical coordinate system to the beam pointing angle of the antenna array surface, and calculate the pitch closed-loop control parameters; the output end of the DSP beam stabilization unit is connected to the input end of the FPGA beam stabilization unit, and is used to send the operating frequency, the azimuth angle in the array coordinate system, and the servo control parameters to the FPGA beam stabilization unit for further processing;

[0014] The input end of the DSP signal processing unit is connected to the output end of the FPGA signal processing unit through SRIO, and is used to receive the data information of the sum and difference two-way pulse compression and one-way clutter suppression output by the FPGA; the output end of the DSP signal processing unit is connected to the internal input end of the Ethernet port through the network, and is used to report the target information processed by the DSP to the display and control computer through the network.

[0015] The FPGA unit includes an FPGA beam stabilization unit and an FPGA signal processing unit. The input end of the FPGA beam stabilization unit is connected to the output end of the DSP beam stabilization unit, and is used to read in the azimuth pointing angle in the array coordinate system and the operating frequency and calculate the amplitude-phase control code information of each channel's TR component; the output end of the FPGA beam stabilization unit is connected to the TR component, the frequency synthesizer, and the servo, and is used to realize the control of the TR component in azimuth and the control of the frequency synthesizer and the servo in pitch, thereby realizing the stabilization of the two-dimensional beam pointing;

[0016] The input end of the FPGA signal processing unit is connected to the sum-difference echo AD unit, which is used to read the digitized sum-difference echo data and perform digital down-conversion, pulse compression, and clutter suppression processing; the output end of the FPGA signal processing unit is connected to the input end of the DSP signal processing unit, which is used to send the data information of sum-difference two-way pulse compression and one-way clutter suppression to the DSP through the SRIO bus for further processing.

[0017] The external input / output end of the network port unit is connected to the display and control computer, which is used to receive the control instructions of the display and control computer and report the target data information; the internal output end of the network port unit is connected to the DSP beam stabilization unit, and the internal input end of the network unit is connected to the output end of the DSP signal processing unit, which is used to output the target information through the network.

[0018] The input end of the RS422 serial port unit is connected to the output end of the external inertial navigation, which is used to receive the roll angle, heading angle, and pitch angle information output by the inertial navigation and participate in realizing the transformation function of the pointing angle information issued by the display and control computer to the radar array pointing angle information.

[0019] The input end of the servo AD unit is connected to the output end of the external servo angle, which is used to transfer the digitized current servo angle to the DSP beam stabilization unit from the FPGA beam stabilization unit through the EMIF bus; the input end of the echo AD unit is connected to the output ends of the external sum path echo and difference path echo, which is used to digitally collect the sum-difference two-way echo signals output by the receiver and transfer the digitized intermediate frequency echo to the FPGA signal processing unit.

[0020] The DSP beam stabilization unit includes an instruction receiving and parsing unit, a pointing angle transformation unit, and a pitch closed-loop calculation unit; the input end of the instruction receiving and parsing unit is connected to the internal output end of the network port unit, which is used to read the control instruction information through the network; the output end of the instruction receiving and parsing unit is sequentially connected to the pointing angle transformation unit and the pitch closed-loop calculation unit, which is used to realize the parsing of the input control instruction, the transformation of the pointing angle information issued by the display control unit from the geographic coordinate system to the array coordinate system, the working frequency calculation, and the generation of servo control parameters; the input end of the pointing angle transformation unit is also connected to the output end of the RS422 serial port unit, which is used to read the heading angle, pitch angle, and roll angle information collected by the inertial navigation unit.

[0021] The DSP signal processing unit includes a CFAR processing and detection unit and an angle measurement unit; the input end of the CFAR processing and detection unit is connected to the output end of the FPGA unit through the SRIO, which is used to read the target data after clutter suppression processing; the output of the CFAR processing and detection unit is connected to the input end of the angle measurement unit, which is used to output the target information to the display and control computer through the network after angle measurement processing.

[0022] The described FPGA beam stabilization unit includes an amplitude-phase control code calculation unit, a TR component control unit, a frequency synthesis control unit, and a servo control unit. The input end of the amplitude-phase control code calculation unit is connected to the output end of the DSP beam stabilization unit, and is used to read in the operating frequency and the azimuth angle information in the antenna array coordinate system, and calculate and generate the amplitude-phase control code information of each channel of the TR component. The input end of the TR component control unit is connected to the output end of the amplitude-phase control code calculation unit, and the output end of the TR component control unit is connected to the external TR component, and is used to implement the control of the TR component and the beam stabilization function in the azimuth direction. The input end of the frequency synthesis control unit is connected to the output end of the DSP beam stabilization unit, and is used to implement the frequency scanning control function in the elevation direction. The input end of the servo control unit is simultaneously connected to the output end of the DSP beam stabilization unit and the servo AD unit, and is used to read in the current servo angle information and transmit it to the DSP pitch closed-loop control unit through the EMIF, and read the servo control parameters from the DSP pitch closed-loop control unit. The output end of the servo control unit is connected to the external servo, and is used to implement the servo control function in the elevation direction. The frequency synthesis control and the servo control together implement the electronic stabilization function of the elevation beam.

[0023] The described FPGA signal processing unit includes a digital down-conversion unit, a pulse compression unit, and a clutter suppression unit. The input end of the digital down-conversion unit is connected to the sum-difference two-channel echo AD unit, and is used to read in the digitized echo data. The output end of the digital down-conversion unit is sequentially connected to the pulse compression unit and the clutter suppression unit, and is used to implement the digital down-conversion, pulse compression, and clutter suppression functions of the sum-difference two-channel echo data. The output end of the clutter suppression unit is connected to the input end of the DSP signal processing unit through the SRIO bus, and is used to transmit the echo pulse compression and clutter suppression results to the DSP for further processing.

[0024] It also includes a clock unit, a storage unit, and a power supply unit;

[0025] The output of the described clock unit is connected to the clock input ends of the AD unit and the FPGA unit, and is used to provide clock input for the AD unit and the FPGA unit. The clock inputs of the DSP unit and the RS422 serial port unit use separate crystal oscillator inputs;

[0026] The described storage unit includes a DSP program memory unit and an FPGA program memory unit, which are respectively connected to the DSP unit and the FPGA unit, and are used to provide storage for the application programs of the DSP unit and the FPGA unit respectively. The described DSP storage unit includes a DSP data memory and a DSP program memory, which are connected to the DSP, and are used to provide data storage and program storage for the DSP respectively. The described FPGA storage unit includes an FPGA data memory and an FPGA program memory, which are connected to the FPGA unit, and are used to provide data storage and program storage for the FPGA.

[0027] The power supply unit includes a DSP power supply unit, an FPGA power supply unit, an echo AD unit power supply, a servo AD unit power supply, an RS422 serial port unit power supply, and a memory unit power supply, which are used to provide various power supplies required for the above units to work properly.

[0028] The network interface chip uses 88E1111, and the RS422 serial port chip uses MAX3491DSP.

[0029] The echo AD chip uses AD9268, and the servo AD chip uses AD7980.

[0030] The FPGA chip uses XC7VX690T, and the DSP chip uses TMS320C6678.

[0031] The power supply chips use TPS51200, LTM4644, and LTM4642.

[0032] The utility model replaces the bulky and large - volume three - axis stabilization platform with an electronic beam stabilization device, greatly reducing the volume and weight. At the same time, by integrating the radar signal processing and the beam stabilization device, through hardware reuse, the number of hardware devices is greatly reduced, the wiring between devices is reduced, the R & D cost and design complexity are reduced, and the functions of radar signal processing and beam stabilization are realized. While ensuring to meet the requirements, the overall structure of the invention is simple and the cost is low. Brief Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 It is the principle block diagram of the present utility model;

[0035] Figure 2 It is the principle block diagram of the FPGA unit and the DSP unit of the present utility model. Detailed Embodiments

[0036] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0037] As Figure 1 shown, the present invention is composed of a network port unit, an RS422 serial port unit, an echo AD unit, a servo AD unit, a DSP unit, an FPGA unit, a clock unit, a storage unit, and a power supply unit. Among them: the DSP unit includes a DSP beam stabilization unit and a DSP signal processing unit. The input end of the DSP beam stabilization unit is connected to the output end of the internal network port pair, and is used to receive the control instruction information sent by the display and control computer, implement the transformation from the beam pointing angle in the geographic coordinate system to the beam pointing angle of the antenna array surface, and calculate the pitch closed-loop control parameters; the output end of the DSP beam stabilization unit is connected to the input end of the FPGA beam stabilization unit, and is used to send the operating frequency, the azimuth angle in the array coordinate system, and the servo control parameters to the FPGA beam stabilization unit for further processing;

[0038] The input end of the DSP signal processing unit is connected to the output end of the FPGA signal processing unit through SRIO, and is used to receive the data information of the sum and difference two-way pulse compression and one-way clutter suppression output by the FPGA; the output end of the DSP signal processing unit is connected to the input end of the internal network port through the network, and is used to report the target information processed by the DSP to the display and control computer through the network.

[0039] The FPGA unit includes an FPGA beam stabilization unit and an FPGA signal processing unit. The input end of the FPGA beam stabilization unit is connected to the output end of the DSP beam stabilization unit, and is used to read the azimuth pointing angle in the array coordinate system and the operating frequency and calculate the amplitude-phase control code information of each channel TR component; the output end of the FPGA beam stabilization unit is connected to the TR component, the frequency synthesizer, and the servo, and is used to implement the control of the TR component in the azimuth and the control of the frequency synthesizer and the servo in the pitch, so as to realize the stability of the two-dimensional beam pointing;

[0040] The input end of the FPGA signal processing unit is connected to the sum and difference echo AD unit, and is used to read the digitized sum and difference echo data and perform digital down-conversion, pulse compression, and clutter suppression processing; the output end of the FPGA signal processing unit is connected to the input end of the DSP signal processing unit, and is used to send the data information of the sum and difference two-way pulse compression and one-way clutter suppression to the DSP through the SRIO bus for further processing;

[0041] The external input / output terminal of the network port unit is connected to the display and control computer, which is used to receive the control instructions of the display and control computer and report the target data information; the internal output terminal of the network port unit is connected to the DSP beam stabilization unit, and the internal input terminal of the network unit is connected to the output terminal of the DSP signal processing unit, which is used to output the target information through the network;

[0042] The input terminal of the RS422 serial port unit is connected to the output terminal of the external inertial navigation, which is used to receive the roll angle, heading angle and pitch angle information output by the inertial navigation and participate in realizing the transformation function of the pointing angle information issued by the display and control computer to the radar array surface pointing angle information;

[0043] The input terminal of the echo AD unit is connected to the output terminals of the external combined echo sum and difference channels, which is used for digital acquisition of the sum and difference two-channel echo signals output by the receiver and transmitting the digitized intermediate frequency echo to the FPGA signal processing unit; the input terminal of the servo AD unit is connected to the output terminal of the external servo angle, which is used to transmit the digitized current servo angle to the DSP beam stabilization unit from the FPGA beam stabilization unit through the EMIF bus;

[0044] The DSP beam stabilization unit includes an instruction receiving and parsing unit, a pointing angle transformation unit and a pitch closed-loop calculation unit; the input terminal of the instruction receiving and parsing unit is connected to the internal output terminal of the network port unit, which is used to read the control instruction information through the network; the output terminal of the instruction receiving and parsing unit is sequentially connected to the pointing angle transformation unit and the pitch closed-loop calculation unit, which is used to realize the parsing of the input control instructions, the transformation of the pointing angle information in the geographical coordinate system issued by the display and control unit to the pointing angle information in the array coordinate system, the working frequency calculation and the generation of servo control parameters; the input terminal of the pointing angle transformation unit is also connected to the output terminal of the RS422 serial port unit, which is used to read the heading angle, pitch angle and roll angle information collected by the inertial navigation unit;

[0045] The DSP signal processing unit includes a CFAR processing and detection unit and an angle measurement unit; the input terminal of the CFAR processing and detection unit is connected to the output terminal of the FPGA unit through SRIO, which is used to read the target data after clutter suppression processing; the output of the CFAR processing and detection unit is connected to the input terminal of the angle measurement unit, which is used to output the target information to the display and control computer through the network after angle measurement processing.

[0046] The described FPGA beam stabilization unit includes an amplitude-phase control code calculation unit, a TR component control unit, a frequency synthesizer control unit, and a servo control unit. The input end of the amplitude-phase control code calculation unit is connected to the output end of the DSP beam stabilization unit, and is used to read in the operating frequency and azimuth angle information in the antenna array coordinate system, and calculate and generate the amplitude-phase control code information of each channel's TR component. The input end of the TR component control unit is connected to the output end of the amplitude-phase control code calculation unit, and the output end of the TR component control unit is connected to the external TR component, and is used to implement the TR component control and the beam stabilization function in the azimuth direction. The input end of the frequency synthesizer control unit is connected to the output end of the DSP beam stabilization unit, and is used to implement the frequency scanning control function in the elevation direction. The input end of the servo control unit is simultaneously connected to the output end of the DSP beam stabilization unit and the servo AD unit, and is used to read in the current servo angle information and transmit it to the DSP elevation closed-loop control unit through the EMIF, and read the servo control parameters from the DSP elevation closed-loop control unit. The output end of the servo control unit is connected to the external servo, and is used to implement the servo control function in the elevation direction. The frequency synthesizer control and the servo control together implement the electronic stabilization function of the elevation beam;

[0047] The described FPGA signal processing unit includes a digital down-conversion unit, a pulse compression unit, and a clutter suppression unit. The input end of the digital down-conversion unit is connected to the sum-difference two-channel echo AD unit, and is used to read in the digitized echo data. The output end of the digital down-conversion unit is sequentially connected to the pulse compression unit and the clutter suppression unit, and is used to implement the digital down-conversion, pulse compression, and clutter suppression functions of the sum-difference two-channel echo data. The output end of the clutter suppression unit is connected to the input end of the DSP signal processing unit through the SRIO bus, and is used to transmit the echo pulse compression and clutter suppression results to the DSP for further processing.

[0048] The output of the clock unit is connected to the clock input ends of the AD unit and the FPGA unit, and is used to provide clock input for the AD unit and the FPGA unit. The clock inputs of the DSP unit and the RS422 serial port unit use separate crystal oscillator inputs;

[0049] The described storage unit includes a DSP program memory unit and an FPGA program memory unit, which are respectively connected to the DSP unit and the FPGA unit, and are used to respectively provide storage for the application programs of the DSP unit and the FPGA unit. The DSP storage unit includes a DSP data memory and a DSP program memory, which are connected to the DSP, and are used to respectively provide data storage and program storage for the DSP. The FPGA storage unit includes an FPGA data memory and an FPGA program memory, which are connected to the FPGA unit, and are used to provide data storage and program storage for the FPGA;

[0050] The power supply unit includes a DSP power supply unit, an FPGA power supply unit, an echo AD unit power supply, a servo AD unit power supply, an RS422 serial port unit power supply, and a memory unit power supply, which are used to provide various power supplies required for the normal operation of the above units.

[0051] For the airborne radar signal processing and beam stabilization device described above, in order to achieve the function of radar signal processing, after the radar antenna receives the target reflected echo in the set airspace, sum and difference two-way echo information is formed and written into the FPGA signal processing unit through the echo AD unit. The FPGA signal processing unit sequentially performs digital down-conversion, pulse compression, and clutter suppression processing and then sends it to the DSP signal processing unit, and successively undergoes CFAR processing, target detection, and angle measurement processing, and outputs the distance, amplitude, speed, and angle information of the target through the network port to the display and control computer for further processing and display.

[0052] For the airborne radar signal processing and beam stabilization device described above, in order to achieve the function of beam electronic stabilization, the master computer sends the azimuth angle and pitch angle information of the geographical coordinate system to the DSP beam stabilization unit through the Ethernet. The DSP beam stabilization unit also receives the heading angle, pitch angle, and roll angle information measured in real time by the inertial navigation unit through the RS422 unit. Through coordinate transformation, the transformation from the pointing angle of the geographical coordinate system to the pointing angle of the radar array coordinate system is realized, and then the pitch angle and azimuth angle information of the antenna array coordinate system are obtained. The DSP beam stabilization unit reads the current angle information of the servo from the FPGA beam stabilization unit through the EMIF bus. By comparing the pitch angle of the array coordinate system, the current angle information of the servo, and the relationship table between the antenna operating frequency and the pitch beam pointing, using the closed-loop control algorithm, the parameter information such as the antenna operating frequency, direction control, speed control, and start / stop setting of the servo is calculated and sent to the FPGA beam control unit through the EMIF bus; after the FPGA beam control unit reads the azimuth angle of the array coordinate system, it calculates the amplitude-phase control code of each channel TR component, and combines the TR component timing signal to realize the control of the TR component and the beam stabilization function in the azimuth direction; the FPGA beam control unit reads the operating frequency and servo control parameters to control the frequency synthesizer and servo to realize the beam stabilization function in the pitch direction.

[0053] The described clock unit provides synchronous clock information for the FPGA unit, echo AD unit, and servo AD unit; the storage unit provides program storage functions for the DSP unit and FPGA unit, ensuring that the DSP application program and FPGA application program can be automatically loaded and run after power-on; the storage unit also provides data storage functions for the DSP unit and FPGA unit, providing data caching space for the operation of the DSP unit and FPGA unit application programs; the power supply unit provides various power supplies required for the normal operation of the network interface unit, RS422 serial port unit, echo AD unit, servo AD unit, DSP unit, and FPGA unit.

[0054] As Figure 2 As shown, the FPGA signal processing unit includes a digital down-conversion unit, a pulse compression unit, and a clutter suppression unit. The output of the FPGA clutter suppression unit is connected to the input of the DSP signal processing unit through the SRIO bus; the DSP signal processing unit includes a CFAR processing and detection unit and an angle measurement unit. The output of the DSP angle measurement unit is connected to the display control computer through the network interface. The signal processing units of the DSP unit and FPGA unit, together with the echo AD unit, collect dual-channel echo data to implement the radar signal processing function.

[0055] The working process of the radar signal processing implemented by the present utility model is as follows: After the two-channel echo AD unit digitizes the radar target echo, the FPGA unit sequentially performs tasks with fixed algorithms such as digital down-conversion, pulse compression, and clutter suppression on the sum and difference of the two-channel echoes, and tasks with high real-time requirements for processing. The data after clutter suppression is transmitted to the DSP unit through the EMIF bus. The DSP unit sequentially completes tasks such as constant false alarm rate processing, target detection, and angle measurement, and transmits information such as the distance, speed, azimuth angle, and elevation angle of the target detection to the display control computer through the network interface for further processing and display.

[0056] As Figure 2 As shown, the DSP unit beam stabilization unit includes an instruction receiving and parsing unit, a pointing angle transformation unit, and a servo closed-loop control unit. The DSP servo closed-loop control unit is connected to the FPGA beam stabilization unit through the EMIF bus; the FPGA beam stabilization unit includes a beam control code calculation unit, a TR component control unit, a frequency synthesizer control unit, and a servo control unit. The FPGA TR component control unit is connected to the TR component, the FPGA frequency synthesizer unit is connected to the frequency synthesizer, and the FPGA servo control unit is connected to the servo. The beam stabilization units of the DSP unit and FPGA unit, together with the servo unit, inertial navigation unit, TR component, and phased array antenna, implement the beam stabilization function of the antenna beam in the elevation direction and azimuth direction.

[0057] The working process of the present utility model to achieve beam electronic stabilization is as follows: The DSP instruction receiving and parsing unit is used to receive and parse the azimuth angle and elevation angle information in the geographical coordinate system sent by the display and control computer through the network. The DSP pointing angle transformation unit is used to combine the received azimuth angle and elevation angle information in the geographical coordinate system with the attitude angle information of the antenna array surface such as the heading angle, elevation angle, and roll angle input by the inertial navigation unit through the RS422 serial port, and through coordinate transformation, obtain the azimuth angle and elevation angle information of the current antenna array surface coordinate system. By looking up the correspondence table between the elevation pointing and working frequency obtained from antenna testing, the DSP elevation closed-loop calculation unit calculates the frequency synthesis working frequency and the servo setting angle in the array surface coordinate system. By comparing the servo setting angle in the array surface coordinate system with the servo current angle read through the AD unit, servo control parameters such as direction control, speed control, and start / stop control required for servo control are generated and written into the FPGA unit through the EMIF bus.

[0058] The FPGA amplitude and phase control code calculation unit calculates the amplitude and phase control code information of each channel TR component according to the working frequency and the azimuth angle information of the array surface coordinate system; the FPGA TR component control unit distributes the amplitude and phase control codes of each TR component channel, and coordinates with the working timing of the TR component to achieve the amplitude and phase control of the TR component and the beam alignment function in the antenna azimuth.

[0059] After the FPGA frequency synthesis control unit reads in the working frequency information, it coordinates with the frequency synthesis working timing to complete the frequency scanning control function in the elevation; after the FPGA servo control unit reads in the servo control parameters such as direction control, speed control, and servo start / stop, it realizes the servo control function; the frequency synthesis and the servo together realize the beam alignment function in the antenna elevation direction.

[0060] The reading and information transfer processes involved in the above working process are all modular and commonly used public technical solutions, and the inventive point of the present invention lies in the functions realized by the device composed of modular combinations, rather than the internal control processes and methods. Therefore, there is no improvement and innovation in the method of the present invention!

[0061] When the utility model is actually used, the network interface chip adopts 88E1111, the RS422 serial port chip adopts MAX3491, the AD chip adopts AD7980, the FPGA chip adopts XC7VX690T, the DSP chip adopts TMS320C6678, the DSP program memory adopts MT25QU128ABA1ESE, the DSP data memory adopts MT41K128M16JT, the FPGA program memory adopts MT25QU256ABA1EW7, the FPGA data memory adopts MT41K256M16TW, and the power supply chips adopt TPS51200, LTM4644 and LTM4642. The above chips are matched with peripheral circuits. This is only an example of a specific instance. Other chip structures that can achieve the same and similar technical effects all belong to the protection scope of the utility model.

[0062] The utility model uses a dual-channel echo AD to realize the acquisition and digital processing of radar echoes; the radar echo signal processing realizes its functions through the collaborative processing of the DSP unit and the FPGA unit. The FPGA signal processing unit realizes tasks with fixed algorithms and high real-time requirements, such as digital down-conversion, pulse compression, and clutter suppression processing of dual-channel digital echoes. The DSP signal processing unit realizes tasks with relatively low real-time requirements, such as constant false alarm rate processing, target detection, and angle measurement. After the target detection is completed, it is transmitted to the display control computer through the network interface for subsequent processing and display.

[0063] The beam electronic stabilization function realizes the electronic stabilization function of the antenna beam in the pitch and azimuth directions by sharing the DSP and FPGA resources with the signal processing unit and combining the inertial navigation, servo, and TR component units. The DSP beam stabilization unit calculates the pitch and azimuth pointing angle information in the antenna array coordinate system according to the received pitch and azimuth pointing angle information and the attitude angle information provided by the inertial navigation unit; the beam electronic stabilization in the azimuth direction is realized by the FPGA beam stabilization unit controlling the TR component for phase scanning, and the beam electronic stabilization in the pitch direction is achieved through antenna frequency scanning. If the array surface pointing exceeds the antenna frequency scanning range, the servo will automatically adjust the pitch beam pointing to ensure that the pitch beam points to the target.

[0064] In the description of the present utility model, it should be noted that for orientation terms, such as the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., the indicated orientation and positional relationship are based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as limiting the specific protection scope of the present utility model.

[0065] It should be noted that the terms "comprising" and "having" in the description and claims of this application, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0066] Note that the above is only the preferred embodiment of the present utility model and the application of the technical principle. Those skilled in the art will understand that the present utility model is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present utility model. Therefore, although the present utility model has been described in more detail through the above embodiments, the present utility model is not limited to the specific embodiments described herein. Without departing from the concept of the present utility model, it may also include more other effective embodiments, and the scope of the present utility model is determined by the scope of the appended claims.

Claims

1. An airborne radar signal processing and beam electronic stabilization device, characterized in that: It includes an Ethernet port unit and an RS422 serial port unit, an echo AD unit and a servo AD unit, a DSP unit, and an FPGA unit, where: The DSP unit includes a DSP beam stabilization unit and a DSP signal processing unit. The input end of the DSP beam stabilization unit is connected to the output end of the internal Ethernet port pair, and is used to receive the control instruction information sent by the display and control computer, realize the transformation of the beam pointing angle in the geographic coordinate system to the beam pointing angle of the antenna array surface, and calculate the pitch closed-loop control parameters; the output end of the DSP beam stabilization unit is connected to the input end of the FPGA beam stabilization unit, and is used to send the operating frequency, azimuth angle in the array coordinate system, and servo control parameters to the FPGA beam stabilization unit for further processing; The input end of the DSP signal processing unit is connected to the output end of the FPGA signal processing unit through SRIO, and is used to receive the data information of sum and difference two-way pulse compression and one-way clutter suppression output by the FPGA; the output end of the DSP signal processing unit is connected to the input end of the internal Ethernet port through the network, and is used to report the target information processed by the DSP to the display and control computer through the network; The FPGA unit includes an FPGA beam stabilization unit and an FPGA signal processing unit. The input end of the FPGA beam stabilization unit is connected to the output end of the DSP beam stabilization unit, and is used to read in the azimuth pointing angle and operating frequency in the array coordinate system and calculate the amplitude-phase control code information of each channel TR component; the output end of the FPGA beam stabilization unit is connected to the TR component, frequency synthesizer, and servo, and is used to realize the control of the TR component in the azimuth and the control of the frequency synthesizer and servo in the pitch, so as to realize the stabilization of the two-dimensional beam pointing; The input end of the FPGA signal processing unit is connected to the sum and difference echo AD unit, and is used to read in the digitized sum and difference echo data and perform digital down-conversion, pulse compression, and clutter suppression processing; the output end of the FPGA signal processing unit is connected to the input end of the DSP signal processing unit, and is used to send the data information of sum and difference two-way pulse compression and one-way clutter suppression to the DSP through the SRIO bus for further processing; The external input / output end of the Ethernet port unit is connected to the display and control computer, and is used to receive the control instructions of the display and control computer and report the target data information; the internal output end of the Ethernet port unit is connected to the DSP beam stabilization unit, and the internal input end of the network unit is connected to the output end of the DSP signal processing unit, and is used to output the target information through the network; The input end of the RS422 serial port unit is connected to the output end of the external inertial navigation, and is used to receive the roll angle, heading angle, and pitch angle information output by the inertial navigation, and participate in realizing the transformation function of the pointing angle information sent by the display and control computer to the radar array pointing angle information; The input end of the echo AD unit is connected to the output ends of the external sum-difference path echo and the sum-difference path echo, and is used for digitally collecting the sum-difference two-path echo signals output by the receiver, and transmitting the digitized intermediate-frequency echo to the FPGA signal processing unit; the input end of the servo AD unit is connected to the output end of the external servo angle, and is used for transmitting the digitized current servo angle to the DSP beam stabilization unit from the FPGA beam stabilization unit through the EMIF bus.

2. The airborne radar signal processing and beam electronic stabilization device according to claim 1, wherein: The DSP beam stabilization unit includes an instruction receiving and parsing unit, a pointing angle transformation unit, and a pitch closed-loop calculation unit; the input end of the instruction receiving and parsing unit is connected to the internal output end of the network port unit, and is used for reading in control instruction information through the network; the output end of the instruction receiving and parsing unit is sequentially connected to the pointing angle transformation unit and the pitch closed-loop calculation unit, and is used for realizing the parsing of the input control instruction, the transformation of the geographic coordinate system pointing angle information issued by the display control unit to the array coordinate system pointing angle information, the working frequency calculation, and the generation of servo control parameters; The input end of the pointing angle transformation unit is further connected to the output end of the RS422 serial port unit, and is used for reading in the heading angle, pitch angle, and roll angle information collected by the inertial navigation unit; The DSP signal processing unit includes a CFAR processing and detection unit and an angle measurement unit; the input end of the CFAR processing and detection unit is connected to the output end of the FPGA unit through SRIO, and is used for reading the target data after clutter suppression processing; the output of the CFAR processing and detection unit is connected to the input end of the angle measurement unit, and is used for outputting the target information to the display control computer through the network after angle measurement processing.

3. The airborne radar signal processing and beam electronic stabilization device according to claim 1, characterized in that: The FPGA beam stabilization unit includes an amplitude-phase control code calculation unit, a TR component control unit, a frequency synthesis control unit, and a servo control unit. The input end of the amplitude-phase control code calculation unit is connected to the output end of the DSP beam stabilization unit, and is used for reading in the working frequency and the azimuth angle information in the antenna array coordinate system, and calculating and generating the amplitude-phase control code information of each channel TR component; The input end of the TR component control unit is connected to the output end of the amplitude-phase control code calculation unit, and the output end of the TR component control unit is connected to the external TR component, and is used for realizing the TR component control and the azimuth beam stabilization function; the input end of the frequency synthesis control unit is connected to the output end of the DSP beam stabilization unit, and is used for realizing the pitch frequency scanning control function; the input end of the servo control unit is simultaneously connected to the output end of the DSP beam stabilization unit and the servo AD unit, and is used for reading in the current servo angle information and transmitting it to the DSP pitch closed-loop control unit through the EMIF, and reading the servo control parameters from the DSP pitch closed-loop control unit; the output end of the servo control unit is connected to the external servo, and is used for realizing the pitch servo control function. The frequency synthesis control and the servo control together realize the electronic stabilization function of the pitch beam. The described FPGA signal processing unit includes a digital down-conversion unit, a pulse compression unit, and a clutter suppression unit; the input end of the digital down-conversion unit is connected to the sum-difference two-channel echo AD unit for reading in digitized echo data; the output end of the digital down-conversion unit is sequentially connected to the pulse compression unit and the clutter suppression unit, which are used to implement the digital down-conversion, pulse compression, and clutter suppression functions of the sum-difference two-channel echo data; the output end of the clutter suppression unit is connected to the input end of the DSP signal processing unit through the SRIO bus, which is used to transmit the echo pulse compression and clutter suppression results to the DSP for further processing.

4. The airborne radar signal processing and beam electronic stabilization device according to claim 1, characterized in that: It also includes a clock unit, a storage unit, and a power supply unit; The output of the clock unit is connected to the clock input ends of the AD unit and the FPGA unit, which is used to provide clock input for the AD unit and the FPGA unit; the clock inputs of the DSP unit and the RS422 serial port unit use separate crystal oscillator inputs; The storage unit includes a DSP program memory unit and an FPGA program memory unit, which are respectively connected to the DSP unit and the FPGA unit and are used to provide storage for the application programs of the DSP unit and the FPGA unit respectively; the DSP program memory unit includes a DSP data memory and a DSP program memory, which are connected to the DSP and are used to provide data storage and program storage for the DSP respectively; the FPGA program memory unit includes an FPGA data memory and an FPGA program memory, which are connected to the FPGA unit and are used to provide data storage and program storage for the FPGA; The power supply unit includes a DSP power supply unit, an FPGA power supply unit, an echo AD unit power supply, a servo AD unit power supply, an RS422 serial port unit power supply, and a memory unit power supply, which are used to provide the power required for the normal operation of the above units.

5. The airborne radar signal processing and beam electronic stabilization device according to any one of claims 1-4, characterized in that: The network port unit uses 88E1111, and the RS422 serial port chip uses MAX3491DSP.

6. The airborne radar signal processing and beam electronic stabilization device according to claim 5, characterized in that: The described echo AD unit uses AD9268, and the servo AD unit uses AD7980.

7. The airborne radar signal processing and beam electronic stabilization device according to claim 6, characterized in that: The described FPGA unit uses XC7VX690T, and the DSP chip uses TMS320C6678.

8. The airborne radar signal processing and beam electronic stabilization device according to claim 4, characterized in that: The power supply unit uses TPS51200, LTM4644, and LTM4642.

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