Multi-ARM and FPGA control system for mass spectrometer

Abstract

A multi-ARM (Advanced RISC Machines) and FPGA (Field Programmable Gate Array) system belongs to a distributed control system, and is commonly used in the fields of industrial production, manufacturing, processing and the like, including the industries of chemical industry, pharmacy, food, paper pulp, papermaking and the like. The system has the characteristics of high universality, flexible system configuration, complete control function, convenience in data processing, simplicity and standardization in installation, convenience in debugging, safety and reliability in operation and the like. According to the multi-ARM and FPGA control system for the mass spectrometer provided by the utility model, a distributed control system is realized for the mass spectrometer through a plurality of ARM and FPGAs, and the multi-ARM and FPGA control system has the advantages of high performance, strong fault detection capability and high system reliability. Through excellent power-on, power-off and reset circuits, the mass spectrometer has high robustness, and provides safety guarantee for a mass spectrometer system.

Description

Technical Field

[0001] The utility model belongs to the technical field of distributed control systems, and particularly relates to a control system of multiple ARMs and FPGAs for a mass spectrometer. Background Art

[0002] As an analytical instrument, the digital system of a mass spectrometer is characterized by high-speed real-time output, high-speed data acquisition, high-speed signal processing, and complex control systems and logics. These characteristics require its control system to have high processing capabilities, that is, high-performance processors. The combination of ARM and FPGA is a good choice, with characteristics such as easy-to-use, practical, and high-speed interfaces.

[0003] In the existing mass spectrometry field, most adopt a single-ARM and single-FPGA solution or an integrated chip with the functions of ARM and FPGA. Its characteristic is simplified design, and the disadvantages are high proportion of control system component failures and low self-fault detection ability.

[0004] The multi-ARM and FPGA system involves multi-core startup, multi-core synchronization, multi-core reset, and multi-core communication. Multi-core communication can improve the detection rate and reliability of faulty components. Multi-core startup, multi-core reset, and multi-core reset are design difficulties in distributed control systems. In current applications, most systems do not achieve orderly startup, orderly shutdown, and orderly reset, and unpredictable risks will occur during the disorderly period. When the power-on timing is not controlled, the program startup times of each control chip are inconsistent. During the disorderly period, unpredictable states will occur on the peripheral control pins and interconnection pins of the control chip, and in severe cases, peripheral devices will be burned out. Summary of the Invention

[0005] In view of this, the utility model aims to overcome the above deficiencies in the prior art and proposes a control system of multiple ARMs and FPGAs for a mass spectrometer. Both ARM and FPGA are split into a distributed control system, that is, multiple ARM chips and multiple FPGA chips are used, which can reduce the proportion of component damage, improve system reliability, improve the detection rate of component failures, and is suitable for collaborative development by multiple people, reducing the development difficulty and risk.

[0006] To achieve the above object, the technical solution of the utility model is realized as follows:

[0007] A control system for a mass spectrometer with multiple ARMs and FPGAs, including a main ARM chip 1, a slave ARM chip 2, a main FPGA chip 1, and slave FPGA chips. The slave FPGA chips include a slave FPGA chip 2, a slave FPGA chip 3, a slave FPGA chip 4, and a slave FPGA chip 5. The main ARM chip 1 is connected to the slave ARM chip 2 and the main FPGA chip 1. The slave ARM chip 2 is connected to the slave FPGA chip 5. The main FPGA chip 1 is connected to the slave FPGA chip 2, the slave FPGA chip 3, and the slave FPGA chip 4. The main ARM chip 1 is connected to an external reset switch. The main ARM chip 1 is also connected to a power supply circuit 0. The power supply circuit 0 is connected to a power-off release circuit of the power supply circuit 0. The main ARM chip 1 is also connected to a power supply circuit 1. The power supply circuit 1 is connected to a power-off release circuit of the power supply circuit 1 and the main FPGA chip 1. The slave ARM chip 2 is connected to a power supply circuit 5 and a power supply circuit 6. The power supply circuit 5 is connected to a power-off release circuit of the power supply circuit 5. The main ARM chip 1 is also connected to the power supply circuit 5. The slave FPGA chip 5 is connected to the power supply circuit 6. The power supply circuit 6 is connected to a power-off release circuit of the power supply circuit 6. The main FPGA chip 1 is also connected to a power supply circuit 2. The power supply circuit 2 is connected to a power-off release circuit of the power supply circuit 2 and the slave FPGA chip 2. The main FPGA chip 1 is also connected to a power supply circuit 3. The power supply circuit 3 is connected to a power-off release circuit of the power supply circuit 3 and the slave FPGA chip 3. The main FPGA chip 1 is also connected to a power supply circuit 4. The power supply circuit 4 is connected to a power-off release circuit of the power supply circuit 4 and the slave FPGA chip 4.

[0008] Further, the power-off release circuits of the power supply circuit 0, the power supply circuit 1, the power supply circuit 2, the power supply circuit 3, the power supply circuit 4, the power supply circuit 5, and the power supply circuit 6 all include a power-consuming resistor and a storage capacitor connected in parallel with the power-consuming resistor.

[0009] Further, the main ARM chip and the slave ARM chip are both high-performance ARMs with cache operations.

[0010] Further, the main FPGA chip 1 and the slave FPGA chips are all high-performance FPGAs.

[0011] Compared with the prior art, the control system for a mass spectrometer with multiple ARMs and FPGAs of the present utility model has the following advantages:

[0012] The utility model realizes a distributed control system for a mass spectrometer through multiple ARM and FPGA chips, which has the advantages of high performance, strong fault detection ability and high system reliability. With excellent power-on, power-off and reset circuits, it has high robustness and provides safety guarantee for the mass spectrometer system. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings constituting a part of the present utility model are used to provide a further understanding of the present utility model. The schematic embodiments of the present utility model and their descriptions are used to explain the present utility model and do not constitute an improper limitation of the present utility model. In the drawings:

[0014] Figure 1 is a schematic diagram of the principle of a control system for a mass spectrometer with multiple ARM and FPGA chips according to the present utility model;

[0015] Figure 2 is a schematic diagram of the connection between the power supply loop release circuit and the power supply loop in the embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] It should be noted that, without conflict, the embodiments in the present utility model and the features in the embodiments may be combined with each other.

[0017] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present utility model. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise stated, the meaning of "a plurality" is two or more.

[0018] In the description of the present utility model, it should be noted that, unless otherwise clearly defined and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood through specific situations.

[0019] The present utility model will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0020] As Figure 1 shown, the present utility model provides a control system for a mass spectrometer with multiple ARMs and FPGAs, including a main ARM chip 1, a slave ARM chip 2, a main FPGA chip 1, and slave FPGA chips. The slave FPGA chips include a slave FPGA chip 2, a slave FPGA chip 3, a slave FPGA chip 4, and a slave FPGA chip 5. The main ARM chip 1 is connected to the slave ARM chip 2 and the main FPGA chip 1. The slave ARM chip 1 is connected to the slave FPGA chip 5. The main FPGA chip 1 is connected to the slave FPGA chip 2, the slave FPGA chip 3, and the slave FPGA chip 4. The main ARM chip 1 is connected to an external reset switch. The main ARM chip 1 is also connected to a power supply circuit 0. The power supply circuit 0 is connected to a power-off release circuit for the power supply circuit 0. The main ARM chip 1 is also connected to a power supply circuit 1. The power supply circuit 1 is connected to a power-off release circuit for the power supply circuit 1 and the main FPGA chip 1. The slave ARM chip 2 is connected to a power supply circuit 5. The power supply circuit 5 is connected to a power-off release circuit for the power supply circuit 5. The main ARM chip 1 is also connected to the power supply circuit 5 and the power supply circuit 6. The power supply circuit 6 is connected to a power-off release circuit for the power supply circuit 6. The main FPGA chip 1 is also connected to a power supply circuit 2. The power supply circuit 2 is connected to a power-off release circuit for the power supply circuit 2 and the slave FPGA chip 2. The main FPGA chip 1 is also connected to a power supply circuit 3. The power supply circuit 3 is connected to a power-off release circuit for the power supply circuit 3 and the slave FPGA chip 3. The main FPGA chip 1 is also connected to a power supply circuit 4. The power supply circuit 4 is connected to a power-off release circuit for the power supply circuit 4 and the slave FPGA chip 4.

[0021] Figure 1Both ARM1 and ARM2 are high-performance ARMs with cache operations and strong data processing and communication capabilities; FPGA1 to FPGA5 are all high-performance FPGAs. Region A, Region B, Region C, Region D, Region E, and Region F are the block diagrams of respective control devices and peripheral circuits. Region A is responsible for overall control and communication. It is connected to the PC via Ethernet and to each ARM or FPGA in Regions B, C, D, E, and F via a parallel port. Region B controls the excitation of the mass spectrometer quadrupole. The higher the ion mass number passing through the quadrupole, the higher the excitation voltage output to the quadrupole mass filter. Region C controls the ion optical voltage. The higher the ion mass number passing through the transmission path, the higher the guiding voltage of the required electric field. Region D controls the high voltage for substance ionization, outputting thousands of volts of positive high voltage when positive ions need to be generated and negative high voltage when negative ions need to be generated. Regions E and F jointly complete the construction of the mass spectrometer test environment, which includes ion spray gas, heating gas, curtain gas, ion heating source, vacuum degree control and measurement, etc. Communication signals 1, 2, 3, 4, 5, and 6 are all two-way communications. Both communication parties regularly send "status" signals to each other, and can know whether the other party is operating normally, improving the component fault detection rate. Each ARM and FPGA is only responsible for part of the functions, and the damage of this part of the functions does not affect other functions, improving the reliability of the control system.

[0022] Multiple ARMs and FPGAs bring power-on, power-off, and reset problems. To solve the power-on problem, this patent follows the principle that the "master" chip is powered on first and the "slave" chip is powered on later. ARM1 first completes power-on, loads the program, and gives "control signal 1" and "control signal 5" to enable the power supply circuits of FPGA1 and ARM2. After FPGA1 completes power-on and program loading, it outputs "loading complete signal 1" and gives "control signal 2", "control signal 3", and "control signal 4" to enable FPGA2 to FPGA4 to complete program loading. At the same time, FPGA2 to FPGA4 output "loading complete signal 2, loading complete signal 3, loading complete signal 4" to FPGA1. After ARM2 loads the program, it gives "control signal 6" to enable the power supply circuit of FPGA5. After FPGA5 completes program loading, it outputs "loading complete signal 6" to ARM2. ARM1, ARM2, and FPGA1 are the "master" chips of the entire control system. After receiving the program loading complete signals from the "slave" chips, ARM1 uniformly issues instructions and completes instruction transmission through their respective communication interfaces, ensuring the safety of the instructions.

[0023] If a program anomaly occurs during the operation of the mass spectrometer, the solution is to reset and power on again. Although powering on again can solve the problem, it will prolong the formation time of the vacuum system, thereby affecting the operation efficiency of the device. Therefore, when an anomaly occurs, the primary method is to reset, and use the "external reset switch" to reset the mass spectrometer system. When ARM1 detects that the "external reset switch" has been pressed for a duration exceeding the set time (such as 5 seconds), it outputs the "reset signal 1" to reset FPGA1 and outputs the "reset signal 5" to the reset circuit of ARM2. FPGA1 that detects the reset signal resets FPGA2 to FPGA4 respectively, and ARM2 after reset outputs the "reset signal 6" to FPGA5. In this progressive manner, orderly reset of multiple ARM and FPGA can be achieved.

[0024] As Figure 2 shown, the power-off release circuits of power supply loop 0, power supply loop 1, power supply loop 2, power supply loop 3, power supply loop 4, power supply loop 5, and power supply loop 6 all include a power-consuming resistor and a storage capacitor connected in parallel with the power-consuming resistor.

[0025] It should be noted that the ARM, FPGA, chips, power supply loops, etc. used in the present invention are all existing products.

[0026] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A control system for a mass spectrometer with multiple ARMs and an FPGA, characterized in that: It includes a main ARM chip 1, a slave ARM chip 2, a main FPGA chip 1, and slave FPGA chips. The slave FPGA chips include a slave FPGA chip 2, a slave FPGA chip 3, a slave FPGA chip 4, and a slave FPGA chip 5. The main ARM chip 1 is connected to the slave ARM chip 2 and the main FPGA chip 1. The slave ARM chip 2 is connected to the slave FPGA chip 5. The main FPGA chip 1 is connected to the slave FPGA chip 2, the slave FPGA chip 3, and the slave FPGA chip 4. The main ARM chip 1 is connected to an external reset switch. The main ARM chip 1 is also connected to a power supply circuit 0. The power supply circuit 0 is connected to a power-off release circuit of the power supply circuit 0. The main ARM chip 1 is also connected to a power supply circuit 1. The power supply circuit 1 is connected to a power-off release circuit of the power supply circuit 1 and the main FPGA chip 1. The slave ARM chip 2 is connected to a power supply circuit 5 and a power supply circuit 6. The power supply circuit 5 is connected to a power-off release circuit of the power supply circuit 5. The main ARM chip 1 is also connected to the power supply circuit 5. The slave FPGA chip 5 is connected to the power supply circuit 6. The power supply circuit 6 is connected to a power-off release circuit of the power supply circuit 6. The main FPGA chip 1 is also connected to a power supply circuit 2. The power supply circuit 2 is connected to a power-off release circuit of the power supply circuit 2 and the slave FPGA chip 2. The main FPGA chip 1 is also connected to a power supply circuit 3. The power supply circuit 3 is connected to a power-off release circuit of the power supply circuit 3 and the slave FPGA chip 3. The main FPGA chip 1 is also connected to a power supply circuit 4. The power supply circuit 4 is connected to a power-off release circuit of the power supply circuit 4 and the slave FPGA chip 4.

2. The control system for a mass spectrometer with multiple ARMs and an FPGA according to claim 1, characterized in that: The power-off release circuits of the power supply circuit 0, the power supply circuit 1, the power supply circuit 2, the power supply circuit 3, the power supply circuit 4, the power supply circuit 5, and the power supply circuit 6 all include a power-consuming resistor and a storage capacitor connected in parallel with the power-consuming resistor.

3. The control system for a mass spectrometer with multiple ARMs and FPGAs according to claim 1, characterized in that: The main ARM chip 1 and the slave ARM chip 2 are both high-performance ARMs with cache operations.

4. The control system of multiple ARMs and FPGAs for a mass spectrometer according to claim 1, wherein: The main FPGA chip 1 and the slave FPGA chips are all high-performance FPGAs.

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