Power failure protection circuit of router
By introducing voltage detection pins and resistor voltage division into the router to detect power loss of the external power input interface, and using electrolytic capacitors to continue power supply, the abnormal power supply problem during power loss of the router is solved and ensures that the router starts normally.
Patent Information
- Application Number
- CN202422453121.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-10-11
AI Technical Summary
Existing routers lack power outage detection protection function, which leads to abnormal power supply between the CPU and the Flash chip when the power is out, resulting in abnormal router startup.
By introducing voltage detection pins and resistor voltage division into the router to detect the power outage of the external power input interface, and using electrolytic capacitors to continue power supply during power outage, combined with the power outage protection of the CPU, ensure the normal operation of the Flash chip.
It realizes fast and accurate detection and power supply when the external power input interface is powered off, avoids Flash chip abnormalities and ensures that the router starts normally.
Smart Images
Figure CN223155451U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of router circuits, in particular to a power-off protection circuit of a router. Background Art
[0002] With the development and progress of computer network and wireless communication technology, the functions and performance of routers have been significantly improved, meeting various needs from simple data transmission to complex network applications, and achieving universal coverage in homes, offices and public scenes. In the process of using the router, it is inevitable to encounter power failures or power interruptions, which may cause abnormal power failure of the device. Abnormal power failure may cause abnormal use of the Flash chip inside the router, resulting in subsequent abnormal startup or operation of the router; the Flash chip stores the files of the operating system and application programs.
[0003] See also Figure 1 The data read and write pins and write protection pins of the Flash chip 20 are connected to the CPU 10, and the external power input interface J1 supplies power to the CPU 10 and the Flash chip 20 through the first buck 30 and the second buck 40. Most of the existing router power-off protection only relies on the WP (Write Protect) pin of the Flash chip to perform soft protection on the Flash chip. When the write protection pin is at a high level, data is prohibited from being written to the Flash chip, but data can be read from the Flash chip; when the write protection pin is at a low level, data can be read and written normally.
[0004] Due to the lack of power-off detection and protection function, the CPU of a traditional router cannot predict in advance the power outage or low power voltage of the external power input interface. When the external power input interface loses power, the power supply of the CPU and the Flash chip is abnormal, the CPU interrupts the read and write operations on the Flash chip, or the CPU has difficulty in setting a high level to the write protection pin to write-protect the Flash chip, which can easily cause subsequent router startup abnormalities.
[0005] Therefore, how to implement power-off detection by the CPU and continue to supply power normally when power is off at the external power input interface is a technical problem that needs to be solved urgently in the current field. Utility Model Content
[0006] The technical problem to be solved by the utility model is to provide a power-off protection circuit of a router, in which a CPU realizes power-off detection and continues to supply power normally when a power-off occurs at an external power input interface.
[0007] The utility model is implemented as follows: a power-off protection circuit of a router, comprising:
[0008] A CPU, an external power input interface, a diode, a first capacitor, a first resistor, a second resistor, and a power output terminal;
[0009] The positive pole of the external power input interface is connected to one end of the first resistor and the anode of the diode. The voltage detection pin of the CPU is connected to the other end of the first resistor and one end of the second resistor. The cathode of the diode is connected to one end of the first capacitor and the power output terminal. The power output terminal is connected to the power pin of the CPU through a first voltage regulator. The negative pole of the external power input interface, the other end of the second resistor, and the other end of the first capacitor are all grounded.
[0010] Further, it further includes a Flash chip. The power output terminal is connected to the power pin of the Flash chip through a second voltage regulator. The data read pin, data write pin, and write protection pin of the Flash chip are all connected to the CPU.
[0011] Further, it further includes a TVS diode. One end of the TVS diode is connected to the positive pole of the external power input interface, and the other end of the TVS diode is connected to the negative pole of the external power input interface.
[0012] Further, the first capacitor is an electrolytic capacitor.
[0013] Further, it further includes a second capacitor, a third capacitor, and a fourth capacitor. The second capacitor, the third capacitor, and the fourth capacitor are all connected in parallel with the first capacitor.
[0014] Further, the first resistor and the second resistor are both adjustable resistors.
[0015] Further, the register inside the CPU stores a power-down protection voltage threshold.
[0016] Further, the power-down protection voltage threshold is first stored in the Flash chip. The CPU reads the power-down protection voltage threshold and then stores it in the register.
[0017] Compared with the background technology, the advantages and beneficial effects of the present utility model are as follows:
[0018] Select a pin of the CPU as the voltage detection pin, and then detect the power failure of the external power input interface through resistor voltage division. When a power failure occurs, the first capacitor supplies power to ensure normal power supply to the CPU. After the CPU detects the power failure, it performs a power failure protection action on the Flash chip, effectively avoiding abnormal use of the Flash chip caused by power failure; in this utility model, the CPU realizes power failure detection. When a power failure occurs at the external power input interface, the power supply continues to be normal. The circuit is simple and ingenious, and the power failure detection is flexible, fast and accurate, which helps to ensure the normal startup of the subsequent router. Description of the Drawings
[0019] The following further describes the present utility model with reference to the drawings in conjunction with embodiments.
[0020] Figure 1 It is a schematic connection diagram of the CPU, Flash chip and external power input interface of the traditional router in the background art.
[0021] Figure 2 It is a schematic structural diagram of the power failure protection circuit of the router of the present utility model.
[0022] Figure 3 It is a schematic connection diagram of the CPU, Flash chip and power output terminal in the embodiment of the present utility model. Detailed Embodiment
[0023] The embodiment of the present utility model provides a power failure protection circuit for a router, which overcomes the shortcoming that the CPU of the traditional router in the background art lacks the power failure detection and protection function, and is likely to cause abnormal startup of the subsequent router after a power failure; it realizes power failure detection by the CPU. When a power failure occurs at the external power input interface, the power supply continues to be normal. After the CPU detects the power failure, it performs a power failure protection action on the Flash chip, which helps to ensure the normal startup of the subsequent router.
[0024] The general idea of the technical solution of the embodiment of the present utility model is as follows:
[0025] The external power input interface is set with a resistor voltage divider, and then the CPU's voltage detection pin is used to detect power failure; when the external power input interface is normally powered, the electrolytic capacitor stores electricity, and when the external power input interface has a power failure, the electrolytic capacitor continues to supply power to the CPU and the Flash chip normally; the diode prevents the electricity of the electrolytic capacitor from flowing back to the CPU's voltage detection pin to avoid interfering with the power failure detection of the CPU. The CPU quickly detects the power failure and responds to execute a protection action. When the Flash chip is performing a set of read and write instruction operations, due to the electrolytic capacitor supplying power, the CPU can continue to work for a period of time. After completing this set of read and write instruction operations, the CPU closes the operation of the Flash chip, or the CPU sets a high level to the write protection pin to perform write protection on the Flash chip; to avoid data chaos or data loss in the Flash chip storage.
[0026] To better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings of the specification and specific embodiments.
[0027] Refer to Figures 1 to 3 , the preferred embodiment of the present invention.
[0028] A power failure protection circuit for a router, comprising:
[0029] CPU 10, external power input interface J1, diode D1, first capacitor C1, first resistor R1, second resistor R2, and power output terminal VinDC;
[0030] The positive pole of the external power input interface J1 is connected to one end of the first resistor R1 and the anode of the diode D1, the voltage detection pin 11 of the CPU is connected to the other end of the first resistor R1 and one end of the second resistor R2, the cathode of the diode D1 is connected to one end of the first capacitor C1 and the power output terminal VinDC, the power output terminal VinDC is connected to the power supply pin VCC1 of the CPU through a first voltage reducer 30, and the negative pole of the external power input interface J1, the other end of the second resistor R2, and the other end of the first capacitor C1 are all grounded.
[0031] The beneficial effects of the above technical solution are as follows: One pin of the CPU 10 is selected as the voltage detection pin 11, and the power-off situation of the external power input interface J1 is detected through resistor voltage division. When a power-off occurs, the first capacitor C1 supplies power to ensure normal power supply to the CPU 10. After detecting the power-off, the CPU 10 performs a power-off protection action on the Flash chip 20, effectively avoiding abnormal use of the Flash chip 20 caused by power-off. In the present utility model, the CPU 10 realizes power-off detection. When the external power input interface J1 has a power-off, normal power supply continues. The circuit is simple and ingenious, and the power-off detection is flexible, fast, and accurate, which helps to ensure the normal startup of the subsequent router.
[0032] It further includes a Flash chip 20. The power output terminal VinDC is connected to the power supply pin VCC2 of the Flash chip through a second voltage regulator 40. The data reading pin, data writing pin, and write protection pin of the Flash chip 20 are all connected to the CPU 10. The beneficial effect of this technical solution is that when the external power input interface J1 has a power-off, the first capacitor C1 continues to supply power to the Flash chip 20. Combining Figure 3 , the GND1 pin of the CPU 10 and the GND2 pin of the Flash chip 20 are both grounded.
[0033] The voltage of the external power supply is relatively large, such as the commonly used 12V; after reducing the voltage of the power output terminal through circuit devices such as DCtoDC or LDO (BUCK) to the voltage required by the chip and then supplying power to the chip; the power supply voltages required by the CPU 10 and the Flash chip 20 are inconsistent, such as 3.3V, 1.8V, etc. Therefore, a first voltage regulator 30 and a second voltage regulator 40 are respectively provided for the power supply pin VCC1 of the CPU 10 and the power supply pin VCC2 of the Flash chip 20.
[0034] It further includes a TVS diode D2. One end of the TVS diode D2 is connected to the positive pole of the external power input interface J1, and the other end of the TVS diode D2 is connected to the negative pole of the external power input interface J1. The beneficial effect of this technical solution is that the TVS diode D2, also known as a transient voltage suppression diode, protects the CPU 10 from being impacted by transient high-voltage spike pulses.
[0035] The first capacitor C1 is an electrolytic capacitor. The electrolytic capacitor has the characteristic of a large rated capacitance.
[0036] It further includes a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are all connected in parallel with the first capacitor C1. Here, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 play a filtering role.
[0037] Both the first resistor R1 and the second resistor R2 are adjustable resistors. The beneficial effect of this technical solution is that it is convenient for the staff to adjust the voltage division value according to the actual situation.
[0038] The register inside the CPU 10 stores the power-down protection voltage threshold. The beneficial effect of this technical solution is that the CPU 10 compares the voltage value of the voltage detection pin 11 with the power-down protection voltage threshold. When it is lower than the power-down protection voltage threshold, after the CPU 10 completes a group of data read and write operations, it preferentially performs the power-down protection action on the Flash chip 20.
[0039] The power-down protection voltage threshold is first stored in the Flash chip 20. The CPU 10 reads the power-down protection voltage threshold and then stores it in the register. The power-down protection voltage threshold is flexibly set by the staff, and the power-down protection voltage threshold is higher than zero and lower than the value after the external power supply is divided by voltage.
[0040] The working mode of the present invention: (1) The external power input interface J1 of the router is normally powered. The external power input interface J1 provides direct current power. The current charges the first capacitor C1 through the diode D1. After the first capacitor C1 is fully charged, the power output terminal VinDC supplies power to electronic components such as the CPU 10 and the Flash chip 20 of the router after voltage reduction. The voltage of the external power input interface J1 is divided by the first resistor R1 and the second resistor R2 and connected to the voltage detection pin 11 of the CPU. After the CPU 10 is started, the CPU 10 compares the voltage value of the voltage detection pin 11 with the power-down protection voltage threshold to implement power-down detection by the CPU 10.
[0041] (2) When a power-down situation such as power failure or low power supply voltage occurs at the external power input interface J1, the first capacitor C1 releases the stored electrical energy, and the router can continue to work for a period of time. Combining with the write protection pin of the Flash chip 20 and through the communication between the CPU 10 and the Flash chip 20, the data read and write operations on the Flash chip 20 are closed, or the CPU 10 waits for the current data read and write operations to be completed before stopping the working state of the Flash chip 20.
[0042] (3) Since the voltage-dividing resistor detection point is located at the front stage of the circuit and the power supply output terminal VinDC is located at the rear stage of the circuit, when the external power input interface J1 loses power, the CPU10 can detect the power loss in the first instance. The diode D1 can ensure that when the external power input interface J1 loses power or is interrupted and the first capacitor C1 supplies power, the electrical energy of the first capacitor C1 will not flow back to the voltage detection pin 11 of the CPU, avoiding affecting the voltage detection state. By detecting the change in the large voltage of the external power input interface J1 with the small voltage after resistor voltage division, the voltage division ratio can be flexibly adjusted to set the detection threshold.
[0043] Although the specific embodiments of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.
Claims
1. A power-off protection circuit for a router, characterized in that, Comprising: CPU, external power input interface, diode, first capacitor, first resistor, second resistor, and power output terminal; The positive electrode of the external power input interface is connected to one end of the first resistor and the anode of the diode. The voltage detection pin of the CPU is connected to the other end of the first resistor and one end of the second resistor. The cathode of the diode is connected to one end of the first capacitor and the power output terminal. The power output terminal is connected to the power pin of the CPU through a first step-down voltage regulator. The negative electrode of the external power input interface, the other end of the second resistor, and the other end of the first capacitor are all grounded.
2. The power-off protection circuit of a router according to claim 1, wherein It further includes a Flash chip. The power output terminal is connected to the power pin of the Flash chip through a second step-down voltage regulator. The data read pin, data write pin, and write protection pin of the Flash chip are all connected to the CPU.
3. The power-off protection circuit of a router according to claim 1, characterized in that It further includes a TVS diode. One end of the TVS diode is connected to the positive electrode of the external power input interface, and the other end of the TVS diode is connected to the negative electrode of the external power input interface.
4. The power-off protection circuit of a router according to claim 1, characterized in that, The first capacitor is an electrolytic capacitor.
5. The power-off protection circuit of a router according to claim 1, characterized in that, It further includes a second capacitor, a third capacitor, and a fourth capacitor. The second capacitor, the third capacitor, and the fourth capacitor are all connected in parallel with the first capacitor.
6. The power-off protection circuit of a router according to claim 1, characterized in that, The first resistor and the second resistor are both adjustable resistors.
7. The power-off protection circuit of a router according to claim 1, characterized in that The register inside the CPU stores a power-down protection voltage threshold.
8. The power-off protection circuit of a router according to claim 7, wherein, The power-down protection voltage threshold is first stored in the Flash chip. The CPU reads the power-down protection voltage threshold and then stores it in the register.