Package of radio frequency device and communication equipment
By optimizing the ground pattern layout on the package substrate of the RF device, the parasitic effects caused by the substrate layout are solved, the passband matching and stability of the RF device are improved, and the return loss performance is ensured.
Patent Information
- Application Number
- CN202422052094.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-08-23
AI Technical Summary
The substrate layout of existing RF devices leads to an increase in parasitic inductance and capacitance, affecting port passband matching, resulting in unnecessary losses and resonance, and reducing return loss performance.
On the package substrate of RF devices, optimize the layout of the ground pattern to ensure that the chip pins are spaced between specific metal layers, avoid overlapping the ground pattern, reduce parasitic effects, and improve passband matching.
By optimizing the ground pattern layout, additional resonance and loss are reduced, and the stability and return loss performance of RF devices are improved.
Smart Images
Figure CN223156035U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a radio frequency device, and more particularly to a package of a radio frequency device and a communication device including the same. Background Art
[0002] Portable communication devices, such as mobile phones, laptops, personal digital assistants
[0003] (personal digital assistant, PDA), Global Positioning System (GPS), and Beidou, etc., need to acquire and transmit signals, and different signals correspond to different frequency ranges. In order to meet the requirements of signal acquisition and transmission of portable communication devices, radio frequency devices such as filters and multiplexers have emerged. With the increase in 5G commercial use, the demand for radio frequency devices such as filters and multiplexers is also increasing.
[0004] Taking the filter in the radio frequency device as an example, there is a close relationship between the substrate layout of the filter in the prior art and the port passband matching. An inappropriate substrate layout will lead to an increase in parasitic inductance and capacitance, which may introduce unnecessary losses or resonances in the port passband, affect the port passband matching, and reduce the return loss performance.
[0005] Taking the multiplexer in the radio frequency device as an example, the multiplexer in the prior art is composed of multiple filters with different frequencies. An inappropriate substrate layout of the multiplexer cannot achieve the equal distribution of power between different ports and cannot ensure the passband matching of each port. Summary of the Utility Model
[0006] In view of the above technical problems, the utility model carefully designs the layout of the ground pattern on the substrate of the radio frequency device, so as to avoid the deterioration of the port passband matching and improve the return loss performance.
[0007] A brief overview of the present utility model will be given below to provide a basic understanding of certain aspects of the present utility model. It should be understood that this overview is not an exhaustive overview of the present utility model. It is not intended to identify the key or important parts of the present utility model, nor is it intended to limit the scope of the present utility model. Its purpose is only to present some concepts in a simplified form as a prelude to the more detailed description to follow.
[0008] According to one aspect of the present utility model, there is provided a packaging structure for a radio frequency device, including: a bare die of the radio frequency device and a packaging substrate, wherein the bare die of the radio frequency device is disposed on the packaging substrate; the packaging substrate includes a plurality of metal layers and insulating layers arranged at intervals, wherein the number of metal layers is N, and N is a natural number greater than or equal to 3; chip pins of the radio frequency device are disposed on the metal layer of the Nth layer in the packaging substrate; no ground pattern is provided at least at a position overlapping the projection area of the chip pins of the radio frequency device on the metal layer of the (N - 1)th layer of the packaging substrate.
[0009] Further, no ground pattern is provided at positions overlapping the projection area of the chip pins of the radio frequency device on metal layers within 3 layers from the metal layer of the Nth layer of the packaging substrate.
[0010] Further, the ground pattern overlapping the projection area of the chip pins of the radio frequency device on the packaging substrate is provided on the metal layer of the first layer of the packaging substrate.
[0011] Further, when N is 7; the ground pattern overlapping the projection area of the chip pins of the radio frequency device on the packaging substrate is provided on the metal layer of the first layer and / or the second layer of the packaging substrate.
[0012] Further, the pads on the bare die of the radio frequency device are connected to the pads on the metal layer of the first layer of the packaging substrate.
[0013] Further, the number of bare dies of the radio frequency device is one or more.
[0014] Further, the chip of the radio frequency device is formed by packaging the bare die of the radio frequency device, and the chip of the radio frequency device is a filter chip, a duplexer chip or a multiplexer chip.
[0015] Further, the multiplexer chip includes at least four filters; the first transmit filter is disposed in the upper left part of the packaging substrate; the first receive filter is disposed in the upper right part of the packaging substrate; the second transmit filter is disposed in the lower left part of the packaging substrate; the second receive filter is disposed in the lower right part of the packaging substrate; the pins of each filter are all disposed on the Nth layer of the packaging substrate.
[0016] Further, a filter network is included between the first end and the second end of the first transmit filter, between the first end and the second end of the first receive filter, between the first end and the second end of the second transmit filter, and between the first end and the second end of the second receive filter; a matching module is further included in the multiplexer chip.
[0017] According to another aspect of the present utility model, there is provided a communication device including the packaging structure described in any one of the foregoing.
[0018] The utility model has the following excellent technical effects: By optimizing the layout of the ground pattern on the substrate of the radio frequency device, parasitic effects can be reduced, additional resonances and losses can be avoided, passband matching can be improved, and stability can be enhanced, thereby ensuring that the filter or multiplexer performs excellently in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The specific content of the utility model will be described below with reference to the drawings, which will help to more easily understand the above and other objects, features, and advantages of the utility model. The drawings are only for showing the principle of the utility model. The dimensions and relative positions of the units do not have to be drawn to scale in the drawings.
[0020] Figure 1 Schematic diagram of the frame of the multiplexer provided by the utility model;
[0021] Figure 2 show Figure 1 Schematic diagram of the filter network of the transmit filter B1Tx in the B1 frequency band in
[0022] Figure 3a Schematic layout diagram of the package structure of the multiplexer in the prior art;
[0023] Figure 3b is Figure 3a Cross-sectional view taken along line A-A' in
[0024] Figure 4 Schematic layout diagram of the package substrate of the multiplexer provided by the utility model;
[0025] Figure 5 Schematic layout diagram of the package substrate of the multiplexer provided by the comparative example;
[0026] Figures 6a - 6b Echo loss curve diagrams of the multiplexer installed on the package substrate provided by the utility model and the multiplexer installed on the package substrate provided by the comparative example. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0027] In the following, the exemplary disclosure of the utility model will be described in conjunction with the drawings. For the sake of clarity and conciseness, not all features for implementing the utility model are described in the specification. However, it should be understood that many specific decisions specific to the utility model can be made during the development of any such implementation of the utility model in order to achieve the specific goals of the developer, and these decisions may vary with different implementations of the utility model.
[0028] Here, it should also be noted that in order to avoid obscuring the present utility model due to unnecessary details, only the device structures closely related to the solution according to the present utility model are shown in the drawings, while other details less related to the present utility model are omitted.
[0029] It should be understood that the present utility model is not limited to the described embodiments only due to the following description with reference to the drawings. In the present utility model, where feasible, the features between different embodiments can be replaced or borrowed, and one or more features can be omitted in one embodiment.
[0030] Hereinafter, a diplexer including B1 + B3 will be taken as an example to detail the present solution. Specifically, the diplexer includes a B1 receive filter, a B1 transmit filter, a B3 receive filter, and a B3 transmit filter. Among them, the passband frequency range of the B1 receive filter is 2110 MHz to 2170 MHz, the passband frequency range of the B1 transmit filter is 1920 MHz to 1980 MHz. The passband frequency range of the B3 receive filter is 1805 MHz to 1880 MHz and the passband frequency range of the B3 transmit filter is 1710 MHz to 1785 MHz, so as to adapt to the wide network coverage of the B1 band and the B3 band, and to adapt to communication devices using the two as a carrier aggregation combination. Those skilled in the art should understand that the multiplexer in the present utility model does not only refer to the B1 + B3 diplexer. The multiplexer in the present utility model specifically refers to a device including two or more filters with different passbands.
[0031] Please refer to Figure 1 , Figure 1 which is a schematic framework diagram of the diplexer provided by the present utility model. As Figure 1 shown, the diplexer includes an antenna port P0, a B1 band transmit filter B1Tx, a B1 band receive filter B1Rx, a B3 band transmit filter B3Tx, and a B3 band receive filter B3Rx.
[0032] The antenna port P0 is an external port for transmitting and receiving radio waves through the antenna element ANT. A matching inductor L can be connected between the antenna port P0 and the ground. The matching inductor L is used to achieve impedance matching with the antenna element ANT and can adjust the passband characteristics of each filter in the diplexer. It can be understood that other types of matching modules can also be provided between the antenna port P0 and the common ports of each filter. The present utility model does not make further limitations in this regard.
[0033] The input end of the transmit filter B1Tx in the B1 frequency band is connected to port P1, the output end of the receive filter B1Rx in the B1 frequency band is connected to port P2, the input end of the transmit filter B3Tx in the B3 frequency band is connected to port P3, and the output end of the receive filter B3Rx in the B3 frequency band is connected to port P4. The output port 11 of the transmit filter B1Tx in the B1 frequency band is connected to the antenna port P0, the input port 12 of the receive filter B1Rx in the B1 frequency band is connected to the antenna port P0, the output port 13 of the transmit filter B3Tx in the B3 frequency band is connected to the antenna port P0, and the input port 14 of the receive filter B3Rx in the B3 frequency band is connected to the antenna port P0.
[0034] Between the input port P1 and the output port 11 of the transmit filter B1Tx in the B1 frequency band, between the input port 12 and the output port P2 of the receive filter B1Rx in the B1 frequency band, between the input port P3 and the output port 13 of the transmit filter B3Tx in the B3 frequency band, and between the input port 14 and the output port P4 of the receive filter B3Rx in the B3 frequency band, there are respectively filter networks composed of resonators and inductors.
[0035] Figure 2 Show Figure 1 The structural schematic diagram of the filter network of the transmit filter B1Tx in the B1 frequency band in. Please refer to Figure 2 As shown, the transmit filter B1Tx in the B1 frequency band includes 4 series resonance branches, and the 4 series resonance branches are sequentially arranged between the output end 11 and the port P1 of the transmit filter B1Tx in the B1 frequency band. There are connection nodes between adjacent series resonance branches of the transmit filter B1Tx in the B1 frequency band, that is, there are a total of 3 connection nodes N1 - N3. There are 3 parallel resonance branches, and one end of the first to third parallel resonance branches is respectively connected to the connection nodes N1, node N2, and node N3. The other ends of the first to third parallel resonance branches are respectively connected to the ground.
[0036] Such as Figure 2 As shown, series resonance units are respectively arranged on the series resonance branches, and parallel resonance units are respectively arranged on the parallel resonance branches.
[0037] Further, the series resonance unit on the first series resonance branch is composed of an inductor 121 and a resonator 101 connected in series; the series resonance unit on the second series resonance branch is composed of a resonator 102; the series resonance unit on the third series resonance branch is composed of a resonator 103; the series resonance unit on the fourth series resonance branch is composed of a resonator 104. The parallel resonance unit on the first parallel resonance branch is composed of a resonator 111 and an inductor 123 connected in series; the parallel resonance unit on the second parallel resonance branch is composed of a resonator 112 and an inductor 124 connected in series; the parallel resonance unit on the third parallel resonance branch is composed of a resonator 113 and an inductor 125 connected in series.
[0038] Further, the inductance values of the inductor elements in the series resonance unit and the parallel resonance unit can be equal or unequal.
[0039] It can be understood that the number of series branches in the transmit filter B1TX of the B1 band is not limited to 4, and the number of parallel branches is not limited to 3. The specific number can be determined according to specific design requirements and should not be used as a specific limitation to the present utility model here.
[0040] For the series resonance unit and the parallel resonance unit, in addition to the Figure 2 composition method shown, each series resonance unit and parallel resonance unit can be selected from a single resonator unit, a form in which the resonator unit and the inductor element are connected in series and / or in parallel, and a form in which the resonator unit and the capacitor element are connected in series and / or in parallel. Specifically, the resonator unit further includes at least one resonator or multiple resonators. When the resonator unit includes multiple resonators, the multiple resonators are connected in series and / or in parallel. The resonator in this embodiment is preferably a thin film bulk acoustic resonator.
[0041] It can be understood that the setting methods of the series resonance branches and parallel resonance branches of the transmit filter B3TX in the B3 band, the receive filter B1RX in the B1 band, and the receive filter B3RX in the B3 band can refer to the setting method of the transmit filter B1TX in the B1 band and will not be elaborated here.
[0042] Figure 3a shows a layout schematic diagram of a duplexer packaging structure in the prior art; Figure 3b is Figure 3a a cross-sectional view taken at A-A' in Figures 3a - 3bAs shown, the receive filter B1TX for the B1 frequency band, the transmit filter B3TX for the B3 frequency band, the receive filter B1RX for the B1 frequency band, and the receive filter B3RX for the B3 frequency band are respectively provided on 4 wafer substrates. It can be understood that the receive filter B1TX for the B1 frequency band, the transmit filter B3TX for the B3 frequency band, the receive filter B1RX for the B1 frequency band, and the receive filter B3RX for the B3 frequency band can also be provided on 2 or 3 wafer substrates. Then, through the cutting process, the receive filter B1TX for the B1 frequency band, the transmit filter B3TX for the B3 frequency band, the receive filter B1RX for the B1 frequency band, and the receive filter B3RX for the B3 frequency band on different wafer substrates are cut and formed into chips and packaged on the same package substrate to cooperate with other components to complete the corresponding circuit functions.
[0043] The package substrate is usually a printed circuit board formed by alternating multiple metal layers and dielectric layers.
[0044] Figure 4 Shows the layout schematic diagram of the diplexer package substrate provided by the present invention. As Figure 4 shown, the diplexer package substrate provided by the present invention is a printed circuit board with seven metal layers, and the first metal layer to the seventh metal layer are respectively represented by L1 - L7. It can be understood that Figure 4 the number of layers of the package substrate in [description] is only an example. In fact, the number of metal layers of the package substrate can be N layers, where N is a natural number greater than 3.
[0045] In the specific embodiment provided by the present invention, when the chip pins of the diplexer chip installed on the package substrate overlap with the projection area of the ground pattern on a metal layer of the package substrate, the overlap claimed in the present invention refers to partial overlap or complete overlap. Then, at least one metal layer of the package substrate is spaced between the metal layer of the package substrate where the chip pins of the diplexer chip are located and the metal layer where the ground pattern on the package substrate is located. The chip of the diplexer mentioned in the present invention refers to the structure after packaging the bare die of the unencapsulated diplexer or the bare die of the diplexer only packaged at the wafer level.
[0046] Exemplarily, as Figure 4As shown, the quadruplexer packaging substrate provided by the present utility model is a printed circuit board with seven metal layers, and the first metal layer to the seventh metal layer are respectively represented by L1-L7. The metal layer where the chip pins of the quadruplexer chip are located is the seventh metal layer L7 of the packaging substrate, where the pin B1Rx1 is the pin of the receive filter B1RX for the B1 frequency band, and the pin B3Tx1 is the pin of the transmit filter B3TX for the B3 frequency band. The first metal layer L1 of the packaging substrate has a ground pattern G1, and the second metal layer L2 has a ground pattern G2, and the projection areas of the pin B1Rx1 and the pin B3Tx1 overlap with the ground pattern G1 on the first metal layer L1 and the ground pattern G2 on the second metal layer L2 of the packaging substrate. At this time, at the positions on the third metal layer to the sixth metal layer that overlap with the projection area of the chip pins, such as Figure 4 the positions shown in the square boxes are not provided with ground copper foils. Through the above settings, the capacitance of the chip pins of the quadruplexer chip coupled to the ground can be reduced. The pads on the bare die of the quadruplexer provided by the present utility model are connected to the pads on the first metal layer L1 of the packaging substrate. It can be understood that the bare die of the quadruplexer provided by the present utility model can be one or more. Next, the ground pattern layout of the quadruplexer packaging substrate provided by the present utility model will be compared with the ground pattern layout of the quadruplexer packaging substrate provided by the comparative example.
[0047] Figure 5 Fig. shows the layout schematic diagram of the quadruplexer packaging substrate provided by the comparative example. Exemplarily, as Figure 5 shown, the quadruplexer packaging substrate provided by the comparative example is a printed circuit board with seven metal layers, and the first metal layer to the seventh metal layer are respectively represented by L1'-L7'.
[0048] As Figure 5 shown, there are ground patterns between the first metal layer L1 and the sixth metal layer L6 of the packaging substrate, and ground patterns are provided at the positions on the first to sixth metal layers that overlap with the projection area of the chip pins of the quadruplexer chip. The metal layer where the chip pins are located is the seventh metal layer L7 of the packaging substrate, where the pin B1Rx1 is the pin of the receive filter B1RX for the B1 frequency band, and the pin B3Tx1 is the pin of the transmit filter B3TX for the B3 frequency band. The first metal layer L1 of the packaging substrate has a ground pattern G1', and the second metal layer L2 has a ground pattern G2', and the projection areas of the pin B1Rx1 and the pin B3Tx1 overlap with the ground pattern G1' on the first metal layer L1 and the ground pattern G2' on the second metal layer L2 of the packaging substrate. At this time, at the positions where the ground patterns G3'-G6' on the third metal layer to the sixth metal layer overlap with the projection areas of the pin B1Rx1 and the pin B3Tx1, such as Figure 5 the positions shown in the square boxes are all provided with ground copper foils.
[0049] Please refer toFigures 6a - 6b , Figures 6a - 6b is the echo loss curve graph of the duplexer installed on the packaging substrate provided by the present utility model and the duplexer installed on the packaging substrate provided by the comparative example. The echo losses of the duplexer installed on the packaging substrate provided by the present utility model and the duplexer installed on the packaging substrate provided by the comparative example are tested to obtain the echo loss comparison graph of the receive filter B1RX in the B1 frequency band and the transmit filter B3TX in the B3 frequency band. Among them Figure 6a is the echo loss comparison graph of the receive filter B1RX in the B1 frequency band of the two, where the thin line represents the echo loss graph of the receive filter B1RX in the B1 frequency band on the packaging substrate provided by the comparative example, and the thick line represents the echo loss graph of the receive filter B1RX in the B1 frequency band on the packaging substrate provided by the present utility model. Figure 6b is the echo loss comparison graph of the transmit filter B3TX in the B3 frequency band of the two, where the thin line represents the echo loss graph of the transmit filter B3TX in the B3 frequency band on the packaging substrate provided by the comparative example, and the thick line represents the echo loss graph of the transmit filter B3TX in the B3 frequency band on the packaging substrate provided by the present utility model. It can be seen from Figures 6a - 6b that due to the relatively large capacitance of the chip pins of the duplexer on the packaging substrate provided by the comparative example coupled to the ground, the deviation of the echo loss RL value in the corresponding passband from the echo loss RL value of the duplexer on the packaging substrate provided by the present utility model is about 1 - 2 dB. It can be seen that the duplexer installed on the packaging substrate provided by the present utility model can avoid the deterioration of the port passband matching, thereby improving the echo loss performance.
[0050] It should be understood that although the present utility model is described by taking the duplexer as an example, the layout of the ground pattern on the corresponding packaging substrate can also be carried out for single filters, diplexers and other radio frequency devices. The present utility model does not limit this.
[0051] Furthermore, the packaging substrate of the radio frequency device of the present utility model can be used in electronic devices, and the electronic devices can be desktop computers, laptops, smart phones, smart watches, wearable devices, Internet server intelligent voice systems, routers, automotive electronic devices, Internet of Things (IoT) devices, medical devices, etc.
[0052] The present utility model has been described above in combination with specific implementation schemes, but those skilled in the art should clearly understand that these descriptions are exemplary and do not limit the protection scope of the present utility model. Those skilled in the art can make various variations and modifications to the present utility model according to the spirit and principle of the present utility model, and these variations and modifications are also within the scope of the present utility model.
Claims
1. A packaging structure of a radio frequency device, characterized in that, Comprising: The bare die of the RF device and the packaging substrate, wherein the bare die of the RF device is disposed on the packaging substrate; The packaging substrate includes a plurality of metal layers and insulating layers arranged at intervals, wherein the number of metal layers is N, and N is a natural number greater than or equal to 3; The chip pins of the RF device are disposed on the metal layer of the Nth layer in the packaging substrate; At least at the position overlapping the projection area of the chip pins of the RF device on the metal layer of the (N - 1)th layer of the packaging substrate, no ground pattern is provided.
2. The encapsulation structure according to claim 1, wherein: No ground pattern is provided at the position overlapping the projection area of the chip pins of the RF device on the metal layer within 3 layers from the Nth metal layer of the packaging substrate.
3. The encapsulation structure according to claim 1 or 2, characterized in that: The ground pattern overlapping the projection area of the chip pins of the RF device on the packaging substrate is disposed on the metal layer of the first layer of the packaging substrate.
4. The encapsulation structure according to claim 3, characterized in that: When N is 7; the ground pattern overlapping the projection area of the chip pins of the RF device on the packaging substrate is disposed on the metal layer of the first layer and / or the second layer of the packaging substrate.
5. The encapsulation structure according to claim 4, wherein: The pads on the bare die of the RF device are connected to the pads on the metal layer of the first layer of the packaging substrate.
6. The encapsulation structure according to claim 5, characterized in that: The number of bare dies of the RF device is one or more.
7. The encapsulation structure according to claim 6, wherein: The chip of the RF device is formed by packaging the bare die of the RF device, and the chip of the RF device is a filter chip, a duplexer chip or a multiplexer chip.
8. The encapsulation structure according to claim 7, wherein: The multiplexer chip includes at least four filters; the first transmit filter is disposed in the upper left part of the packaging substrate; the first receive filter is disposed in the upper right part of the packaging substrate; the second transmit filter is disposed in the lower left part of the packaging substrate; The second receive filter is disposed in the lower right part of the packaging substrate; the pins of each filter are all disposed on the Nth layer of the packaging substrate.
9. The encapsulation structure according to claim 8, characterized in that: Between the first end and the second end of the first transmit filter, between the first end and the second end of the first receive filter, between the first end and the second end of the second transmit filter, and between the first end and the second end of the second receive filter, a filter network is included; a matching module is further included in the multiplexer chip.
10. A communication device, characterized in that: Comprising the packaging structure according to any one of claims 1 - 9.