Packaging structure of power module

Abstract

The utility model relates to the technical field of power semiconductors, in particular to a packaging structure of a power module, which comprises a power substrate and a packaging shell in packaging connection with the power substrate. A three-phase power area is arranged on the front metal layer of the power substrate; each phase power region comprises N power chips, and a phase current power output pin, a first gate pin, a second gate pin, a first source pin and a second source pin which are connected with the N power chips; in each phase power area, the N power chips comprise a first power chip set and a second power chip set, the power chips of the first power chip set are connected with the power chips of the second power chip set in a one-to-one correspondence mode, the phase current power output pin, the first grid electrode pin and the first source electrode pin are connected with the first power chip set, and the first grid electrode pin and the second source electrode pin are connected with the second power chip set. The second grid electrode pin and the second source electrode pin are connected with the second power chip set. The structure has the advantages of small assembly volume, low cost, high power applicability and the like.

Description

Technical Field

[0001] The utility model relates to the technical field of power semiconductors, in particular to a packaging structure of a power module. Background Art

[0002] In existing power modules for motor drives, there are various ways of power inversion (DC - AC - DC). Based on the differences in terminal applications of three - phase motors, different ways of realizing power inversion also exist. Currently, the power modules for driving three - phase motors in terminal applications are as follows: One is based on the TO single - tube packaging process, where multiple power chip single - tube devices are connected in series and parallel according to the corresponding bridge - type power combination, and the switching characteristics of each single - tube device are utilized for terminal three - phase motor drive. The other is plastic - encapsulated integrated 2 - in - 1, 3 - in - 1, 6 - in - 1 modules based on the Quad Flat Package (QFP) process. Referring to the single - tube packaging of epoxy plastic encapsulation, they are all encapsulated with epoxy plastic. However, due to the diversification of power inversion terminals and the requirements of high - voltage platforms, especially in the motor drives of new energy vehicles, high - power modules encapsulated with plastic casings such as HPD and HP1 are used for motor drives, resulting in problems such as relatively large volume and high process requirements for power modules in motor drives. Therefore, the structures of existing power modules for motor drives have problems such as high packaging cost, complex packaging process, and large occupied space. Summary of the Utility Model

[0003] By providing a packaging structure of a power module in an embodiment of the present application, the technical problems in the prior art that the power module for motor drive has high packaging cost, complex packaging process, and large occupied space are solved. The advantages of small assembly volume, low cost, and high power applicability of the packaging structure of the power module are realized, enabling large - scale integration of power devices in the packaging structure of the power module, and avoiding problems such as large occupied space, high cost, and inapplicable power caused by integrated power modules or single - tube combinations for driving motors, etc.

[0004] In a first aspect, an embodiment of the present utility model provides a packaging structure of a power module, including: a power substrate, and a packaging housing encapsulated and connected to the power substrate;

[0005] A three - phase power area is provided on the front - side metal layer of the power substrate; each phase power area includes N power chips, a phase - current power output pin, a first gate pin, a second gate pin, a first source pin, and a second source pin connected to the N power chips, where N is a positive even number greater than 3;

[0006] In each phase power region, the N power chips include a first power chip group and a second power chip group. The number of power chips in both the first power chip group and the second power chip group is N / 2. The power chips in the first power chip group are connected to the power chips in the second power chip group in a one-to-one correspondence. The phase current power output pin, the first gate pin, and the first source pin are all connected to the first power chip group, and the second gate pin and the second source pin are all connected to the second power chip group.

[0007] Preferably, in the first power chip group of each phase power region, the gates of each power chip in the first power chip group are commonly connected to the first gate pin; the sources of each power chip in the first power chip group are commonly connected to the first source pin and the phase current power output pin, and the drains of each power chip in the first power chip group are commonly connected.

[0008] Preferably, in the second power chip group of each phase power region, the gates of each power chip in the second power chip group are commonly connected to the second gate pin, the sources of each power chip in the second power chip group are commonly connected to the second source pin, and the drain of one power chip in the second power chip group is connected to the source of one power chip in the first power chip group of this phase power region.

[0009] Preferably, the first power chip group of each phase power region is located in the first area on the positive metal layer, and the second power chip group of each phase power region is located in the second area on the positive metal layer. The first area and the second area are correspondingly arranged.

[0010] Preferably, it further includes: a negative electrode area and at least one positive electrode area. A positive electrode area pin is provided on the positive electrode area, and a negative electrode area pin is provided on the negative electrode area. The drains of each power chip in the first power chip group of each phase power region are commonly connected to the positive electrode area pin, and the sources of each power chip in the second power chip group of each phase power region are commonly connected to the negative electrode area pin.

[0011] Preferably, it further includes: at least one thermistor and the temperature sampling pin of each thermistor. The thermistor is arranged in the first power chip group of a certain phase power region and / or in the second power chip group of a certain phase power region.

[0012] Preferably, it further includes: a current sensing resistor and the current sampling pin of the current sensing resistor. The current sensing resistor is arranged in the negative electrode area.

[0013] Preferably, it further includes: bubble fixing points, which are arranged on the front metal layer and the back metal layer of the power substrate. The thickness of the bubble fixing points is less than that of the front metal layer and less than that of the back metal layer.

[0014] Preferably, it further includes: stress relief holes, which are arranged between the power chips.

[0015] Preferably, the power chip is a MOSFET chip or a parallel-connected IGBT chip and FRD chip, and the power substrate is any one of DBC ceramic substrate, TFC ceramic substrate, TPC ceramic substrate, aluminum substrate, AMB ceramic substrate, DPC ceramic substrate and LAM ceramic substrate.

[0016] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0017] In the embodiments of the present invention, through the setting of the packaging structure of the power module, multiple power chips are reasonably designed and directly packaged and integrated together, thus realizing the large-scale integration of power devices and improving the reliability and stability of the packaging structure of the power module. In each phase power area, the power chips are embedded in a full-bridge manner, greatly increasing the output power of a single phase area and providing a power module solution for three-phase motor drive above 3kw. And, compared with traditional power devices, the assembly volume of the packaging structure of the power module is greatly reduced, the product process is simplified, and the shell material is saved. In this way, the packaging structure of the power module is highly integrated, the creepage distance is reduced, and it is more conducive to the heat dissipation of the whole device. Compared with the single-tube power chip device arranged on the circuit board, through the packaging structure of the power module in this embodiment, multiple power chips are highly integrated, reducing the internal resistance of the superposition of multiple power chips, reducing the power consumption of the circuit by multiple chips, reducing the creepage distance, avoiding the increase of circuit power consumption caused by too large internal resistance of multiple power chips and the influence on work caused by too large creepage distance, and thus solving to a certain extent the problems such as uneven power consumption and poor heat dissipation caused by individual differences (small electrical performance differences between single-tube power chips) of single power chip devices, resulting in the failure of single devices. Description of the Drawings

[0018] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0019] Figure 1Shows the external structure schematic diagram of the packaging structure of the power module in the embodiment of the present utility model;

[0020] Figure 2 Shows the structure schematic diagram of the power substrate in the embodiment of the present utility model;

[0021] Figure 3 Shows the top view structure schematic diagram of the power substrate in the embodiment of the present utility model;

[0022] Figure 4 Shows the circuit schematic diagram of the packaging structure of the power module in the embodiment of the present utility model;

[0023] Figure 5 Shows the circuit schematic diagram of the packaging structure of the power module with N = 4 in the embodiment of the present utility model.

[0024] In the drawings, 101, power substrate; 200, packaging housing; 102, power chip; 103, phase current power output pin; 104, first gate pin; 105, second gate pin; 106, first source pin; 107, second source pin; 108, positive region pin; 109, negative region pin; 110, thermistor; 111, temperature sampling pin; 112, current detection resistor; 113, current sampling pin; 114, bubble point. Detailed implementation manners

[0025] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0026] Embodiment 1

[0027] The first embodiment of the present utility model provides a packaging structure of a power module, as Figure 1 and Figure 2 shown, including: a power substrate 101, and a packaging housing 200 packaged and connected to the power substrate 101. As Figure 3 shown, a three-phase power region is provided on the front metal layer of the power substrate 101. Among them, the three-phase power regions are respectively a U-phase power region, a V-phase power region, and a W-phase power region. Each phase power region includes N power chips 102, and phase current power output pins 103, a first gate pin 104, a second gate pin 105, a first source pin 106, and a second source pin 107 connected to the N power chips 102, and N is a positive even number greater than 3. N is preferably 4 or 6.

[0028] In each phase power region, N power chips 102 include a first power chip group and a second power chip group. The number of power chips 102 in both the first power chip group and the second power chip group is N / 2. The power chips 102 in the first power chip group are connected to the power chips 102 in the second power chip group in a one-to-one correspondence. The phase current power output pin 103, the first gate pin 104, and the first source pin 106 are all connected to the first power chip group, and the second gate pin 105 and the second source pin 107 are both connected to the second power chip group.

[0029] It should be noted that in this embodiment Figures 1-4 , the structure and connection relationship of each phase power region are described with N = 6 power chips 102. In Figure 3 , the pins represented by the letter G are gate pins, and G1, G2, and G3 respectively represent the first gate pins 104 of each phase power region. G1 is the first gate pin 104 of the U-phase power region, G2 is the first gate pin 104 of the V-phase power region, and G3 is the first gate pin 104 of the W-phase power region. G4, G5, and G6 respectively represent the second gate pins 105 of each phase power region. G6 is the second gate pin 105 of the U-phase power region, G5 is the second gate pin 105 of the V-phase power region, and G4 is the second gate pin 105 of the W-phase power region.

[0030] The pins represented by the letter S are source pins, and S1, S2, and S3 respectively represent the first source pins 106 of each phase power region. S1 is the first source pin 106 of the U-phase power region, S2 is the first source pin 106 of the V-phase power region, and S3 is the first source pin 106 of the W-phase power region. S4, S5, and S6 respectively represent the second source pins 107 of each phase power region. S6 is the second source pin 107 of the U-phase power region, S5 is the second source pin 107 of the V-phase power region, and S4 is the second source pin 107 of the W-phase power region. U, V, and W respectively correspond to the phase current power output pins 103 of the phase power regions. U is the phase current power output pin 103 of the U-phase power region, V is the phase current power output pin 103 of the V-phase power region, and W is the phase current power output pin 103 of the W-phase power region.

[0031] In this embodiment, through the setting of the packaging structure of the power module, multiple power chips 102 are rationally designed and directly packaged and integrated together, thus realizing the large-scale integration of power devices and improving the reliability and stability of the packaging structure of the power module. In each phase power area, the power chips 102 are embedded in a full-bridge manner, greatly increasing the output power of a single phase area and providing a power module solution for three-phase motor drive above 3kw. Moreover, compared with traditional power devices, the assembly volume of the packaging structure of the power module is greatly reduced, the product process is simplified, and the housing material is saved. In this way, the packaging structure of the power module is highly integrated, the creepage distance is reduced, and it is more conducive to the heat dissipation of the whole device. Compared with the single-tube power chip device arranged on the circuit board, through the packaging structure of the power module in this embodiment, multiple power chips 102 are highly integrated, the internal resistance of the superposition of multiple power chips 102 is reduced, the power consumption of the circuit by multiple chips 102 is reduced, the creepage distance is reduced, and the increase in circuit power consumption caused by the too large internal resistance of multiple power chips 102 and the influence on the operation caused by the too large creepage distance are avoided. Furthermore, to a certain extent, the problems such as uneven power consumption and poor heat dissipation caused by individual differences (small electrical performance differences between single-tube power chips) of single power chip devices, resulting in the failure of single devices are solved.

[0032] Next, in combination with Figures 1-3 elaborate in detail the packaging structure of the power module in this embodiment:

[0033] The power substrate 101 of the present utility model includes a front metal layer, a ceramic layer, and a back metal layer that are stacked in sequence. The power substrate 101 is used for soldering the power chip 102 and dissipating heat from the devices on the power substrate 101. The power chip 102 is electrically connected to the power substrate 101. The power substrate 101 can be selected from substrates with electrical transmission, insulation, and heat dissipation functions. For example, thin film ceramic substrate (TFC), thick film printed ceramic substrate (TPC), direct bonded copper ceramic substrate (DBC), active metal brazing ceramic substrate (AMB), direct plated copper ceramic substrate (DPC), laser activated metallization ceramic substrate (LAM), aluminum substrate, etc. The power substrate of the present utility model preferably uses a ceramic substrate with low cost, good performance, and simple manufacturing process, and is further preferably a DBC ceramic substrate.

[0034] As Figure 2 and Figure 3 shown, the first power chip group of each phase power region is located in the first region on the front metal layer, indicating that the first power chip group of each phase power region is located on the same side of the front metal layer. The second power chip group of each phase power region is located in the second region on the front metal layer, indicating that the second power chip group of each phase power region is located on the other side of the front metal layer. The first region and the second region are correspondingly arranged. In this way, the power chips 102 and multiple pins of each phase power region and each phase power region are reasonably and simply distributed, facilitating device wiring, simplifying the packaging structure of the power module, reducing the packaging cost, and reducing the assembly volume of the packaging structure.

[0035] As Figure 4 shown, in the first power chip group of each phase power region, the gates of each power chip 102 in the first power chip group are commonly connected to the first gate pin 104. The sources of each power chip 102 in the first power chip group are commonly connected to the first source pin 106 and the phase current power output pin 103, and the drains of each power chip 102 in the first power chip group are commonly connected. For example, in Figure 4In the first power chip group in the U-phase power region, the gates of each power chip 102 in the first power chip group are commonly connected to the first gate pin 104 (i.e., G1) of the U-phase power region. The sources of each power chip 102 in the first power chip group are commonly connected to the first source pin 106 (i.e., S1) of the U-phase power region and the phase current power output pin 103 (i.e., U) of the U-phase power region. The drains of each power chip 102 in the first power chip group are commonly connected to the positive region pin 108 (i.e., VDD) of the positive region. And so on for the connection relationships of the first power chip groups in the V-phase power region and the W-phase power region.

[0036] As Figure 4 shown, in the second power chip group in each phase power region, the gates of each power chip 102 in the second power chip group are commonly connected to the second gate pin 105. The sources of each power chip 102 in the second power chip group are commonly connected to the second source pin 107. The drain of one power chip 102 in the second power chip group is connected to the source of one power chip 102 in the first power chip group of this phase power region. For example, in Figure 4 the U-phase power region, the gates of each power chip 102 in the second power chip group in the U-phase power region are commonly connected to the second gate pin 105 (i.e., G6) of the U-phase power region. The sources of each power chip 102 in the second power chip group are commonly connected to the second source pin 107 (i.e., S6) of the U-phase power region and are also commonly connected to the negative region pin 109 (i.e., VSS) of the negative region. The drain of one power chip 102 in the second power chip group is connected to the source of one power chip 102 in the first power chip group of the U-phase power region. And so on for the connection relationships of the second power chip groups in the V-phase power region and the W-phase power region.

[0037] Regarding the connection structure settings of the power chips 102 in the first power chip group and the second power chip group in each phase power region, in each phase power region, the power chips 102 are embedded in a full-bridge manner, greatly increasing the output power of a single phase region and providing a power module solution for driving a three-phase motor with a power above 3 kW. In this way, multiple power chips 102 are reasonably designed and directly packaged and integrated together, thus realizing the large-scale integration of power devices and improving the reliability and stability of the packaging structure of the power module. This also enables the power chips 102 and multiple pins in each phase power region and each phase power region to be reasonably and simply distributed, facilitating device wiring, simplifying the packaging structure of the power module, reducing the packaging cost, and reducing the assembly volume of the packaging structure.

[0038] The packaging structure of the power module in this embodiment further includes: a negative electrode region and at least one positive electrode region. A positive electrode region pin 108 is provided on the positive electrode region, and a negative electrode region pin 109 is provided on the negative electrode region. The drains of each power chip 102 in the first power chip group of each phase power region are commonly connected to the positive electrode region pin 108, and the sources of each power chip 102 in the second power chip group of each phase power region are commonly connected to the negative electrode region pin 109. In the drawings of this embodiment, VDD represents the positive electrode region pin 108 of the positive electrode region, and VSS represents the negative electrode region pin 109 of the negative electrode region. In Figure 2 In, on the front metal layer, the positive electrode region is connected to one phase power region, and the negative electrode region can be a separate region to achieve the electrical connection of each electrode region. In this way, the positive electrode region, the positive electrode region pin 108, the negative electrode region, and the negative electrode region pin 109 are reasonably and simply set, which is convenient for device wiring, simplifies the packaging structure of the power module, reduces the packaging cost, and reduces the assembly volume of the packaging structure.

[0039] The packaging structure of the power module in this embodiment further includes: at least one thermistor 110 and a temperature sampling pin 111 of each thermistor 110. The thermistor 110 is provided in the first power chip group of a certain phase power region and / or in the second power chip group of a certain phase power region, and the temperature sampling pin 111 of each thermistor 110 is connected to its own thermistor 110. In the drawings of this embodiment, T1 and T2 represent the two temperature sampling pins 111 of the thermistor 110. As Figures 3-4 shown, the thermistor 110 is provided beside S3, and the thermistor 110 can also be provided between G6 and VDD. The thermistor 110 is used to detect the temperature of the power module and can achieve more efficient control of the power module. As Figure 3 shown by the setting of the thermistor 110, the temperature in the corresponding region of the first power chip group in each phase power region and the temperature in the corresponding region of the second power chip group in each phase power region can be detected more efficiently, quickly, and conveniently.

[0040] The packaging structure of the power module in this embodiment further includes: a current detection resistor 112 and a current sampling pin 113 of the current detection resistor 112. The current detection resistor 112 is provided in the negative electrode region, and the current sampling pin 113 is connected to the current detection resistor 112. In the drawings of this embodiment, as Figures 3-4 shown, R1 and R2 represent the two current sampling pins 113 of the current detection resistor 112. By setting the current detection resistor 112, the magnitude of the current of the power module can be detected in real time, and further, the performance of the packaging structure of the power module can be judged according to the magnitude of the current.

[0041] The packaging structure of the power module in this embodiment further includes: stud bumps 114, which are arranged on the front metal layer and the back metal layer of the power substrate 101. The thickness of the stud bumps 114 is less than that of the front metal layer and less than that of the back metal layer. Specifically, as Figure 3 shown, the stud bumps 114 are arranged in the power areas of the front metal layer, such as the power areas of each phase, the power area of the thermistor 110, or the power area of the current sensing resistor 112. The stud bumps 114 are arranged in the heat dissipation areas of the back metal layer, such as the edge areas of the back metal layer.

[0042] In this embodiment, the stud bumps 114 are used to increase the adhesion and adhesiveness between the metal layer and the ceramic layer, and improve the adhesion. It can solve the problem of ceramic cracking of the power substrate 101 when ultrasonic bonding the power pins and the power chip 102 on the power substrate 101. The stud bumps 114 are in a dot shape, a spherical shape or other shapes, that is, blind holes. The diameter of the stud bumps 114 can be selected from 0.2 to 0.8 mm. It should be noted that the stud bumps 114 in this embodiment are only studded on the metal layer of the power substrate 101 through the studding process and do not completely penetrate the metal layer.

[0043] The packaging structure of the power module in this embodiment further includes: stress relief holes, which are arranged between the power chips 102. The stress relief holes are used to relieve or eliminate the stress generated when the power chips 102 are soldered in the power areas, prevent the power substrate 101 from cracking, further improve the reliability of the device manufacturing process, reduce the process damage rate, and improve the production yield of the packaging structure product of the power module.

[0044] In the packaging structure of the power module in this embodiment, the power chip 102 is a MOSFET chip or IGBT chips and FRD chips connected in parallel. In the drawings of this embodiment, the power chip 102 is shown as a MOSFET chip.

[0045] As Figure 5 shown, Figure 5 it shows the circuit connection relationship of each phase power area with N = 4 power chips 102. In Figure 5Among them, G1 is the first gate pin 104 of the U-phase power region, G2 is the first gate pin 104 of the V-phase power region, and G3 is the first gate pin 104 of the W-phase power region. G6 is the second gate pin 105 of the U-phase power region, G5 is the second gate pin 105 of the V-phase power region, and G4 is the second gate pin 105 of the W-phase power region. S1 is the first source pin 106 of the U-phase power region, S2 is the first source pin 106 of the V-phase power region, and S3 is the first source pin 106 of the W-phase power region. S6 is the second source pin 107 of the U-phase power region, S5 is the second source pin 107 of the V-phase power region, and S4 is the second source pin 107 of the W-phase power region. U is the phase current power output pin 103 of the U-phase power region, V is the phase current power output pin 103 of the V-phase power region, and W is the phase current power output pin 103 of the W-phase power region.

[0046] In Figure 5 Among them, in the first power chip group of the U-phase power region, the gates of each power chip 102 of the first power chip group are commonly connected to the first gate pin 104 (i.e., G1) of the U-phase power region. The sources of each power chip 102 of the first power chip group are commonly connected to the first source pin 106 (i.e., S1) of the U-phase power region and the phase current power output pin 103 (i.e., U) of the U-phase power region, and the drains of each power chip 102 of the first power chip group are commonly connected to the positive region pin 108 (i.e., VDD) of the positive region. And so on for the connection relationships of the first power chip groups in the V-phase power region and the W-phase power region.

[0047] In Figure 5 Among them, in the second power chip group of the U-phase power region, the gates of each power chip 102 of the second power chip group are commonly connected to the second gate pin 105 (i.e., G6) of the U-phase power region. The sources of each power chip 102 of the second power chip group are commonly connected to the second source pin 107 (i.e., S6) of the U-phase power region, and are also commonly connected to the negative region pin 109 (i.e., VSS) of the negative region. The drain of one power chip 102 of the second power chip group is connected to the source of one power chip 102 of the first power chip group in the U-phase power region. And so on for the connection relationships of the second power chip groups in the V-phase power region and the W-phase power region.

[0048] A current sensing resistor 112 and the current sampling pins 113 of the current sensing resistor 112 (i.e., R1, R2) are provided in the negative region. As Figure 5 shown, a thermistor 110 and the temperature sampling pins 111 of each thermistor 110 (i.e., T1, T2) are provided between the second power chip group in the W-phase power region and the second power chip group in the V-phase power region.

[0049] In this embodiment, various power pins (such as phase current power output pin 103, first gate pin 104, second gate pin 105, first source pin 106, second source pin 107, and pole region pin), temperature sampling pin 111, and current sampling pin 113 can all adopt Z-shaped, S-shaped, pin-shaped, etc. The power pins, temperature sampling pin 111, and current sampling pin 113 are all connected to the corresponding regions by ultrasonic bonding or chip / solder welding. The power chip 102 is connected to the power pin or the copper layer where the power pin is located by bonding metal wires (optional aluminum wires, copper wires) or bonding metal sheets (optional copper sheets), and the power regions are connected by bonding metal wires (optional aluminum wires, copper wires) or bonding metal sheets (optional copper sheets).

[0050] As Figure 1 shown, the encapsulation housing 200 adopts electrical insulating materials such as silicone gel and epoxy resin, preferably silicone gel, to directly encapsulate the power substrate 101. In this way, there is no need for an encapsulation frame, which has the advantages of low cost, simplifying the encapsulation structure of the power module, reducing the encapsulation cost, and decreasing the assembly volume of the encapsulation structure. The encapsulation housing 200 can also protect the power chip 102 and isolate the power chip 102 from external moisture and dust.

[0051] Those skilled in the art should understand that although the preferred embodiments of the present invention have been described, once the basic creative concepts are known to those skilled in the art, additional changes and modifications can be made to these embodiments. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0052] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A packaging structure of a power module, characterized in that, Including: A power substrate and a packaging housing packaged and connected to the power substrate; A three-phase power area is provided on the front metal layer of the power substrate; each phase power area includes N power chips, a phase current power output pin, a first gate pin, a second gate pin, a first source pin, and a second source pin connected to the N power chips, and N is a positive even number greater than 3; In each phase power area, the N power chips include a first power chip group and a second power chip group. The number of power chips in the first power chip group and the second power chip group is both N / 2. The power chips in the first power chip group are connected to the power chips in the second power chip group in one-to-one correspondence. The phase current power output pin, the first gate pin, and the first source pin are all connected to the first power chip group, and the second gate pin and the second source pin are all connected to the second power chip group.

2. The packaging structure of the power module according to claim 1, wherein, In the first power chip group of each phase power area, the gates of each power chip in the first power chip group are commonly connected to the first gate pin; the sources of each power chip in the first power chip group are commonly connected to the first source pin and the phase current power output pin, and the drains of each power chip in the first power chip group are commonly connected.

3. The encapsulation structure of the power module according to claim 2, characterized in that In the second power chip group of each phase power area, the gates of each power chip in the second power chip group are commonly connected to the second gate pin, the sources of each power chip in the second power chip group are commonly connected to the second source pin, and the drain of one power chip in the second power chip group is connected to the source of one power chip in the first power chip group of this phase power area.

4. The encapsulation structure of the power module according to claim 1, characterized in that, The first power chip group of each phase power area is located in a first area on the front metal layer, and the second power chip group of each phase power area is located in a second area on the front metal layer. The first area and the second area are correspondingly arranged.

5. The encapsulation structure of the power module according to claim 1, characterized in that, Also including: A negative electrode area and at least one positive electrode area. A positive electrode area pin is provided on the positive electrode area, and a negative electrode area pin is provided on the negative electrode area. The drains of each power chip in the first power chip group of each phase power area are commonly connected to the positive electrode area pin, and the sources of each power chip in the second power chip group of each phase power area are commonly connected to the negative electrode area pin.

6. The encapsulation structure of the power module according to claim 1, characterized in that, Also including: At least one thermistor and a temperature sampling pin for each thermistor. The thermistor is provided in the first power chip group of a certain phase power area and / or the second power chip group of a certain phase power area.

7. The packaging structure of the power module according to claim 5, characterized in that Also including: A current detection resistor and a current sampling pin of the current detection resistor. The current detection resistor is provided in the negative electrode area.

8. The encapsulation structure of the power module according to claim 1, characterized in that, Also including: A calibration bubble point. The calibration bubble point is provided on the front metal layer and the back metal layer of the power substrate. The thickness of the calibration bubble point is less than the thickness of the front metal layer and less than the thickness of the back metal layer.

9. The encapsulation structure of the power module according to claim 1, wherein, Also including: Stress relief holes. The stress relief holes are provided between the power chips.

10. The encapsulation structure of the power module according to any one of claims 1 to 9, characterized in that The power chip is a MOSFET chip or IGBT chips and FRD chips connected in parallel, and the power substrate is any one of a DBC ceramic substrate, a TFC ceramic substrate, a TPC ceramic substrate, an aluminum substrate, an AMB ceramic substrate, a DPC ceramic substrate, and a LAM ceramic substrate.

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