High-efficiency low-ripple two-cascade joint debugging DC regulated power supply system

Abstract

The utility model relates to the technical field of direct-current power supplies, in particular to a high-efficiency low-ripple two-cascade joint debugging direct-current voltage-stabilized power supply system, which comprises a switching power supply, a main controller circuit, a power conversion circuit, an auxiliary power supply module and a serial port communication module, and is characterized in that the main controller circuit is respectively connected with the power conversion circuit, the auxiliary power supply module and the serial port communication module; the main controller circuit is connected with the switching power supply through the gate driver and is used for adjusting the output of the switching power supply, the main controller circuit controls the conversion of the power conversion circuit through an adjusting signal to obtain an actual output voltage, carries out error comparison on the actual output voltage and a set voltage, and dynamically adjusts the output voltage through a PID algorithm; the auxiliary power supply module is used for providing stable power supply voltage for the power conversion circuit and the serial port communication module; the serial port communication module is used for monitoring output voltage and current. According to the utility model, low ripples can be maintained on the premise that high efficiency is maintained.

Description

Technical Field

[0001] The utility model relates to the technical field of DC power supplies, and specifically to a high-efficiency and low-ripple two-stage cascade-regulated DC voltage-stabilized power supply system. Background Art

[0002] At present, as the cornerstone of modern electronic technology, the stability and reliability of DC power supplies are crucial for all fields. According to different working principles, DC power supplies can be mainly divided into two types: linear voltage-stabilized power supplies and switching voltage-stabilized power supplies. Linear voltage-stabilized power supplies have the advantages of stable output voltage, high output accuracy, small output ripple, and low noise. However, at the same time, linear voltage-stabilized power supplies also have the disadvantages of low efficiency, serious heat generation problems, and inability to achieve a wide range of input voltages. Switching voltage-stabilized power supplies have the advantages of high efficiency, less heat generation, and the ability to achieve a wide range of input voltages. However, at the same time, switching voltage-stabilized power supplies also have the disadvantages of larger output ripple, higher noise, more complex circuit structures, and greater design and debugging difficulties.

[0003] Since linear voltage regulators and switching voltage-stabilized power supplies each have their own advantages and disadvantages, they are suitable for different application scenarios. With the progress of society and the development of technology, power supplies are constantly facing new challenges, requiring electronic devices to not only be small in size and low in cost but also have excellent technical indicators. This has promoted the continuous development of power supplies in terms of miniaturization, high efficiency, and low ripple. The two-stage cascade regulation of switching voltage-stabilized power supplies and linear voltage-stabilized power supplies can also maintain low ripple while maintaining high efficiency, and its importance in modern electronic devices is becoming more and more prominent. Summary of the Utility Model

[0004] The purpose of the utility model is to solve the problem that traditional single-stage voltage-stabilized power supplies are difficult to meet the requirements of high-performance application scenarios. Therefore, a two-stage cascade-regulated DC voltage-stabilized power supply scheme is proposed. The technical solution adopted to achieve the purpose of the utility model is: to provide a high-efficiency and low-ripple two-stage cascade-regulated DC voltage-stabilized power supply system, including a switching power supply, a main controller circuit, a power conversion circuit, an auxiliary power supply module, and a serial communication module. The main controller circuit is respectively connected to the power conversion circuit, the auxiliary power supply module, and the serial communication module. The main controller circuit is connected to the switching power supply through a gate driver for adjusting the output of the switching power supply. The main controller circuit controls the conversion of the power conversion circuit through an adjustment signal to obtain the actual output voltage, compares the actual output voltage with the set voltage for error comparison, and dynamically adjusts the output voltage through the PID algorithm; the auxiliary power supply module is used to provide a stable power supply voltage for the power conversion circuit and the serial communication module; the serial communication module is used for monitoring the output voltage and current.

[0005] Further, the main controller circuit includes a power supply circuit, a clock circuit, a reset circuit, and a peripheral interface; the power supply circuit is connected to the clock circuit, the reset circuit, and the peripheral interface, and the power supply circuit provides the required operating voltage for the clock circuit, the reset circuit, and the peripheral interface. The clock circuit provides a time base signal for timing and synchronization operations inside the main controller circuit. The reset circuit is used to restore the main controller circuit to its initial state when an abnormal state is detected or the reset button is pressed. The peripheral interface is used to implement communication and control with external devices. The main controller circuit is an STM32G431 chip.

[0006] Further, the power conversion circuit includes an anti-reverse connection circuit, a synchronous BUCK bucking circuit, and a PMOS linear voltage regulator circuit connected in sequence to the switching power supply. The anti-reverse connection circuit is used to protect the power supply input to the switching power supply against reverse connection and can disconnect the power supply when the power supply is connected reversely. The synchronous BUCK bucking circuit steps down the input power supply, and the output after stepping down is used to provide the input voltage for the linear voltage regulator. The PMOS linear voltage regulator circuit is used to step down the output voltage of the switching power supply, reduce the output noise of the switching power supply, and stabilize the output voltage.

[0007] Further, the anti-reverse connection circuit includes a diode anti-reverse connection, a rectifier bridge anti-reverse connection, an NMOS anti-reverse connection, and a PMOS anti-reverse connection circuit.

[0008] Further, the PMOS anti-reverse connection circuit includes a voltage input terminal VIN, a power supply U1, a triode Q1, a diode D1, a ground terminal A1, a ground terminal A2, and a resistor R3. The negative pole of the power supply U1 is connected to the ground terminal A1, the positive pole of the power supply U1 is connected to the positive pole of the triode Q1, the resistor R3 is connected to the ground terminal A2, the other end of the resistor R3 is respectively connected to the positive pole of the diode D1 and the triode Q1, and the negative pole of the diode D1 and the negative pole of the triode Q1 are connected to the voltage input terminal VIN.

[0009] Further, the synchronous BUCK bucking circuit obtains the output voltage of the switching power supply through a pulse width modulation control method. The output voltage of the switching power supply can be expressed as: V OUT = V IN ×D; D is the set duty cycle, then D = T ON / T S , the switching period is T S , then the switching frequency f s = 1 / T S , the conduction time is T ON , the turn-off time is T OFF , then T S = T ON + TOFF 。

[0010] Further, the NMOS in the synchronous BUCK bucking circuit is IRF3205PBF; the synchronous BUCK bucking circuit includes a driving circuit that converts the PWM control output by STM32G431 into sufficient driving voltage and driving current to ensure the normal conduction of the NMOS and reduce the on-resistance when the NMOS conducts, thereby improving the conversion efficiency.

[0011] Further, the PMOS linear voltage regulation circuit includes an error amplifier, a resistor voltage division network, a reference voltage source, a feedback network, and a PMOS power transistor. The resistor voltage division network obtains the output voltage of the reference voltage source to obtain a feedback voltage. The feedback voltage is applied to the non-inverting input terminal of the error amplifier for comparison with the reference voltage. After amplifying the difference of the comparison, it directly drives the PMOS power transistor to obtain a stable output voltage. When the LDO loop gain is large enough, the input terminal of the error amplifier is short-circuited, and the LDO output voltage can be expressed as:

[0012] Further, the PMOS power transistor is IRF4905.

[0013] Further, it further includes a human-computer interaction module, and the human-computer interaction module includes independent buttons, a rotary encoder, and an OLED screen, and the OLED screen uses IIC communication.

[0014] Compared with the prior art, the beneficial effects of the present utility model are as follows: The present utility model adopts a synchronous BUCK bucking circuit at the first stage to achieve efficient energy conversion, and at the same time, a PMOS linear voltage regulation circuit is adopted at the second stage for fine adjustment, thereby significantly suppressing the residual ripple and providing a stable and low-noise DC output. This design uses the PWM signal of the main controller to drive the NMOS to adjust the output of the switching power supply. At the same time, by comparing the output of the DAC with the feedback value of the error amplifier of the PMOS linear voltage regulator in real time, the output voltage is accurately regulated to reduce the voltage difference and ensure an efficient and low-ripple output effect. Through the strategy of coarse adjustment in the front stage and fine adjustment in the rear stage, the overall performance is optimized, the output ripple is significantly reduced, and a fast transient response is ensured. During actual testing, it was found that there was an error in the output current, and then a linear regression equation was obtained through data fitting, improving the current output accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The following shows the overall system block diagram of the present utility model;

[0016] Figure 2 The following shows the power conversion circuit structure of the present utility model;

[0017] Figure 3The figure shows the circuit diagram of the PMOS reverse connection prevention circuit of the present utility model;

[0018] Figure 4 The figure shows the basic structure of the PMOS linear voltage regulation circuit of the present utility model;

[0019] Among them, 10 - main controller circuit, 20 - power conversion circuit, 21 - reverse connection prevention circuit, 22 - synchronous BUCK step-down circuit, 23 - PMOS linear voltage regulation circuit, 30 - serial communication module, 40 - switching power supply. Specific embodiments

[0020] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without making creative efforts belong to the scope of protection of the present utility model.

[0021] As Figures 1-4 shown, the present utility model provides an efficient and low-ripple two-stage cascaded DC regulated power supply system, including a switching power supply 40, a main controller circuit 10, a power conversion circuit 20, an auxiliary power supply module, and a serial communication module 30. The main controller circuit 10 is used to control the switching state and adjust the output of the switching power supply 40. The main controller circuit 10 controls the power conversion circuit 20 to the actual output voltage through an adjustment signal, compares the actual output voltage with the set voltage, and dynamically adjusts the output voltage through a PID algorithm; the auxiliary power supply module is used to provide a stable power supply voltage for the system; the serial communication module 30 is used for monitoring the output voltage and current.

[0022] Specifically, in this system, the main controller circuit 10 drives the gate driver by outputting a PWM signal, and then controls the switching state of the NMOS to adjust the output of the switching power supply 40. At the same time, the main controller circuit 10 outputs an adjustment signal through the DAC. This signal is compared with the feedback value of the error amplifier of the linear voltage regulator, and then the output of the linear voltage regulator is adjusted according to the comparison result, so as to reduce the voltage difference between the two outputs, so as to achieve the output effect of high efficiency and low ripple. After the output voltage of each stage is sampled by the sampling resistor, it is sent to the A / D converter of the single-chip microcomputer to obtain the actual output voltage value. The actual output voltage is compared with the set voltage, and the output voltage is dynamically adjusted through a PID algorithm to ensure a stable voltage output even when the load changes.

[0023] The main controller circuit 10 includes a power supply circuit, a clock circuit, a reset circuit, and a peripheral interface; the STM32G431 chip is selected as the main controller circuit 10 of the system. The STM32G431 is a high-performance 32-bit microcontroller based on the ARM Cortex-M4 core, with a working frequency of 170 MHz, 128 KB of Flash memory, 12-bit ADC and DAC, operational amplifiers, comparators, timers, IIC, USART, internal voltage reference buffers, and other rich peripheral interfaces. The numerous peripheral interfaces of the STM32G431 can be used in this design, which is beneficial to simplifying the external design and saving costs. The power supply circuit, as the voltage supply center of the entire system, is directly connected to the power pins of the main controller circuit 10 (STM32G431 chip) to provide it with a stable operating voltage. In addition, the power supply circuit also provides the required operating voltage for other modules in the system (such as the power conversion circuit 20, auxiliary power supply module, etc.) through appropriate voltage conversion and filtering. Ensure that the main controller and other key components operate under a stable voltage to avoid performance degradation or failures caused by voltage fluctuations. The clock circuit is directly connected to the clock pins of the STM32G431 chip to provide it with an accurate time base signal. The clock signal is the basis for various timing and synchronization operations inside the microcontroller and has a direct impact on the operating speed and performance of the system. The reset circuit is connected to the reset pins of the STM32G431 chip and is used to send a reset signal to the chip when the system is powered on, the reset button is pressed, or an abnormal condition is detected, so that the system returns to the initial state. The STM32G431 chip has rich peripheral interfaces, including ADC, DAC, timers, IIC, USART, etc. These interfaces are connected to the core processing unit of the microcontroller through an internal bus to achieve communication and control with external devices.

[0024] Because three analog quantities, namely the output voltage of the switching power supply 40, the output voltage of the linear regulator, and the output current, need to be measured, but there are only two ADC cores inside the STM32G431, it is necessary to use the same core for multi-channel time-division multiplexing measurement. To maximize the ADC measurement accuracy, the analog quantities are connected to the OPAMP inside the STM32G431 before being connected to the ADC measurement, and after programmable gain, they are output from the OPAMP OUT to the ADC input channel. To improve the measurement accuracy of the output voltage and output current, the STM32G431 reallocates the OPAMP originally connected to the output sampling of the switching power supply 40 for DAC output. In addition, a 2.5V external reference voltage source REF25 interface is also reserved for the STM32G431.

[0025] The high-efficiency and low-ripple two-stage cascaded regulated DC power supply system also includes a human-machine interaction module. The human-machine interaction module includes independent buttons, a rotary encoder, and an OLED screen. The OLED screen uses IIC communication and can directly call the hardware IIC of STM32G431 for power-down data protection. Connect USART1 of STM32G431 to CH3E and connect to the host computer through a TYPE-C interface to achieve serial communication for monitoring the output voltage and current.

[0026] The power conversion circuit 20 mainly includes an anti-reverse connection circuit 21, a synchronous BUCK step-down circuit 22, and a PMOS linear voltage regulation circuit 23. The input power supply enters the load through the anti-reverse connection circuit 21, the synchronous BUCK step-down circuit 22, and the PMOS linear voltage regulation circuit 23 in sequence. The anti-reverse connection circuit 21 is used to protect against reverse connection of the input power supply and can disconnect the power supply when the power is connected reversely to protect the subsequent circuits. The synchronous BUCK step-down circuit 22 steps down the input power supply, and the stepped-down output is used to provide input for the linear voltage regulator. The stepped-down output of the synchronous BUCK step-down circuit 22 always tracks and is slightly higher than the output of the linear voltage regulator to maintain normal voltage regulation of the linear voltage regulator and improve its efficiency. The PMOS linear voltage regulation circuit 23 steps down the output voltage of the switching power supply 40, reduces the output noise of the switching power supply 40, and stabilizes the output voltage.

[0027] The anti-reverse connection circuit 21 includes a diode anti-reverse connection, a rectifier bridge anti-reverse connection, an NMOS anti-reverse connection, and a PMOS anti-reverse connection circuit.

[0028] Considering the loss to the system and the impact on system stability, the anti-reverse connection circuit 21 used in this embodiment is a PMOS anti-reverse connection circuit. Refer to Figure 3 , the PMOS anti-reverse connection circuit includes a voltage input terminal VIN, a power supply U1, a triode Q1, a diode D1, a ground terminal A1, a ground terminal A2, and a resistor R3. The negative pole of the power supply U1 is connected to the ground terminal A1, the positive pole of the power supply U1 is connected to the positive pole of the triode Q1, the resistor R3 is connected to the ground terminal A2, the other end of the resistor R3 is respectively connected to the positive pole of the diode D1 and the triode Q1, and the negative pole of the diode D1 and the negative pole of the triode Q1 are connected to the voltage input terminal VIN.

[0029] The anti-reverse connection circuit 21 utilizes the on-off characteristics of the PMOS transistor under specific conditions to achieve monitoring and protection of the power input direction. When the power supply is correctly connected, the PMOS transistor is in the on state, allowing current to pass through; when the power supply is connected reversely, the PMOS transistor automatically turns off, cutting off the current, thereby protecting the subsequent circuits from damage. To avoid PMOS damage caused by excessive V GS Use a zener diode to make VGS It stabilizes at 12V. At this time, the PMOS is fully conducting and the loss is small.

[0030] In this embodiment, a 28V input voltage is selected, and its voltage is transformed to obtain an output voltage of 0 - 24V. Then, the input voltage needs to be stepped down. The BUCK topology circuit is relatively simple and uses fewer components, which helps to reduce the manufacturing cost and improve the reliability. In order to reduce the energy loss during the switching process and achieve a higher conversion efficiency, a BUCK bucking circuit is selected. The synchronous BUCK bucking circuit 22 obtains the output voltage of the switching power supply 40 through a pulse width modulation control method. The output voltage of the switching power supply 40 can be expressed as: V OUT = V IN × D; D is the set duty cycle, then D = T ON / T S , the switching period is T S , then the switching frequency f s = 1 / T S , the conduction time is T ON , the turn-off time is T OFF , then T S = T ON + T OFF .

[0031] It can be known from the formula that the output voltage of the switching power supply 40 is related to the input voltage and the duty cycle. When the input voltage is fixed, the output voltage is proportional to the duty cycle. The larger the duty cycle, the larger the output voltage.

[0032] In this system, the ideal value of the input voltage is 28V. At this time, the ideal output voltage of the switching power supply 40: V OUT = 28 × D. During the actual operation process, the input voltage may drop, and the output voltage will also change with the change of the load. In order to maintain the stability of the output voltage, it is necessary to measure the output voltage of the switching power supply 40 and then perform dynamic adjustment through the PID algorithm.

[0033] In the synchronous BUCK bucking circuit 22, the NMOS is selected as IRF35PBF. The breakdown voltage from the drain to the source and the continuous drain current of this MOS all meet the requirements, and it has an extremely low on-resistance from the drain to the source, which can improve the conversion efficiency of the synchronous BUCK bucking circuit 22. The input and output capacitors are both ceramic capacitors. Their ESR is small, and the capacitance plays a decisive role in the ripple, which is beneficial to reducing the output ripple. The PWM output by STM32G431 is only 3.3V, which is not enough to drive the NMOS. Therefore, an additional EG3113 MOS driver circuit is required to convert the PWM control output by STM32G431 into a sufficient driving voltage and driving current to ensure the normal conduction of the NMOS and reduce the on-resistance when the NMOS is conducting to improve the conversion efficiency.

[0034] Reference Figure 4 The PMOS linear voltage regulator circuit 23 includes an error amplifier, a resistor voltage dividing network, a reference voltage source, a feedback network, and a PMOS power transistor. The reference voltage source is connected to one end of the error amplifier, the other end of the error amplifier is respectively connected to the resistor voltage dividing network and the PMOS power transistor, and the other end of the resistor voltage dividing network is connected to the feedback network.

[0035] The negative pole of the error amplifier is connected to the reference voltage source. The non-inverting input terminal of the error amplifier is connected to resistor R2 and resistor R1. The other end of resistor R2 is connected to the ground terminal B1. The other end of resistor R1 is respectively connected to the output voltage and the output terminal of the error amplifier. The output terminal of the error amplifier is connected to the PMOS power transistor. Resistor R1, capacitor C, and resistor R4 are connected in parallel. One end of capacitor C is connected to the output voltage V OUT is connected, and the other end of capacitor C is connected to the ground terminal B2. One end of resistor R4 is connected to the output voltage V OUT is connected, and the other end of resistor R4 is connected to the ground terminal B3.

[0036] The resistor voltage dividing network samples the output voltage to obtain a feedback voltage, adds the feedback voltage to the non-inverting input terminal of the error amplifier for comparison with the reference voltage (inverting input terminal), and directly drives the PMOS type power adjustment transistor after amplifying the difference of the comparison. A stable output voltage can be obtained by adjusting the conduction state of the power adjustment transistor. When the LDO loop gain is large enough, the input terminal of the error amplifier can be regarded as short-circuited (V REF =V FB ), and the LDO output voltage can be expressed as: When the voltage dividing resistors are determined, the output voltage can be adjusted by changing the reference voltage by adjusting the DAC output value.

[0037] In this embodiment, the voltage dividing resistors are low-temperature-drift high-precision resistors with a ratio of 10K to 100K. The low temperature drift can reduce the output temperature drift of the linear voltage regulator and reduce the thermal noise. The high precision can reduce the output error and improve the output precision. The ratio of 10K to 100K can reduce the full voltage output range within the ADC sampling and DAC output ranges, which is convenient for adjustment. Since the DAC uses a 2.5V reference voltage and the DAC resolution is 12 bits, assuming the DAC output variable is DACSET, the LDO output voltage at this time: The PMOS power transistor IRF4905 is selected. The breakdown voltage from the drain to the source, the continuous drain current, the dissipation power, etc. of this PMOS all meet the requirements, and the on-resistance from the drain to the source is relatively small, which is beneficial to reducing the minimum voltage difference of the linear regulator and improving the conversion efficiency. OPA2156 is a 36V ultra-low noise, high bandwidth, CMOS, precision rail-to-rail operational amplifier. It is selected as the error amplifier of the linear regulator, and its excellent performance can ensure the normal operation of the linear regulator, reduce the output ripple of the linear regulator, and accelerate the load response of the linear regulator.

[0038] The auxiliary power supply module provides a stable power supply voltage for the gate driver, the error amplifier, the single-chip microcomputer, and the OLED. In this embodiment, the power supply voltages required by each part are different. The power supply voltage required by the MOS transistor drive circuit is relatively high compared to other parts, which is 8V, and the power supply voltages required by the other parts of the system are all 5V or 3.3V. The system input voltage is 28V, and this voltage needs to be stepped down to 8V, 5V, and 3.3V.

[0039] In some embodiments, the gate driver uses a MOS transistor. The voltage difference from 28V to 8V is relatively large, and the MOS transistor has low requirements for power supply voltage noise. Therefore, the MP9942 synchronous buck converter is selected to step down 28V. The MP2225 synchronous buck converter is used for the step-down conversion from 8V to 5V. The 3.3V power supply is mainly used to supply power to the instrumentation amplifier, the single-chip microcomputer, and each peripheral module. The normal operation of the instrumentation amplifier and the single-chip microcomputer, etc. has relatively high requirements for the power supply quality. Therefore, a switching power supply (40) with relatively high noise is not selected for step-down, but an LDO chip RT9013-33G with relatively low noise is selected for step-down.

[0040] The above is a specific description of the preferred embodiment of the present disclosure, but the present disclosure is not limited to the above-mentioned implementation manners. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present disclosure, and these equivalent deformations or substitutions are all included within the scope defined by the claims of the present disclosure.

Claims

1. An efficient low-ripple two-stage regulated DC power supply system, characterized in that: It includes a switching power supply (40), a main controller circuit (10), a power conversion circuit (20), an auxiliary power supply module, and a serial communication module (30). The main controller circuit (10) is respectively connected to the power conversion circuit (20), the auxiliary power supply module, and the serial communication module (30). The main controller circuit (10) is connected to the switching power supply (40) through a gate driver and is used to adjust the output of the switching power supply (40). The main controller circuit (10) controls the conversion of the power conversion circuit (20) through an adjustment signal to obtain the actual output voltage, compares the error between the actual output voltage and the set voltage, and dynamically adjusts the output voltage through the PID algorithm. The auxiliary power supply module is used to provide a stable power supply voltage for the power conversion circuit (20) and the serial communication module (30). The serial communication module (30) is used for monitoring the output voltage and current.

2. An efficient low-ripple two-stage cascaded regulated DC power supply system according to claim 1, characterized in that: The main controller circuit (10) includes a power supply circuit, a clock circuit, a reset circuit, and a peripheral interface. The power supply circuit is connected to the clock circuit, the reset circuit, and the peripheral interface. The power supply circuit provides the required working voltage for the clock circuit, the reset circuit, and the peripheral interface. The clock circuit provides a time base signal for timing and synchronization operations inside the main controller circuit (10). The reset circuit is used to restore the main controller circuit (10) to its initial state when an abnormal state is detected or the reset button is pressed. The peripheral interface is used to realize communication and control with external devices. The main controller circuit (10) is an STM32G431 chip.

3. An efficient low-ripple two-stage cascaded regulated DC power supply system according to claim 2, characterized in that: The power conversion circuit (20) includes an anti-reverse connection circuit (21), a synchronous BUCK step-down circuit (22), and a PMOS linear voltage regulator circuit (23) that are sequentially connected to the switching power supply (40). The anti-reverse connection circuit (21) is used to protect against reverse connection of the power supply input by the switching power supply (40) and can disconnect the power supply when the power supply is connected reversely. The synchronous BUCK step-down circuit (22) steps down the input power supply, and the output after stepping down is used to provide an input voltage for the linear voltage regulator. The PMOS linear voltage regulator circuit (23) is used to step down the output voltage of the switching power supply (40), reduce the output noise of the switching power supply (40), and stabilize the output voltage.

4. An efficient low-ripple two-stage cascaded regulated DC power supply system according to claim 3, characterized in that: The anti-reverse connection circuit (21) includes a diode anti-reverse connection, a rectifier bridge anti-reverse connection, an NMOS anti-reverse connection, and a PMOS anti-reverse connection circuit.

5. An efficient low-ripple two-stage cascaded regulated DC power supply system according to claim 4, characterized in that: The PMOS anti-reverse connection circuit includes a voltage input terminal VIN, a power supply U1, a triode Q1, a diode D1, a ground terminal A1, a ground terminal A2, and a resistor R3. The negative pole of the power supply U1 is connected to the ground terminal A1, the positive pole of the power supply U1 is connected to the positive pole of the triode Q1, the resistor R3 is connected to the ground terminal A2, the other end of the resistor R3 is respectively connected to the positive pole of the diode D1 and the triode Q1, and the negative pole of the diode D1 and the negative pole of the triode Q1 are connected to the voltage input terminal VIN.

6. An efficient low-ripple two-stage cascaded regulated DC power supply system according to claim 3, characterized in that: The synchronous BUCK bucking circuit (22) obtains the output voltage of the switching power supply (40) through pulse width modulation control. The output voltage of the switching power supply (40) is: V OUT = V IN × D; D is the set duty cycle, then D = T ON / T S , the switching period is T S , then the switching frequency f s = 1 / T S , the conduction time is T ON , the turn-off time is T OFF , then T S = T ON + T OFF .

7. An efficient low-ripple two-stage cascaded regulated DC power supply system according to claim 6, characterized in that: The NMOS in the synchronous BUCK step-down circuit (22) is IRF3205PBF; the synchronous BUCK step-down circuit (22) includes a drive circuit that converts the PWM control output by STM32G431 into sufficient drive voltage and drive current to ensure the normal conduction of the NMOS and reduce the on-resistance when the NMOS is conducting to improve the conversion efficiency.

8. An efficient low-ripple two-stage cascaded regulated DC power supply system according to claim 3, characterized in that: The PMOS linear voltage regulator circuit (23) includes an error amplifier, a resistor voltage division network, a reference voltage source, a feedback network, and a PMOS power transistor. The resistor voltage division network obtains the output voltage of the reference voltage source to obtain a feedback voltage. The feedback voltage is applied to the non-inverting input terminal of the error amplifier to be compared with a reference voltage. After amplifying the difference of the comparison, it directly drives the PMOS power transistor to obtain a stable output voltage. When the LDO loop gain is large enough, the input terminal of the error amplifier is short-circuited, and the LDO output voltage can be expressed as:

9. An efficient low-ripple two-stage cascaded regulated DC power supply system according to claim 8, characterized in that: The PMOS power transistor is IRF4905.

10. An efficient low-ripple two-stage cascaded regulated DC power supply system according to claim 1, characterized in that: It further includes a human-machine interaction module, and the human-machine interaction module includes independent buttons, a rotary encoder, and an OLED screen, and the OLED screen uses IIC communication.

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