Delay on-off control circuit of multi-channel chip power supply and electronic equipment

Abstract

The utility model discloses a delay on-off control circuit of a multi-channel chip power supply and electronic equipment. The delay on-off control circuit comprises a delay control unit and at least one first switch control unit and / or second switch control unit, wherein a plurality of output ends of the delay control unit are correspondingly connected with control ends of the first switch control unit and the second switch control unit respectively; the input end of the first switch control unit is connected with a negative voltage source, and the output end is connected with the power end of the first integrated circuit chip; the input end of the second switch control unit is connected with the positive voltage source, and the output end is connected with the power supply end of the second integrated circuit chip; and the delay control unit is used for controlling the working states of the first switch control unit and the second switch control unit and providing accurate power-on and power-off delay control for the first integrated circuit chip and the second integrated circuit chip.

Description

Technical Field

[0001] The utility model relates to a delay on-off control circuit for a multi-channel chip power supply, and also relates to an electronic device including the delay on-off control circuit, belonging to the technical field of power supply control. Background Art

[0002] With the rapid development of integrated circuit technology, an electronic device usually includes multiple integrated circuit chips with different functions. During the actual operation of these integrated circuit chips in the electronic device, there are usually certain requirements for the on-off delay time, so as to realize the power-on or power-off operations of multiple integrated circuit chips in a certain preset order, make the power supply voltage stable, the internal signal transmission smooth, and ensure the normal operation of the electronic device.

[0003] In the prior art, the on-off delay control of the above-mentioned multiple integrated circuit chips is usually realized by a control circuit composed of a capacitor and a resistor. This control circuit cannot perform delay control at the second level, millisecond level or even higher time levels for the delay time, which is likely to cause waste of on-off time during the startup or shutdown process of the application system or electronic device, reduce work efficiency, and due to the limitation of the capacitance storage capacity, it is difficult for this control circuit to achieve a long-time delay control. At the same time, when the on-off delay time requirements of multiple integrated circuit chips change, this control circuit cannot be adjusted at any time and must be realized by replacing electronic components. On the other hand, when there are errors in the on-off delay control of multiple integrated circuit chips, it will affect signal transmission and even cause phenomena such as data loss and file damage, reducing the reliability of the operation of the application system or electronic device. In addition, this control circuit cannot realize the on-off delay control when the power supply of the integrated circuit chip is a negative voltage.

[0004] In the Chinese utility model patent with the patent number ZL 202123432433.9, a circuit for power supply delay is disclosed. This circuit uses a PMOS switch tube as the switching device for controlling the power supply on and off, and uses an RC delay unit as the delay device. When the voltage of the RC delay unit reaches a stable value, the PMOS switch tube conducts to supply the IC chip, avoiding the influence of voltage fluctuation at the moment of power-on on the subsequent load. Summary of the Invention

[0005] The primary technical problem to be solved by the utility model is to provide a delay on-off control circuit for a multi-channel chip power supply.

[0006] Another technical problem to be solved by the utility model is to provide an electronic device including the above delay on-off control circuit.

[0007] To achieve the above object, the utility model adopts the following technical solutions:

[0008] According to the first aspect of the embodiments of the present invention, a delay on-off control circuit for a multi-channel chip power supply is provided, including a delay control unit, at least one first switch control unit and / or a second switch control unit; wherein, the delay control unit is implemented by a main controller;

[0009] Multiple output terminals of the delay control unit are respectively and correspondingly connected to control terminals of the first switch control unit and the second switch control unit;

[0010] An input terminal of the first switch control unit is connected to a negative voltage source, and an output terminal is connected to a power supply terminal of a first integrated circuit chip; the power supply of the first integrated circuit chip is a negative voltage source;

[0011] An input terminal of the second switch control unit is connected to a positive voltage source, and an output terminal is connected to a power supply terminal of a second integrated circuit chip; the power supply of the second integrated circuit chip is a positive voltage source;

[0012] The first switch control unit is used to turn on or off the power supply of the first integrated circuit chip; the second switch control unit is used to turn on or off the power supply of the second integrated circuit chip;

[0013] The delay control unit is used to control the working states of the first switch control unit and the second switch control unit, and provide accurate on-off delay control for the first integrated circuit chip and the second integrated circuit chip.

[0014] Preferably, the first switch control unit includes a first PMOS transistor, a first NMOS transistor, a first resistor, a second resistor and a first diode; wherein,

[0015] The first diode is an anti-connected diode to make the output voltage of the first switch control unit equal to the input negative voltage.

[0016] Preferably, the gate of the first PMOS transistor is connected to the source through the first resistor and is also connected to the ground potential terminal; the source of the first PMOS transistor is used as a control terminal and is connected to the first output terminal of the main controller; the drain of the first PMOS transistor is connected to the gate of the first NMOS transistor, the gate of the first NMOS transistor is connected to the source through the second resistor, the source of the first NMOS transistor is used as an input terminal and is connected to the negative voltage source; the drain of the first NMOS transistor is used as an output terminal and is connected to the power supply terminal of the first integrated circuit chip and also to the positive extreme of the first diode, and the negative extreme of the first diode is connected to the ground potential terminal.

[0017] Preferably, the second switch control unit includes a first NPN transistor, a second PMOS transistor, a third resistor, a fourth resistor, a fifth resistor, and a second diode; wherein,

[0018] The second diode is an anti-connected diode to make the output voltage of the second switch control unit equal to the input positive voltage.

[0019] Preferably, one end of the emitter of the first NPN transistor is connected to the base through the fourth resistor, and the other end is connected to the ground potential terminal; the base of the first NPN transistor is connected to the second output terminal of the main controller as a control terminal after being connected in series with the third resistor; the collector of the first NPN transistor is connected to the gate of the second PMOS transistor, the gate of the second PMOS transistor is connected to the source through the fifth resistor, the source of the second PMOS transistor is connected to the first positive voltage source as an input terminal, the drain of the second PMOS transistor is connected to the power supply terminal of the second integrated circuit chip as an output terminal and is also connected to the negative terminal of the second diode, and the positive terminal of the second diode is connected to the ground potential terminal.

[0020] According to the second aspect of the embodiments of the present invention, an electronic device is provided, which includes the above-mentioned delay on-off control circuit for multiple-chip power supplies.

[0021] Compared with the prior art, the delay on-off control circuit for multiple-chip power supplies provided by the present invention realizes accurate control and management of the on-off and delay time of multiple integrated circuit chips by adopting a technical solution combining a delay control unit, a first switch control unit, and a second switch control unit. Therefore, the delay on-off control circuit for multiple-chip power supplies provided by the present invention has beneficial effects such as a clever and reasonable structural design, a low design cost, high working efficiency, accurately adjustable delay time, and high reliability. Description of the Drawings

[0022] Figure 1 It is a structural block diagram of a delay on-off control circuit for multiple-chip power supplies provided by an embodiment of the present invention;

[0023] Figure 2 It is a schematic wiring diagram of the delay on-off control circuit for multiple-chip power supplies in an embodiment of the present invention. Detailed Embodiments

[0024] The technical content of the present invention will be described in detail below with reference to the drawings and specific embodiments.

[0025] Such as Figure 1As shown in the figure, a delay on / off control circuit 100 for a multi-channel chip power supply provided by an embodiment of the present utility model includes a delay control unit, at least one first switch control unit, and / or a second switch control unit. Among them, multiple output terminals of the delay control unit are respectively connected to the control terminals of the first switch control unit and the second switch control unit; the input terminal of the first switch control unit is connected to a negative voltage source, and the output terminal is connected to the power supply terminal of the first integrated circuit chip; the input terminal of the second switch control unit is connected to a positive voltage source, and the output terminal is connected to the power supply terminal of the second integrated circuit chip. The first integrated circuit chip is Figure 1 respectively multiple negative voltage power supply chips numbered 11 - 1n in Figure 1 respectively multiple positive voltage power supply chips numbered 21 - 2m in

[0026] The delay control unit is used to control the working states of one or more first switch control units and one or more second switch control units, so as to provide accurate on / off delay control for one or more first integrated circuit chips and one or more second integrated circuit chips. The delay control unit can be implemented by a main controller, such as a microcontroller (MCU), a digital signal processor (DSP), etc., which accurately controls the on / off delay time of the multi-channel chip power supply by writing a control program.

[0027] The first switch control unit is used to connect or disconnect the power supply for the first integrated circuit chip. The second switch control unit is used to connect or disconnect the power supply for the second integrated circuit chip.

[0028] The delay on / off control circuit of the multi-channel chip power supply accurately controls the working states of the first switch control unit and the second switch control unit according to the delay time preset by the delay control unit, so as to realize the on / off and its delay control when the multi-channel power supplies supply power to multiple first integrated circuit chips and / or second integrated circuit chips respectively.

[0029] In an embodiment of the present utility model, as Figure 2 shown, assume that there are three integrated circuit chips with different functions in an application system or an electronic device. Among them, chip 11 is the first integrated circuit chip powered by a negative voltage source, and chips 21 and 22 are the second integrated circuit chips powered by a positive voltage source.

[0030] In an embodiment of the present utility model, the delay on-off control circuit includes a delay control unit, a first switch control unit, and two second switch control units. The delay control unit is implemented by a main controller. Among them, the first output terminal IO_1 of the main controller is connected to the control terminal of the first switch control unit, and the second output terminal IO_2 and the third output terminal IO_3 of the main controller are respectively connected to the control terminals of the two second switch control units in correspondence; the input terminal of the first switch control unit is connected to the negative voltage source VEE, and the output terminal is connected to the power supply terminal of the first integrated circuit chip 11; the input terminals of the two second switch control units are respectively connected to the two positive voltage sources VCC1 and VCC2 in correspondence, and the output terminals are respectively connected to the power supply terminals of the two second integrated circuit chips 21 and 22 in correspondence.

[0031] The first switch control unit includes a first PMOS transistor Q1, a first NMOS transistor Q2, a first resistor R1, a second resistor R2, and a first diode D1. Among them, the gate of the first PMOS transistor Q1 is connected to the source through the first resistor R1 on the one hand and to the ground potential terminal on the other hand; the source of the first PMOS transistor Q1 is used as the control terminal and is connected to the first output terminal IO_1 of the main controller; the drain of the first PMOS transistor Q1 is connected to the gate of the first NMOS transistor Q2, the gate of the first NMOS transistor Q2 is connected to the source through the second resistor R2, and the source of the first NMOS transistor Q2 is used as the input terminal and is connected to the negative voltage source VEE; the drain of the first NMOS transistor Q2 is used as the output terminal and is connected to the power supply terminal of the first integrated circuit chip 11 on the one hand and to the positive extreme of the first diode D1 on the other hand, and the negative extreme of the first diode D1 is connected to the ground potential terminal.

[0032] The circuit structures of the two second switch control units are the same. Hereinafter, the second switch control unit connected to the second integrated circuit chip 21 will be taken as an example for description.

[0033] The second switch control unit includes a first NPN transistor Q3, a second PMOS transistor Q4, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a second diode D2. Among them, the emitter of the first NPN transistor Q3 is connected to the base through the fourth resistor R4 on the one hand and to the ground potential terminal on the other hand; the base of the first NPN transistor Q3 is connected in series with the third resistor R3 and used as the control terminal and is connected to the second output terminal IO_2 of the main controller; the collector of the first NPN transistor Q3 is connected to the gate of the second PMOS transistor Q4, the gate of the second PMOS transistor Q4 is connected to the source through the fifth resistor R5, the source of the second PMOS transistor Q4 is used as the input terminal and is connected to the first positive voltage source VCC1, and the drain of the second PMOS transistor Q4 is used as the output terminal and is connected to the power supply terminal of the second integrated circuit chip 21 on the one hand and to the negative extreme of the second diode D2 on the other hand, and the positive extreme of the second diode D2 is connected to the ground potential terminal.

[0034] The second switch control unit connected to the second integrated circuit chip 22 includes a second NPN transistor Q5, a third PMOS transistor Q6, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a third diode D3. The difference between this second switch control unit and the former is that its control terminal is connected to the third output terminal IO_3 of the main controller, its input terminal is connected to the second positive voltage source VCC2, and its output terminal is connected to the power supply terminal of the second integrated circuit chip 22.

[0035] In the delay on / off control circuit for multiple-chip power supplies provided by the embodiments of the present invention, the number of the first switch control unit and the second switch control unit included can be determined according to the number of the first integrated circuit chip and the second integrated circuit chip included in the application system or electronic device where it is located. Among them, the supply voltages of each chip can be the same or different. Next, the working principle of the delay on / off control circuit provided in this embodiment will be described in detail.

[0036] When the application system or electronic device needs to start working, in this delay on / off control circuit for multiple-chip power supplies, after the delay control unit, i.e., the main controller, is powered on, it starts power-on timing. Assume that the power-on delay time of the first integrated circuit chip 11 is set as the first time t1, the power-on delay time of the second integrated circuit chip 21 is set as the second time t2, and the power-on delay time of the second integrated circuit chip 22 is set as the third time t3.

[0037] When the power-on timing time of the main controller reaches the first time t1, the voltage at the first output terminal IO_1 of the main controller changes from low level to high level. At this time, in the first switch control unit, after the first PMOS transistor Q1 is turned on, the gate of the first NMOS transistor Q2 becomes high level. Therefore, the first NMOS transistor Q2 is also turned on, and the negative voltage source VEE starts to supply power to the first integrated circuit chip 11 through the turned-on first NMOS transistor Q2.

[0038] In the first switch control unit, the first diode D1 is an anti-connected diode, and the branch where it is located is in an equivalent open-circuit state, so that the voltage across both ends of the first diode D1 is equal to the negative voltage source VEE, that is, the output voltage of the first switch control unit is equal to the input negative voltage, which is used to ensure that the supply voltage of the first integrated circuit chip 11 is not divided by the branch where the first NMOS transistor Q2 is located, improving the supply quality of the first integrated circuit chip 11 and at the same time reducing the power consumption of the first switch control unit itself.

[0039] When the power-on timing time of the main controller reaches the second time t2, the level at the second output terminal IO_2 of the main controller changes from low level to high level. At this time, in the second switch control unit connected to the second integrated circuit chip 21, after the first NPN transistor Q3 conducts, the gate of the second PMOS transistor Q4 becomes low level. Therefore, the second PMOS transistor Q4 conducts, and the first positive voltage source VCC1 starts to supply power to the second integrated circuit chip 21 through the conducting second PMOS transistor Q4.

[0040] In the second switch control unit connected to the second integrated circuit chip 21, the second diode D2 is an anti-connected diode, and the branch where it is located is in an equivalent open-circuit state, making the voltage across the two ends of the second diode D2 equal to the first positive voltage source VCC1, that is, the output voltage of the second switch control unit is equal to the input positive voltage, which is used to ensure that the power supply voltage of the second integrated circuit chip 21 is not divided by the branch where the second PMOS transistor Q4 is located, improving the power supply quality of the second integrated circuit chip 21 and also reducing the power consumption of the second switch control unit itself.

[0041] Similarly, when the power-on timing time of the main controller reaches the third time t3, the level at the third output terminal IO_3 of the main controller changes from low level to high level. At this time, in the second switch control unit connected to the second integrated circuit chip 22, after the second NPN transistor Q5 conducts, the gate of the third PMOS transistor Q6 becomes low level. Therefore, the third PMOS transistor Q6 conducts, and the second positive voltage source VCC2 starts to supply power to the second integrated circuit chip 22 through the conducting third PMOS transistor Q6. The third diode D3 is an anti-connected diode, and its function is the same as that of the above-mentioned second diode D2.

[0042] It should be noted that in an application system or an electronic device, the power-on sequence of one or more first integrated circuit chips and one or more second integrated circuit chips is determined by the power-on delay time of each chip. This delay time can be conveniently preset or adjusted through the delay control unit.

[0043] When the application system or the electronic device needs to shut down and stop working, in the delay on-off control circuit of the multi-channel chip power supply, the level at the communication port IO_0 of the delay control unit, that is, the main controller, changes from high level to low level. At this time, the main controller starts to power off and time. Assume that the power-off delay time of the first integrated circuit chip 11 is set to the eleventh time t11, the power-off delay time of the second integrated circuit chip 21 is set to the twelfth time t12, and the power-off delay time of the second integrated circuit chip 22 is set to the thirteenth time t13.

[0044] When the power-down timing time of the main controller reaches the eleventh time t11, the level at the first output terminal IO_1 of the main controller changes from high level to low level. At this time, in the first switch control unit, after the first PMOS transistor Q1 is turned off, the gate of the first NMOS transistor Q2 becomes low level. Therefore, the first NMOS transistor Q2 is also turned off, disconnecting the path that provides the negative voltage source VEE for the first integrated circuit chip 11, and the first integrated circuit chip 11 is powered off.

[0045] When the power-down timing time of the main controller reaches the twelfth time t12, the level at the second output terminal IO_2 of the main controller changes from high level to low level. At this time, in the second switch control unit connected to the second integrated circuit chip 21, after the first NPN transistor Q3 is turned off, the gate of the second PMOS transistor Q4 becomes high level. Therefore, the second PMOS transistor Q4 is also turned off, disconnecting the path that provides the first positive voltage source VCC1 for the second integrated circuit chip 21, and the second integrated circuit chip 21 is powered off.

[0046] Similarly, when the power-down timing time of the main controller reaches the thirteenth time t13, the level at the third output terminal IO_3 of the main controller changes from high level to low level. At this time, in the second switch control unit connected to the second integrated circuit chip 22, after the second NPN transistor Q5 is turned off, the gate of the third PMOS transistor Q6 becomes high level. Therefore, the third PMOS transistor Q6 is also turned off, disconnecting the path that provides the second positive voltage source VCC2 for the second integrated circuit chip 22, and the second integrated circuit chip 22 is powered off.

[0047] It should be noted that in an application system or an electronic device, the power-down sequence of one or more first integrated circuit chips and one or more second integrated circuit chips is also determined by the power-down delay time of each chip. This delay time can be conveniently preset or adjusted through the delay control unit.

[0048] The working principle of the delay on-off control circuit for the multi-channel chip power supply provided by the embodiment of the present invention is described in detail above. By accurately setting the on-off delay time of multiple integrated circuit chips in an application system or an electronic device through the delay control unit, and coordinating the on or off operations of multiple first switch control units and / or second switch control units for multiple power paths, the orderly on-off management of multiple chips in the application system or the electronic device is realized.

[0049] Based on the above-mentioned delay on-off control circuit for multi-channel chip power supply, an embodiment of the present invention further provides an electronic device. In addition to including multiple integrated circuit chips with different functions, the electronic device also includes the above-mentioned delay on-off control circuit for multi-channel chip power supply, which is used to accurately control the on-off and delay time management of multiple integrated circuit chips, so that each functional unit inside the electronic device works orderly and the reliability of the operation of the electronic device is improved. The specific structure of the delay on-off control circuit for multi-channel chip power supply in this electronic device will not be elaborated here.

[0050] In summary, compared with the prior art, the delay on-off control circuit for multi-channel chip power supply provided by the present invention realizes the accurate control and management of the on-off and delay time of multi-channel integrated circuit chips by adopting the technical solution combining a delay control unit, a first switch control unit and a second switch control unit. Therefore, the delay on-off control circuit for multi-channel chip power supply provided by the present invention has beneficial effects such as ingenious and reasonable structural design, low design cost, high working efficiency, accurately adjustable delay time and high reliability, and is particularly suitable for application systems or electronic device scenarios with multiple integrated circuit chips powered by positive voltage sources and / or negative voltage sources.

[0051] It should be noted that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more, unless otherwise specifically defined.

[0052] The above has described in detail the delay on-off control circuit for multi-channel chip power supply and the electronic device provided by the present invention. For those of ordinary skill in the art, any obvious modification made without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A delay on / off control circuit for a multi-channel chip power supply, characterized in that It includes a delay control unit, at least one first switch control unit and / or a second switch control unit; wherein, the delay control unit is implemented by a main controller; Multiple output terminals of the delay control unit are respectively and correspondingly connected to control terminals of the first switch control unit and the second switch control unit; An input terminal of the first switch control unit is connected to a negative voltage source, and an output terminal is connected to a power supply terminal of a first integrated circuit chip; the power supply of the first integrated circuit chip is the negative voltage source; An input terminal of the second switch control unit is connected to a positive voltage source, and an output terminal is connected to a power supply terminal of a second integrated circuit chip; the power supply of the second integrated circuit chip is the positive voltage source; The first switch control unit is used to turn on or off the power supply of the first integrated circuit chip; the second switch control unit is used to turn on or off the power supply of the second integrated circuit chip; The delay control unit is used to control the working states of the first switch control unit and the second switch control unit, and provide accurate on / off delay control for the first integrated circuit chip and the second integrated circuit chip.

2. The delay on / off control circuit for a multi-channel chip power supply according to claim 1, wherein: The first switch control unit includes a first PMOS transistor, a first NMOS transistor, a first resistor, a second resistor and a first diode; wherein, The first diode is an anti-connected diode to make the output voltage of the first switch control unit equal to the input negative voltage.

3. The delay on / off control circuit for a multi-channel chip power supply according to claim 2, wherein: The gate of the first PMOS transistor is connected to the source through the first resistor on one hand and to the ground potential terminal on the other hand; the source of the first PMOS transistor is used as a control terminal and connected to the first output terminal of the main controller; the drain of the first PMOS transistor is connected to the gate of the first NMOS transistor, the gate of the first NMOS transistor is connected to the source through the second resistor, the source of the first NMOS transistor is used as an input terminal and connected to the negative voltage source; the drain of the first NMOS transistor is used as an output terminal and connected to the power supply terminal of the first integrated circuit chip on one hand and to the positive extreme of the first diode on the other hand, and the negative extreme of the first diode is connected to the ground potential terminal.

4. The delay on / off control circuit for a multi-channel chip power supply according to claim 1, wherein: The second switch control unit includes a first NPN transistor, a second PMOS transistor, a third resistor, a fourth resistor, a fifth resistor and a second diode; wherein, The second diode is an anti-connected diode to make the output voltage of the second switch control unit equal to the input positive voltage.

5. The delay on / off control circuit for a multi-channel chip power supply according to claim 4, wherein: The emitter of the first NPN transistor is connected to the base through the fourth resistor on one hand and to the ground potential terminal on the other hand; the base of the first NPN transistor is connected in series with the third resistor and then used as a control terminal to be connected to the second output terminal of the main controller; the collector of the first NPN transistor is connected to the gate of the second PMOS transistor, the gate of the second PMOS transistor is connected to the source through the fifth resistor, the source of the second PMOS transistor is used as an input terminal to be connected to the first positive voltage source, the drain of the second PMOS transistor is used as an output terminal and is connected to the power supply terminal of the second integrated circuit chip on one hand and to the negative extreme of the second diode on the other hand, and the positive extreme of the second diode is connected to the ground potential terminal.

6. An electronic device, characterized in that It includes the delay on / off control circuit for the multi-channel chip power supply according to any one of claims 1 to 5.

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