Semiconductor device

Abstract

A semiconductor device includes a plurality of first nanostructure channels, a plurality of second nanostructure channels, a first metal gate structure, a second metal gate structure, a gate isolation structure and an active region isolation structure. The first nanostructure channel is located on a first convex region extending onto the semiconductor substrate and is arranged in a direction perpendicular to the semiconductor substrate. The second nanostructure channel is located on a second convex region extending onto the semiconductor substrate and is arranged in a direction perpendicular to the semiconductor substrate. A first metal gate structure surrounds each of the first nanostructure channels. A second metal gate structure surrounds each of the second nanostructure channels. The gate isolation structure is located between the first and second metal gate structures. The active region isolation structure is located between the gate isolation structure and the second metal gate structure, a dielectric liner of the active region isolation structure is directly contained on the side wall of the gate isolation structure, and the bottom of the active region isolation structure comprises a convex part section and a shallow trench isolation region section.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Art

[0002] With the progress of semiconductor device manufacturing and the reduction of the size of the technology processing nodes, transistors have become susceptible to short-channel effects (SCEs), such as hot carrier degradation effects, energy barrier reduction, and quantum confinement, etc. In addition, as the gate length of the transistors decreases due to smaller technology nodes, source / drain (S / D) electron tunneling also increases, increasing the off-current of the transistors (the current passing through the transistor channel region when the transistor is in the off state). Silicon (Si) / silicon germanium (SiGe) nanostructure transistors, such as nanowires, nanosheets, and gate-all-around (GAA) devices, are potential candidates for overcoming short-channel effects at smaller technology nodes. Nanostructure transistors are effective structures that can have reduced SCEs and enhanced carrier mobility compared to other types of transistors. Summary of the Utility Model

[0003] An embodiment of this disclosure includes a semiconductor device, including a plurality of first nanostructure channels, a plurality of second nanostructure channels, a first metal gate structure, a second metal gate structure, a gate isolation structure, and an active region isolation structure. The first nanostructure channels are located on a first protrusion region extending onto a semiconductor substrate, wherein the first nanostructure channels are arranged in a direction perpendicular to the semiconductor substrate. The second nanostructure channels are located on a second protrusion region extending onto the semiconductor substrate, wherein the second nanostructure channels are arranged in a direction perpendicular to the semiconductor substrate. The first metal gate structure surrounds each of the first nanostructure channels. The second metal gate structure surrounds each of the second nanostructure channels. The gate isolation structure is located between the first metal gate structure and the second metal gate structure. The active region isolation structure is located between the gate isolation structure and the second metal gate structure, wherein a dielectric liner of the active region isolation structure is directly included on sidewalls of the gate isolation structure, and wherein a bottom of the active region isolation structure includes a protrusion section and one or more shallow trench isolation sections. The protrusion section extends into the semiconductor substrate. The shallow trench isolation sections are located under the protrusion section.

[0004] One embodiment of the present disclosure includes a semiconductor device, which includes a plurality of first nanostructured channels, a plurality of second nanostructured channels, source / drain regions, a first metal gate structure, a second metal gate structure, a gate isolation structure, and an active region isolation structure. The first nanostructured channels are located on a first protrusion region extending onto a semiconductor substrate, wherein the first nanostructured channels are arranged in a direction perpendicular to the semiconductor substrate. The second nanostructured channels are located on a second protrusion region extending onto the semiconductor substrate, wherein the second nanostructured channels are arranged in a direction perpendicular to the semiconductor substrate. The source / drain regions are adjacent to the first nanostructured channels. The first metal gate structure surrounds each of the first nanostructured channels. The second metal gate structure surrounds each of the second nanostructured channels. The gate isolation structure is located between the first metal gate structure and the second metal gate structure. The active region isolation structure is located between the gate isolation structure and the second metal gate structure, wherein the dielectric liner of the active region isolation structure is directly included on the sidewalls of the gate isolation structure.

[0005] One embodiment of the present disclosure includes a semiconductor device, which includes a plurality of first nanostructured channels, a plurality of second nanostructured channels, a hybrid fin structure, a first metal gate structure, a second metal gate structure, a gate isolation structure, and an active region isolation structure. The first nanostructured channels are located on a first protrusion region extending onto a semiconductor substrate, wherein the first nanostructured channels are arranged in a direction perpendicular to the semiconductor substrate. The second nanostructured channels are located on a second protrusion region extending onto the semiconductor substrate, wherein the second nanostructured channels are arranged in a direction perpendicular to the semiconductor substrate. The hybrid fin structure is located between the first nanostructured channels and the second nanostructured channels. The first metal gate structure surrounds each of the first nanostructured channels. The second metal gate structure surrounds each of the second nanostructured channels. The gate isolation structure is located between the first metal gate structure and the second metal gate structure. The active region isolation structure is located between the gate isolation structure and the second metal gate structure, wherein the dielectric liner of the active region isolation structure is directly included on the sidewalls of the gate isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, aspects of the present disclosure may be best understood. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1 is a schematic diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 2 is a schematic diagram of an example semiconductor device described herein;

[0009] Figure 3Aand Figure 3B is a schematic diagram of an embodiment of the fin structure forming process described herein;

[0010] Figure 4A and Figure 4B is a schematic diagram of an embodiment of the shallow trench isolation (STI) process described herein;

[0011] Figures 5A to 5C is a schematic diagram of an embodiment of the sidewall coating forming process described herein;

[0012] Figures 6A to 6C is a schematic diagram of an embodiment of the hybrid fin structure forming process described herein;

[0013] Figure 7A and Figure 7B is a schematic diagram of an example dummy gate structure forming process described herein;

[0014] Figures 8A to 8E is a schematic diagram of an embodiment of the source / drain region forming process described herein;

[0015] Figures 9A to 9I is a schematic diagram of an embodiment of the active region isolation structure forming process described herein;

[0016] Figures 10A to 10D is a schematic diagram of an embodiment of the replacement gate process described herein;

[0017] Figures 11A to 11I is a schematic diagram of an embodiment of the active region isolation structure forming process described herein;

[0018] Figure 12 is a schematic diagram of an embodiment of the semiconductor device described herein;

[0019] Figure 13 is a schematic diagram of an embodiment of the semiconductor device described herein;

[0020] Figure 14 is a schematic diagram of an example component of one or more devices described herein;

[0021] Figure 15 is a flowchart of an example process for forming a semiconductor device described herein;

[0022] Figure 16 is a flowchart of an example process for forming a semiconductor device described herein.

[0023]

Symbol Description

[0024] 100: Environment

[0025] 102~114: Tools

[0026] 200: Semiconductor device

[0027] 205: Semiconductor substrate

[0028] 210: Convex region

[0029] 215: STI region

[0030] 220: Nanostructured channel

[0031] 225: Source / drain region

[0032] 230: Buffer

[0033] 235: Overlayer

[0034] 240: Gate structure

[0035] 245: Inner spacer

[0036] 250: ILD layer

[0037] 255: Source / drain region

[0038] 300: Exemplary embodiment

[0039] 305: Layer stack

[0040] 310: First layer

[0041] 315: Second layer

[0042] 320: Hard mask layer

[0043] 325: Overlayer

[0044] 330: Oxide layer

[0045] 335: Nitride layer

[0046] 340: Portion

[0047] 345: Fin structure

[0048] 345a: First subset of fin structures

[0049] 345b: Second subset of fin structures

[0050] 400: Exemplary embodiment

[0051] 405: Pad

[0052] 410: Dielectric layer

[0053] 500: Exemplary embodiment

[0054] 505: Coating layer

[0055] 510: Coated sidewall

[0056] 600: Exemplary embodiment

[0057] 605: Pad

[0058] 610: Dielectric layer

[0059] 615: High-k layer

[0060] 620: Hybrid fin structure

[0061] 700: Exemplary embodiment

[0062] 705:Dummy gate structure

[0063] 710: Gate electrode layer

[0064] 715: Hard mask layer

[0065] 720: Spacer layer

[0066] 725: Gate dielectric layer

[0067] 800: Exemplary embodiment

[0068] 805: Source / drain recess

[0069] 810: Cavity

[0070] 815: Insulating layer

[0071] 900: Exemplary embodiment

[0072] 905: Hard mask layer

[0073] 910: Patterned stack

[0074] 915: Bottom layer

[0075] 920: Middle layer

[0076] 925: Top layer

[0077] 930: Pattern

[0078] 935: Active region isolation recess

[0079] 940: Active region isolation structure

[0080] 945: Dielectric pad

[0081] 950: Dielectric layer

[0082] 1000: Exemplary embodiment

[0083] 1005: Opening

[0084] 1010: High dielectric constant pad

[0085] 1100: Demonstration embodiment

[0086] 1105: Hard mask layer

[0087] 1110: Gate isolation structure

[0088] 1115: Active region isolation structure

[0089] 1120: Patterned stack

[0090] 1125: Bottom layer

[0091] 1130: Middle layer

[0092] 1135: Top layer

[0093] 1140: Pattern

[0094] 1145: Recess

[0095] 1150: Protrusion section

[0096] 1155: Internal STI section

[0097] 1160: External STI section

[0098] 1165: Dielectric pad

[0099] 1170: Dielectric layer

[0100] 1200: Demonstration embodiment

[0101] 1300: Demonstration embodiment

[0102] 1400: Device

[0103] 1410: Port

[0104] 1420: Processor

[0105] 1430: Memory

[0106] 1440: Input component

[0107] 1450: Output component

[0108] 1460: Communication component

[0109] 1500: Process

[0110] 1510~1560: Block

[0111] 1600: Process

[0112] 1610~1670: Block Detailed implementation manners

[0113] The following disclosure provides many different embodiments or examples for implementing different features of the described subject matter. Specific examples of components and arrangements are described below to simplify this specification. Of course, these are merely examples and not restrictive. For example, in the following description, forming a first feature above or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may reuse reference numerals and / or reference letters in multiple examples. Such reuse is for the purposes of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0114] Spatial relative terms such as "under", "below", "bottom", "on", "top", etc. may be used herein for purposes of convenience in description to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly.

[0115] A continuous polysilicon on diffusion region edge (CPODE) process can be performed to remove a part of a polysilicon dummy gate structure and replace a part of the polysilicon dummy gate structure with a CPODE structure. The CPODE structure includes an isolation structure formed in a recess after removing a part of the polysilicon dummy gate structure. The CPODE structure can extend into a silicon fin structure under the polysilicon dummy gate structure. The CPODE structure can be formed to provide isolation (such as electrical isolation and / or physical isolation) between semiconductor devices, such as between device regions of semiconductor devices, between active regions of semiconductor devices, and / or between transistors of semiconductor devices, etc.

[0116] In some cases, the CPODE process can cause one or more layout-dependent effects (LDEs) to occur in a semiconductor device. For example, the portion of the polysilicon dummy gate removed due to the CPODE structure may be adjacent to one or more source / drain regions of a transistor in the semiconductor device. The etching process that removes the portion of the polysilicon dummy gate structure may cause critical dimension loading and epitaxial damage to these source / drain regions. As another example, deep loading may occur in the etching process where the amount of silicon fin structure removed is insufficient to form a CPODE structure with sufficient depth to provide electrical isolation between the source / drain. This may lead to an increased likelihood of leakage current between the source / drain (e.g., through the silicon fin structure and / or through the underlying substrate). As yet another example, the CPODE structure may cause gate deformation of this polysilicon gate structure and / or other polysilicon gate structures, which can cause a shift in the threshold voltage (V t ) or a change in the threshold voltage of the transistors in the semiconductor device. The change in the threshold voltage can cause a change in the switching speed of the transistors in the semiconductor device, a change in power consumption, and / or a decrease in device performance.

[0117] Some embodiments described herein provide a CPODE process for tuning one or more hybrid fin structures and / or shallow trench isolation (STI) regions of a semiconductor device to reduce the likelihood of epitaxial damage to the source / drain regions of the semiconductor device. For example, the height of the tunable hybrid fin structure and / or STI region and / or the etching of the hybrid fin structure and / or STI region are tuned to reduce the likelihood of epitaxial damage to the source / drain regions of the semiconductor device.

[0118] As another example, when forming a recess for the CPODE structure, the STI region can be completely removed, which can reduce the likelihood of epitaxial damage to the source / drain regions of the semiconductor device. The STI region can be removed in a mid-end-of-line (MEOL) CPODE process, where the CPODE structure is formed after a replacement gate process (RGP) that replaces the polysilicon dummy gate structure in the semiconductor device with a metal gate structure.

[0119] The CPODE process described herein can reduce the likelihood of etching into source / drain regions located on the opposite side of the CPODE structure, the likelihood of deep loading in the semiconductor device, and / or the likelihood of gate deformation in the semiconductor device, among others. Thus, the CPODE process described herein can reduce the likelihood of epitaxial damage to the source / drain regions, the likelihood of leakage current between the source / drain regions, and / or the likelihood of threshold voltage shift in the transistors of the semiconductor device. The reduction in the likelihood of threshold voltage shift can provide more consistent and / or faster switching speeds for the transistors, more consistent and / or lower power consumption, and / or improved device performance, among others.

[0120] Figure 1Schematic diagram of an example environment in which the systems and / or methods described herein can be implemented. As Figure 1 shown, the example environment 100 may include a plurality of semiconductor processing tools 102 to 112 and a wafer / die transfer tool 114. The plurality of semiconductor processing tools 102 to 112 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, and / or other types of semiconductor processing tools. The tools included in the example environment 100 may be included in a semiconductor cleanroom, a semiconductor foundry, a semiconductor processing facility, and / or a production facility, etc.

[0121] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices that can deposit various materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool that can deposit a photoresist layer onto a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD tool, a high density plasma CVD tool, a sub-atmospheric CVD tool, a low pressure CVD tool, an atomic layer deposition (ALD) tool, a plasma enhanced ALD tool, or other types of CVD tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of PVD tools. In some embodiments, the deposition tool 102 includes an epitaxial growth tool, and the epitaxial growth tool is configured to form a layer or region on a device by epitaxial growth. In some embodiments, the example environment 100 includes a plurality of deposition tools 102.

[0122] The exposure tool 104 is a semiconductor processing tool that can expose a photoresist layer to a radiation source, and the radiation source is, for example, an ultraviolet (UV) light source (e.g., deep ultraviolet light or extreme ultraviolet light (EUV), etc.), an X light source, an electron beam (e-beam) source, etc. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. This pattern may include one or more semiconductor device layer patterns to form one or more semiconductor devices, may include a pattern of one or more structures for forming a semiconductor device, may include a pattern for etching multiple parts of a semiconductor device, etc. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or other similar types of exposure tools.

[0123] The development tool 106 is a semiconductor processing tool that can develop a photoresist layer that has been exposed to a radiation source to form the pattern transferred to the photoresist layer by the exposure tool 104. In some embodiments, the development tool 106 forms a pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the development tool 106 forms a pattern by removing the exposed portion of the photoresist layer. In some embodiments, the development tool forms a pattern by using a chemical developer to dissolve the unexposed or exposed portion of the photoresist layer.

[0124] The etching tool 108 is a semiconductor processing tool that can etch various materials of a substrate, a wafer, or a semiconductor device. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and so on. In some embodiments, the etching tool 108 includes a cavity that can be filled with an etchant, and the substrate is placed in the cavity for a certain period of time to remove one or more portions of a specific amount of the substrate. In some embodiments, the etching tool 108 uses plasma etching or plasma-assisted etching to etch one or more portions of the substrate, and plasma etching or plasma-assisted etching can involve using an ionized gas to etch one or more portions co-directionally or directionally. In some embodiments, the etching device 108 includes a plasma-based asher to remove photoresist materials or other materials.

[0125] The planarization tool 110 is a semiconductor processing tool that can polish or planarize multiple layers of a wafer or a semiconductor device. For example, the planarization tool 110 can include a chemical mechanical planarization (CMP) tool and / or another tool that planarizes a deposited or plated layer or surface. The planarization tool 110 can polish or planarize the surface of the semiconductor device through a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The planarization device 110 can utilize an abrasive and corrosive chemical slurry in conjunction with a polishing pad and a retainer ring (e.g., typically having a diameter larger than that of the semiconductor device). The polishing pad and the semiconductor device can be squeezed together by a powered polishing head and fixed by the retainer ring. The powered polishing head can rotate along different axes of rotation to remove materials and eliminate any irregular topography, thereby making the semiconductor device planar.

[0126] The plating tool 112 is a semiconductor processing tool that can plate one or more metals onto a substrate (such as a wafer or a semiconductor device, etc.) or a portion thereof. For example, the plating tool 112 can include a copper electroplating device, a tin electroplating device, a composite material or alloy (such as tin-silver or tin-lead, etc.) electroplating device, and / or electroplating devices for one or more other conductive materials, metals, or similar types of materials.

[0127] The wafer / die transfer tool 114 includes a mobile robot, a robotic arm, a rail vehicle, an overhead hoist transport (OHT) system, an automated material handling system (AMHS), and / or other configurations for transporting substrates and / or semiconductor devices between semiconductor processing tools 102 to 112, for transporting substrates and / or semiconductor devices between processing chambers of the same processing tool, and / or for transporting substrates and / or semiconductor devices from other locations, such as a wafer rack and / or a storage room, etc. In some embodiments, the exemplary environment 100 includes multiple wafer / die transfer tools 114.

[0128] For example, the wafer / die transporter 114 can be included in a cluster tool or other type of tool that includes multiple processing chambers, and can be configured to transport substrates and / or semiconductor devices among multiple processing chambers, convey substrates and / or semiconductor devices between a processing chamber and a buffer, convey substrates and / or semiconductor devices between a processing chamber and an interface tool, such as an equipment front end module (EFEM), and / or convey substrates and / or semiconductor devices between a processing chamber and a transport vehicle (such as a front opening unified pod (FOUP)), and so on. In some embodiments, the wafer / die transporter 114 can be included in a multi-chamber (or cluster) deposition tool 102, and the multi-chamber deposition tool 102 can include a pre-clean processing chamber (e.g., for cleaning or removing oxides, oxidation, and other contaminants or by-products from a substrate and / or semiconductor device) and multiple deposition processing chambers (e.g., processing chambers for depositing different materials, processing chambers for performing different deposition operations). As described herein, in these embodiments, the wafer / die transporter 114 is configured to transport substrates and / or semiconductor devices between the processing chambers of the deposition tool 102 without breaking or eliminating the vacuum (or at least partial vacuum) between the processing chambers or processing operations of the deposition tool 102.

[0129] As described herein, the semiconductor processing tools 102 to 112 can be used to perform a combination of several operations to form one or more portions of a nanostructure transistor. In some embodiments, the combination of these operations can include forming multiple nanostructure layers along a direction perpendicular to the semiconductor substrate on the semiconductor substrate of the semiconductor device, where the nanostructure layers include multiple sacrificial layers interleaved with multiple channel layers, can include etching the nanostructure layers and the semiconductor substrate to form multiple protrusion regions and multiple layer stacks located on the protrusion regions, where the layer stacks include portions corresponding to the sacrificial layers and portions corresponding to the channel layers, can include forming shallow trench isolation (STI) regions between adjacent layer stacks in the layer stacks and hybrid fin structures located on the STI regions, can include forming dummy gate structures on the nanostructure layers, can include removing multiple portions of the nanostructure layers to form one or more recesses adjacent to one or more sides of the dummy gate structures, and / or can include forming one or more source / drain regions within the one or more recesses, where the top surface of one of the hybrid fin structures is located at a height greater than that of one of the source / drain regions, and so on.

[0130] In some embodiments, the combination of these operations may include forming multiple nanostructure layers on a semiconductor substrate of a semiconductor device in a direction perpendicular to the semiconductor substrate, wherein the nanostructure layers include multiple sacrificial layers alternating with multiple channel layers, may include forming a dummy gate structure on the nanostructure layer, may include removing multiple portions of the nanostructure layer to form one or more recesses adjacent to one or more sides of the dummy gate structure, may include forming one or more source / drain regions in the one or more recesses, may include replacing the dummy gate structure and multiple portions of the sacrificial layer under the dummy gate structure with a metal gate structure after forming the one or more source / drain regions, wherein the metal gate structure surrounds at least four sides of the channel layer, may include removing a portion of the metal gate structure, multiple portions of the channel layer surrounded by the metal gate structure, extending under the multiple portions of the channel layer to multiple convex regions and STI regions on the semiconductor substrate to form active region isolation recesses between the multiple convex regions, and may include forming an active region isolation structure in the active region isolation recess.

[0131] In some embodiments, the combination of these operations includes Figures 3A to 11I One or more operations related to one or more of the above.

[0132] Figure 1 The number and arrangement of devices shown in the figure are provided as one or more examples. In practice, there may be Figure 1 Additional devices, fewer devices, different devices, or differently arranged devices as shown in . In addition, Figure 1 Two or more of the devices shown in may be implemented in a single device, or Figure 1 A single device shown in the example environment 100 may be implemented as a plurality of separate devices. Additionally or alternatively, one or more devices of one set of devices (ie, one or more devices) of the example environment 100 may perform one or more functions described as being performed by another set of devices of the example environment 100.

[0133] Figure 2 2 is a schematic diagram of an example semiconductor device 200 described herein. The semiconductor device 200 includes one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors. The semiconductor device 200 may include a plurality of transistors not shown in FIG. Figure 2 For example, the semiconductor device 200 may include additional layers and / or the semiconductor device 200 may include one or more additional devices, structures, or layers. Figure 2 Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the embodiment including the semiconductor structure shown in FIG.Figure 2 formed in the same layer of an electronic device or integrated circuit (IC) of the exemplary semiconductor device 200 shown in Figures 3A to 12 One or more of which may include Figure 2 schematic cross-sectional views of multiple portions of the semiconductor device 200 shown in , and corresponding to multiple processing stages of the nanostructure transistors forming the semiconductor device 200.

[0134] The semiconductor device 200 includes a semiconductor substrate 205. The semiconductor substrate 205 includes a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor substrate such as gallium arsenide (GaAs), a silicon-on-insulator substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates. The semiconductor substrate 205 may include multiple layers, including conductive or insulating layers formed on the semiconductor substrate. The semiconductor substrate 205 may include a compound semiconductor or an alloy semiconductor. The semiconductor substrate 205 may include various doping configurations to meet one or more design parameters. For example, different doping profiles (e.g., N-well, P-well) may be formed in regions of the semiconductor substrate 205 designed for different types of devices (e.g., P-type metal-oxide-semiconductor (PMOS) nanostructure transistors, N-type metal-oxide-semiconductor (NMOS) nanostructure transistors). Suitable doping methods may include ion implantation and / or diffusion processes of dopants. Also, the semiconductor device 205 may include an epitaxial layer (EPI layer), may be deformable to enhance performance and / or may have other suitable enhancement features. The semiconductor substrate 205 may include a portion on which other semiconductor devices of a semiconductor wafer are formed.

[0135] The convex region 210 is formed on and / or extends to the semiconductor 205. The convex region 210 provides a nanostructure of the semiconductor device 200, such as a nanostructure channel, a nanostructure gate portion surrounding each nanostructure channel, and / or a sacrificial nanostructure, etc., on which structures can be formed. In some embodiments, one or more convex regions 210 are formed on and / or formed from a fin structure (such as a silicon fin structure) formed from the semiconductor substrate 205. The convex region 210 may comprise the same material as the semiconductor substrate 205 and is formed from the semiconductor substrate 205. In some embodiments, the convex region 210 is doped to form different types of nanostructure transistors, such as P-type nanostructure transistors and / or N-type nanostructure transistors. In some embodiments, the convex region 210 comprises a silicon (Si) material or another elemental semiconductor material, such as germanium (Ge). In some embodiments, the convex region 210 comprises an alloy semiconductor material, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or a combination thereof.

[0136] The convex region 210 is fabricated using suitable semiconductor processing techniques, such as photomasks, lithography, and / or etching, etc. For example, a fin structure can be formed by etching away a portion of the semiconductor substrate 205 to form a recess in the semiconductor substrate 205. The recess can then be filled with an isolation material, and the recessed material is recessed or etched back to form a shallow trench isolation (STI) region 215 between the semiconductor substrate 205 and the fin structure, such that the convex region 210 is formed between the source / drain recesses. However, other manufacturing techniques can also be used to fabricate the STI region 215 and the convex region 210.

[0137] The STI region 215 can electrically isolate adjacent fin structures and can provide a layer on which other layers and / or structures of the semiconductor device 200 can be formed. The STI region 215 may comprise a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorinated silicon glass (FSG), a low dielectric constant dielectric material, and / or other suitable insulating materials. The STI region 215 may comprise a multi-layer structure, such as having one or more liner layers.

[0138] The semiconductor device 200 includes a plurality of nanostructured channels 220 that extend between the source / drain regions 225 and are electrically coupled to the source / drain regions 225. The source / drain regions may refer to the source or the drain, respectively or collectively, depending on the context. The nanostructured channels 220 are arranged in a direction substantially perpendicular to the semiconductor substrate 205. In other words, the nanostructured channels 220 are vertically arranged or stacked on the semiconductor substrate 205.

[0139] The nanostructured channels 220 include silicon-based nanostructures (e.g., nanosheets or nanowires, etc.), and the silicon-based nanostructures serve as the semiconductive channels of the nanostructured transistors of the semiconductor device 200. In some embodiments, the nanostructured channels 220 may include silicon germanium (SiGe) or other silicon-based materials. The source / drain regions 225 include silicon (Si) with one or more dopants, such as p-type materials (e.g., boron (B) or germanium (Ge), etc.), n-type materials (e.g., phosphorus (P) or arsenic (As), etc.), and / or other types of dopants. Thus, the semiconductor device 200 may include p-type metal-oxide-semiconductor (PMOS) nanostructured transistors including p-type source / drain regions 225, n-type metal-oxide-semiconductor (NMOS) nanostructured transistors including n-type source / drain regions 225, and / or other types of nanostructured transistors.

[0140] In some embodiments, a buffer layer 230 is included beneath the source / drain regions 225, between the source / drain regions 225 and the odd-shaped structures on the semiconductor substrate 205. The buffer layer 230 may provide isolation between the source / drain regions 225 and the adjacent bump regions 210. The buffer layer 230 may be included to reduce, minimize, and / or avoid electrons from flowing into the bump regions 210 (e.g., rather than into the nanostructured channels 220, thus reducing leakage current) and / or the buffer layer 230 may be included to reduce, minimize, and / or avoid dopants from entering the bump regions 210 from the source / drain regions 225 (and weakening the short-channel effect).

[0141] A capping layer 235 may be included over and / or above the source / drain regions 225. The capping layer 235 may include silicon, silicon germanium, doped silicon, doped silicon germanium, and / or additional materials. The capping layer 235 may be included to reduce dopant diffusion and protect the source / drain regions 225 of the semiconductor device 200 before forming contacts in semiconductor processing operations. In addition, the capping layer 235 may assist in the formation of metal-semiconductor (e.g., silicide) alloys.

[0142] At least one subset of the nanochannels 220 extends through one or more gate structures 240. The gate structures 240 may be formed of one or more metallic materials, one or more high-k materials, and / or one or more other materials. In some embodiments, a dummy gate structure (e.g., a polysilicon gate structure or other type of gate structure) is formed in the position of the gate structure 240 (e.g., before the gate structure is formed), such that one or more other layers and / or structures of the semiconductor device 200 can be formed before the gate structure 240 is formed. This can reduce and / or avoid damage to the gate structure 240 caused by the formation of one or more other layers and / or structures. Then, a replacement gate process (RGP) is performed to remove the dummy gate structure and replace it with the gate structure 240 (e.g., a replacement gate structure).

[0143] More specifically Figure 2 As shown, multiple portions of the gate structure 240 are formed in a vertically staggered arrangement in multiple pairs of nanostructured channels 220. In other words, as Figure 2 shown, the semiconductor structure 200 includes one or more vertical stacks in which the nanostructured channels 220 and the gate structure 240 are partially interleaved. In this way, the gate structure 240 surrounds all sides of the corresponding nanostructured channels 220, which can improve the control of the nanostructured gates 220, increase the drive current of the nanostructured transistors of the semiconductor device 200, and reduce the short-channel effect (SCE) of the nanostructured transistors of the semiconductor device 200.

[0144] Some source / drain regions 225 and gate structures 240 may be shared by one or more nanoscale transistors of the semiconductor device 200. In these embodiments, as Figure 2 illustrated in the example, one or more source / drain regions 225 and gate regions 240 may be connected or coupled to multiple nanostructured channels 220. This enables multiple nanostructured channels 220 to be controlled by a single gate structure 240 and a pair of source / drain regions 225.

[0145] An internal spacer (InSP) 245 may be included between the source / drain region 225 and the adjacent gate structure 240. Specifically, the internal spacer 245 may be included between the source / drain region 225 and the gate structure 240 surrounding the multiple nanostructured channels 220. The internal spacer 245 is included at the ends of the portions of the gate structure 240 surrounding the multiple nanostructured channels 220. The internal spacer 245 is included in a cavity formed between the end portions of adjacent nanostructured channels 220. The internal spacer 245 is included to reduce parasitic capacitance and protect the source / drain region 225 from being etched in a nanosheet release process for removing sacrificial nanosheets between the nanostructured channels 220. The internal spacer 245 includes silicon nitride (Si x N y) silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or other dielectric materials.

[0146] In some embodiments, the semiconductor device 200 includes a hybrid fin structure (not shown). The hybrid fin structure may also be referred to as a dummy fin, an H-fin, a non-active fin, etc. The hybrid fin structure may be included between adjacent source / drain regions 225, between portions of the gate structure 240, and / or between stacks of adjacent nanostructure channels 220, etc. The hybrid fin structure extends in a direction approximately perpendicular to the gate structure 240.

[0147] The hybrid fin structure is configured to provide electrical isolation between two or more structures and / or components included in the semiconductor device 200. In some embodiments, the hybrid fin structure is configured to provide electrical isolation between two or more source / drain regions 225. In some embodiments, the hybrid fin structure is configured to provide electrical isolation between two or more gate structures or portions of the gate structure. In some embodiments, the hybrid fin structure is configured to provide electrical isolation between the source / drain region 225 and the gate structure 240.

[0148] The hybrid fin structure may include a variety of dielectric materials. The hybrid fin structure may include one or more low dielectric constant dielectric materials (e.g., silicon oxide (SiO x ) and / or silicon nitride (Si x N y ) etc.) and a combination of one or more high dielectric constant dielectric materials (e.g., hafnium oxide (HfO x ) and / or other high dielectric constant dielectric materials).

[0149] The semiconductor device 200 may also include an interlayer dielectric (ILD) layer 250 on the STI region. The ILD layer 250 may be referred to as the ILD0 layer. The ILD layer 250 surrounds the gate structure 240 to provide electrical isolation and / or insulation between the gate structure 240 and / or the source / drain region 225, etc. Conductive structures, such as contacts and / or interconnects, may be formed through the ILD layer 250 to the source / drain region 225 and the gate structure 240 to provide control of the source / drain region 225 and the gate structure 240.

[0150] As indicated above, Figure 2 is provided as an example. Other examples may be different from Figure 2 the related content.

[0151] Figure 3A and Figure 3BFIG. 0 is a schematic diagram of an exemplary embodiment 300 of a fin structure formation process described herein. Exemplary embodiment 300 includes an example of forming a fin structure of a semiconductor device 200 or a portion thereof. Semiconductor device 200 may include Figure 3A and Figure 3B one or more additional devices, structures, and / or layers not shown in FIGS. Figure 3A and Figure 3B Additional layers and / or dies may be formed above and / or below a portion of semiconductor device 200 shown in FIGS.

[0152] Figure 3A FIG. 12 shows a perspective view of semiconductor device 200 and a cross-sectional view along line A-A in the perspective view. As shown in Figure 3A FIG. 13, semiconductor device 200 is processed in relation to semiconductor substrate 205. A layer stack 305 is formed on semiconductor substrate 205. Layer stack 305 may be referred to as a superlattice. In some embodiments, one or more operations are performed in relation to semiconductor substrate 205 prior to forming layer stack 305. For example, an anti-punchthrough (APT) implantation operation may be performed. The APT implantation operation may be performed in one or more regions of semiconductor substrate 205 on which nanostructure channels 220 are formed. For example, the APT implantation operation is performed to reduce and / or avoid punchthrough or unwanted diffusion into semiconductor substrate 205.

[0153] Layer stack 305 includes a plurality of interleaved layers arranged in a direction approximately perpendicular to semiconductor substrate 205. For example, layer stack 305 includes a plurality of first layers 310 and a plurality of second layers 315 vertically interleaved above semiconductor substrate 205. Figure 3A The number of first layers 310 and the number of second layers 315 shown in FIG. 18 are examples, and other numbers of first layers 310 and second layers 315 are still within the scope of the present disclosure. In some embodiments, first layer 310 and second layer 315 are formed with different thicknesses. For example, second layer 315 may be formed with a thickness greater than that of first layer 310. In some embodiments, first layer 310 (or a subset thereof) is formed with a thickness in the range of approximately 4 nanometers to approximately 7 nanometers. In some embodiments, second layer 315 (or a subset thereof) is formed with a thickness in the range of approximately 8 nanometers to approximately 12 nanometers. However, other values for the thickness of first layer 310 and the thickness of second layer 315 are also within the scope of the present disclosure.

[0154] The first layer 310 comprises a first material composition, while the second layer comprises a second material composition. In some embodiments, the first material composition and the second material composition are the same material composition. In some embodiments, the first material composition and the second material composition are different material compositions. For example, the first layer 310 may comprise silicon germanium (SiGe) while the second layer 315 may comprise silicon (Si). In some embodiments, the first material composition and the second material composition have different oxidation rates and / or etching selectivities.

[0155] As described herein, the second layer 315 may be processed to form the nanostructure channel 220 of the nanostructure transistor that is to be formed next in the semiconductor device 200. The first layer 310 is a sacrificial nanostructure, and the sacrificial nanostructure will ultimately be removed and used to define the vertical distance between adjacent nanostructure channels 220 for the gate structure 240 of the semiconductor device 200 that is to be formed next. Accordingly, the first layer 310 is referred to as the sacrificial layer, and the second layer 315 is referred to as the channel layer.

[0156] The deposition tool 102 deposits and / or grows the interleaved layers of the layer stack 305 to include nanostructures (such as nanosheets) on the semiconductor substrate 205. For example, the deposition tool 102 grows the interleaved layers by epitaxial growth. However, other processes may also be used to form the interleaved layers of the layer stack 305. The epitaxial growth of the interleaved layers can be carried out by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer, such as the second layer 315, comprises the same material as the semiconductor substrate 205. In some embodiments, the first layer 310 and / or the second layer 315 comprise materials different from the semiconductor substrate 205. As described above, in some embodiments, the first layer 310 comprises an epitaxially grown silicon germanium (SiGe) layer and the second layer 315 comprises an epitaxially grown silicon (Si) layer. Alternatively, the first layer 310 and / or the second layer 315 may comprise other materials, such as germanium (Ge), compound semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb), alloy semiconductors such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP), and / or combinations of the above. The materials of the first layer 310 and the materials of the second layer 315 may be selected based on their different oxidation properties, different etching selectivity properties, and / or other different properties.

[0157] As Figure 3AAs further shown, deposition tool 102 may form one or more additional layers on layer stack 305. For example, a hard mask (HM) layer 320 may be formed on layer stack 305 (e.g., on the second layer 315 of the topmost layer of layer stack 305). As another example, a capping layer 325 may be formed on hard mask layer 320. As yet another example, another hard mask layer including an oxide layer 330 and a nitride layer 335 may be formed on capping layer 325. One or more hard mask layers 320, 330, and 335 may be used to form one or more structures of semiconductor device 200. Oxide layer 330 may serve as an adhesion layer between layer stack 305 and nitride layer 335 and may also serve as an etch stop layer for etching nitride layer 335. One or more hard mask layers 320, 330, and 335 may include silicon germanium (SiGe), silicon nitride (Si x N y ), silicon oxide (SiO x ) or other materials. Capping layer 325 may include silicon (Si) and / or other materials. In some embodiments, capping layer 325 is formed of the same material as semiconductor substrate 205. In some embodiments, one or more additional layers are formed by thermal growth, by CVD, PVD, ALD, and / or other deposition techniques.

[0158] Figure 3B A perspective view and a cross-sectional view along line A-A of semiconductor device 200 are shown. As Figure 3B shown, layer stack 305 and semiconductor substrate 205 are etched to remove portions of layer stack 305 and portions of semiconductor substrate 205. The portion 340 of layer stack 305 and the protrusion region 210 (also referred to as a silicon protrusion or protrusion portion) remaining after the etching operation are referred to as fin structures 345 on semiconductor substrate 205 of semiconductor device 200. Fin structures 345 include the portion 340 of layer stack 305 formed on and / or within protrusion region 210 on semiconductor substrate 205. Fin structures 345 may be formed by any suitable semiconductor processing techniques. For example, deposition tool 102, exposure tool 104, development tool 106, and / or etch tool 108 may utilize one or more lithography processes to form fin structures 345. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes such that a pattern to be formed and having, for example, a pitch, is smaller than that obtained from a single direct lithography process. For example, a sacrificial layer may be formed on a substrate and patterned using lithography. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may be used to pattern the fin structures.

[0159] In some embodiments, a deposition tool 102 forms a photoresist layer on a hard mask layer including an oxide layer 330 and a nitride layer 335. An exposure tool 104 exposes the photoresist layer to a radiation source (e.g., deep ultraviolet radiation, extreme ultraviolet (EUV) radiation), performs a post-exposure bake process (e.g., to remove residual solvent from the photoresist layer), and a development tool 106 develops the photoresist layer to form a mask element (or pattern) in the photoresist layer. In some embodiments, patterning the photoresist layer to form a mask element is performed by an electron beam (e-beam) lithography process, and the mask element can then be used to protect portions of the semiconductor substrate 205 and portions of the layer stack 305 from being etched to form fin structures 345. Unprotected portions of the substrate and unprotected portions of the layer stack 305 are etched (e.g., by an etch tool 108) to form grooves in the semiconductor substrate 205. The etch tool can use dry etch techniques (e.g., reactive ion etching), wet etch techniques, and / or a combination of the above to etch unprotected portions of the substrate and unprotected portions of the layer stack 305.

[0160] In some embodiments, another fin formation technique is used to form the fin structures 345. For example, a fin region can be defined (e.g., using a mask or an isolation region) and a portion 340 can be epitaxially grown in the formation of the fin structures 345. In some embodiments, forming the fin structures 345 includes a trimming process to reduce the width of the fin structures 345. The trimming process can include a wet etch process and / or a dry etch process, etc.

[0161] As Figure 3B As further shown, the fin structures 345 can be formed according to different types of nanostructure transistors of the semiconductor device 200. Specifically, a first subset 345a of the fin structures can be formed for P-type nanostructure transistors (e.g., P-type metal oxide semiconductor (PMOS) nanostructure transistors), and a second subset 345b of the fin structures can be formed for N-type nanostructure transistors (e.g., N-type metal oxide semiconductor (NMOS) nanostructure transistors). The second subset 345b of the fin structures can be doped with an N-type dopant (e.g., phosphorus (P) and / or arsenic (As), etc.). Additionally or alternatively, P-type source / drain regions 225 can then be formed for the P-type nanostructure transistors including the first subset 345a of the fin structures, and N-type source / drain regions 225 can then be formed for the N-type nanostructure transistors including the second subset 345b of the fin structures.

[0162] A first subset 345a of fin structures (e.g., PMOS fin structures) and a second subset 345b of fin structures (e.g., NMOS fin structures) may be formed to include like and / or different properties. For example, the first subset 345a of fin structures may be formed with a first height while the second subset 345b of fin structures may be formed with a second height, where the first height and the second height are different heights. As another example, the first subset 345a of fin structures may be formed with a first width while the second subset 345b of fin structures may be formed with a second width, where the first width and the second width are different widths. In Figure 3B the example shown, the second width of the second subset 345b of fin structures (e.g., NMOS fin structures) is greater than the first width of the first subset 345a of fin structures (e.g., PMOS fin structures). However, other examples are also within the scope of this disclosure.

[0163] As described above, Figure 3A and Figure 3B are provided as examples, and other examples may differ from those discussed in Figure 3A and Figure 3B The exemplary embodiment 300 may include additional operations, fewer operations, different operations, and / or a different order of operations compared to those described in connection with Figure 3A and Figure 3B .

[0164] Figure 4A and Figure 4B are schematic diagrams of an exemplary embodiment 400 of the STI formation process described herein. The exemplary embodiment 400 includes an example of forming STI regions 215 between fin structures 345 of a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include one or more additional devices, structures, and / or layers not shown in Figure 4A and / or Figure 4B . Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer as the electronic device including the semiconductor device 200. In some embodiments, the operations described in connection with the exemplary embodiment 400 are performed after the operations in connection with Figure 3A and Figure 3B .

[0165] Figure 4A shows a perspective view and a cross-sectional view along line A-A of the semiconductor device 200. As Figure 4AAs shown, the liner 405 and the dielectric layer 410 are formed on the semiconductor substrate 205 and are interleaved with the fin structures 345. The deposition tool 102 can deposit the liner 405 and the dielectric layer 410 into the grooves between the semiconductor substrate 205 and the fin structures 345. The deposition tool 102 can form the dielectric layer 410 such that the height of the top surface of the dielectric layer 410 is substantially equal to the height of the top surface of the nitride layer 335.

[0166] Alternatively, the deposition tool 102 can form the dielectric layer 410 such that the height of the top surface of the dielectric layer 410 is higher than the height of the top surface of the nitride layer 335, as Figure 4A shown. In this way, the grooves between the fin structures 345 are overfilled with the dielectric layer 410 to ensure that the grooves are completely filled with the dielectric layer 410. Then, the planarization tool 110 can perform a planarization or polishing operation (e.g., a CMP operation) to planarize the dielectric layer 410. In this operation, the nitride layer 335 of the hard mask layer can serve as a CMP stop layer. In other words, the planarization tool 110 planarizes the dielectric layer 410 until it reaches the nitride layer 335 of the hard mask layer. Accordingly, the height of the top surface of the dielectric layer 410 is substantially equal to the height of the top surface of the nitride layer 335 after the operation.

[0167] The deposition tool 102 can use a conformal deposition technique to deposit the liner 405. The deposition tool 102 can use a CVD technique (e.g., a flowable CVD technique or other CVD techniques), a PVD technique, an ALD technique, and / or other deposition techniques to deposit the dielectric layer. In some embodiments, after depositing the liner 405, the semiconductor device 200 is annealed to improve the quality of the liner 405.

[0168] The liner 405 and the dielectric layer 410 each include a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorinated silicate glass (FSG), a low dielectric constant dielectric material, and / or other suitable insulating materials. In some embodiments, the dielectric layer 410 includes a multi-layer structure, such as having one or more liner layers.

[0169] Figure 4B A perspective view and a cross-sectional view along line A-A of the semiconductor device 200 are shown. As Figure 4BAs shown, a re-etch operation is performed to remove portions of the liner 405 and portions of the dielectric layer 410 to form the STI region 215. The etch tool 108 can etch the liner 405 and the dielectric layer 410 in the re-etch operation to form the STI region 215. The etch tool 108 etches the liner 405 and the dielectric layer 410 according to a hard mask layer (such as a hard mask layer including an oxide layer 330 and a nitride layer 335), such that the height of the STI region 215 is lower than or slightly equal to the height of the bottom of the portion 340 of the layer stack 305. Accordingly, the portion 340 of the layer stack 305 extends over the STI region 215. In some embodiments, the liner 405 and the dielectric layer 410 are etched such that the height of the STI region 215 is less than the top surface height of the protrusion region 210.

[0170] In some embodiments, the etch tool 108 uses a plasma-based dry etching technique to etch the liner 405 and the dielectric layer 410. Ammonia (NH-3), hydrofluoric acid (HF), and / or other etchants can be used. The plasma-based dry etching technique may cause reactions between the etchant and the liner 405 and the dielectric layer 410, including:

[0171] SiO2 + 4HF → SiF4 + 2H2O

[0172] wherein the silicon dioxide (SiO2) of the liner 405 and the dielectric layer 410 reacts with hydrofluoric acid to form by-products, including silicon tetrafluoride (SiF4) and water (H2O). The silicon tetrafluoride is further decomposed by hydrofluoric acid and ammonia to form the by-product ammonium fluorosilicate ((NH4)2SiF6):

[0173] SiF4 + 2HF + 2NH3 → (NH4)2SiF6

[0174] The by-product ammonium fluorosilicate is removed from a processing chamber of the etch tool 108. After removing the ammonium fluorosilicate, a post-process temperature in the range of about 200 degrees Celsius to about 250 degrees Celsius is used to sublime the ammonium fluorosilicate into a composition of silicon tetrafluoride, ammonia, and hydrofluoric acid.

[0175] In some embodiments, the etch tool 108 etches the liner 405 and the dielectric layer 410 such that the height of the STI region 215 between a first subset 345a of the fin structures (e.g., of a PMOS nanostructure transistor) is relatively greater than the height of the STI region 215 between a second subset 345b of the fin structures (e.g., of an NMOS nanostructure transistor). This is mainly because the width of the fin structure 345b is relatively greater than the width of the fin structure 345a. Additionally, this causes the top surface of the STI region 215 between the fin structures 345a and 345b to be inclined or (e.g., inclined downward from the fin structure 345a to the fin structure 345b, as Figure 4AAs shown in the example). The etchant used to etch the liner 405 and the dielectric layer 410 is first physically adsorbed (e.g., physically bonded to the liner 405 and the dielectric layer 410) due to the Van der Waals force between the etchant and the surfaces of the liner 405 and the dielectric layer 410. The etchant is captured by the force of the dipole moment. Then, the etchant attaches to the dangling bonds of the liner 405 and the dielectric layer 410 and begins chemisorption. Here, the chemisorption of the etchant on the surfaces of the liner 405 and the dielectric layer 410 causes the etching of the liner 405 and the dielectric layer 410. The larger width of the groove between the second subset 345b of the fin structures provides a larger surface area for chemisorption to occur, resulting in a larger etching rate between the second subset 345b of the fin structures. The larger etching rate causes the height of the STI region 215 between the second subset 345b of the fin structures to be relatively lower than the height of the STI region 215 between the first subset 345a of the fin structures.

[0176] As described above, Figure 4A and Figure 4B are provided as examples, and other examples may be different from Figure 4A and Figure 4B discussed in. The exemplary embodiment 400 may include additional operations, fewer operations, different operations, and / or a different order of operations compared to those described in conjunction with Figure 3A and Figure 3B .

[0177] Figures 5A to 5C is a schematic diagram of an exemplary embodiment 500 of the coating sidewall process described herein. The exemplary embodiment 500 includes an example of forming a coating sidewall on the side of a portion 340 of a layer stack 305 of a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include one or more additional devices, structures, and / or layers not shown in Figures 5A to 5C . Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer as the electronic device including the semiconductor device 200. In some embodiments, the operations described in conjunction with the exemplary embodiment 500 are performed after the operations in conjunction with Figures 3A to 4B .

[0178] Figure 5A shows a perspective view of the semiconductor device 200 and a cross-sectional view along line A-A. As Figure 5AAs shown, the coating layer 505 is formed on the fin structure 345 (e.g., on the top surface and sidewalls of the fin structure 345) and on the STI region 215 between the fin structures 345. The coating layer 505 comprises silicon germanium (SiGe) or other materials. The coating layer 505 can be formed of the same material as the first layer 310 such that the coated sidewalls (formed from the coating layer 505) and the first layer 310 are removed in the same etching process (nanostructure release process), and a replacement gate (e.g., gate structure 240) is formed in the area originally occupied by the coated sidewalls and the first layer 310. This enables the replacement gate to completely surround the nanostructure channel of the nanostructure transistor of the semiconductor device 200.

[0179] The deposition tool 102 can deposit the coating layer 505. In some embodiments, the deposition tool 102 deposits a seed layer (e.g., a silicon seed layer or other types of seed layers) on the fin structure 345 (e.g., on the top surface and sidewalls of the fin structure 345) and on the STI region 215 between the fin structures 345. Then, the deposition tool 102 deposits silicon germanium on the seed layer to form the coating layer 505. The seed layer promotes the growth and adhesion of the coating layer 505.

[0180] The deposition of the seed layer can include providing a silicon precursor to the processing chamber of the deposition tool 102 using a carrier gas, such as nitrogen (N2) or hydrogen (H2), etc. In some embodiments, a pre-cleaning operation is performed prior to depositing the seed layer to reduce the formation of germanium oxide (GeO x )). The silicon precursor can include disilane (Si2H6) or other silicon precursors. Using disilane can enable the seed layer to have a thickness in the range of about 0.5 nanometers to about 1.5 nanometers to provide a sufficient thickness of the coated sidewalls while allowing the coating layer 505 to have a controllable and consistent thickness. However, other values or ranges of the thickness of the seed layer are also within the scope of this disclosure.

[0181] The deposition of the seed layer can be performed at a temperature in the range of about 450 degrees Celsius to about 500 degrees Celsius (or another temperature range), at a pressure in the range of about 30 Torr to about 100 Torr (or another pressure range), and / or for a duration in the range of about 100 seconds to about 300 seconds (or another duration range), etc.

[0182] The silicon germanium for depositing the coating layer 505 may include forming the coating layer 505 to include an amorphous phase texture to facilitate conformal deposition of the coating layer 505. The silicon germanium may include a germanium component in the range of about 15% germanium to about 25% germanium. However, other values of the germanium component are also within the scope of this disclosure. Depositing the coating layer 505 may include providing a silicon precursor (such as disilane (Si2H6) or silane (SiH4), etc.) and a germanium precursor (such as germane (GeH4) or other germanium precursors) to the processing chamber of the deposition tool 102 using a carrier gas, such as nitrogen (N2) or hydrogen (H2). The deposition of the coating layer 505 may be carried out at a temperature in the range of about 500 degrees Celsius to about 550 degrees Celsius (or a temperature in another range) and / or at a pressure in the range of about 5 Torr to about 20 Torr (or a pressure in another range).

[0183] Figure 5B A perspective view and a cross-sectional view along line A-A of the semiconductor device 200 are shown. As Figure 5B shown, a re-etch operation is performed to etch the coating layer 505 to form the coating sidewalls 510. The etching tool 108 may use plasma-based dry etching techniques or other etching techniques to etch the coating layer 505. The etching tool 108 may perform a re-etch operation to remove a portion of the coating layer 505 from the top of the fin structure 345 and the STI region 215. Removing the coating layer 505 from the top of the STI region 215 between the fin structures 345 ensures that the coating sidewalls 510 do not include a pedestal on the STI region 215 between the fin structures 345. This ensures that the coating sidewalls 510 do not include a pedestal under the hybrid fin structure that will be formed on the STI region 215 between the fin structures 345.

[0184] In some embodiments, the etching tool 108 uses a fluorine-based etchant to etch the coating layer 505. The fluorine-based etchant may include sulfur hexafluoride (SF6), fluoromethane (CH3F), and / or other fluorine-based etchants. Other reactants and / or carriers, such as methane (CH4), hydrogen (H2), argon (Ar), and / or helium (He), may be used in the re-etch operation. In some embodiments, the re-etch operation is performed using a plasma bias in the range of about 500 volts to about 2000 volts. However, other values of the plasma bias are also within the scope of this disclosure. In some embodiments, removing a portion of the coating layer 505 from the top of the STI region 215 includes performing a highly directional (e.g., anisotropic) etching to selectively remove (e.g., selectively etch) the coating layer 505 on the top of the STI region 215 between the fin structures 345.

[0185] In some embodiments, the coated sidewall 510 includes an asymmetric property (e.g., different lengths, depths, and / or angles). The asymmetric property can provide increased depth to the gate structures 240 of different types of nanostructure transistors (e.g., P-type nanostructure transistors, N-type nanostructure transistors) and reduce and / or minimize the footprint of the coated sidewall 510 on the STI region 215 under the hybrid fin structure of the nanostructure transistors of the semiconductor device 200 (and thus reduce and / or minimize the footprint of the gate structure 240 formed in the region occupied by the coated sidewall 510 after removing the coated sidewall 510). The reduced and / or minimized footprint further reduces the likelihood of electrical short circuits or leakage currents.

[0186] Figure 5C A perspective view of a semiconductor device and a cross-sectional view along line A-A are shown. As Figure 5C shown, the hard mask layer (including the oxide layer 330 and the nitride layer 335) and the capping layer 325 are removed to expose the hard mask layer 320. In some embodiments, the capping layer 325, the oxide layer 330, and the nitride layer 335 are removed using an etching operation (e.g., performed by the etching tool 108), a planarization operation (e.g., performed by the planarization tool 110), and / or other semiconductor processing techniques.

[0187] As described above, Figures 5A to 5C is provided as an example, and other examples may be different from Figures 5A to 5C those discussed in. The exemplary embodiment 500 may include additional operations, fewer operations, different operations, and / or a different order of operations compared to Figures 5A to 5C that described in connection with.

[0188] Figures 6A to 6C FIG. is a schematic diagram of an exemplary embodiment 600 of the hybrid fin structure process described herein. The exemplary embodiment 600 includes an example of forming a hybrid fin structure between the fin structures 345 of the semiconductor device 200 or a portion thereof. The semiconductor device 200 may include one or more additional devices, structures, and / or layers not shown in Figures 6A to 6C FIG.. Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer as the electronic device including the semiconductor device 200. In some embodiments, the operations described in connection with the exemplary embodiment 600 are performed after the operations in connection with Figures 3A to 5C FIG..

[0189] Figure 6A A perspective view of the semiconductor device 200 and a cross-sectional view along line A-A are shown. As Figure 6AAs shown, a liner 605 and a dielectric layer 610 are formed on the STI region 215 interleaved with the fin structures 345 and on the fin structures 345. The deposition tool 102 can deposit the liner 605 and the dielectric layer 610. The deposition tool 102 can use conformal deposition techniques to deposit the liner 605. The deposition tool 102 can use CVD techniques (such as flowable CVD (FCVD) techniques or other CVD techniques), PVD techniques, ALD techniques, or other deposition techniques to deposit the dielectric layer 610. In some embodiments, after depositing the dielectric layer 610, for example, the semiconductor device 200 is annealed to improve the quality of the dielectric layer 610.

[0190] The deposition tool 102 can form the dielectric layer 610 such that the top surface height of the dielectric layer 610 is approximately equal to the top surface height of the hard mask layer 320. Alternatively, the deposition tool 102 can form the dielectric layer 610 such that the top surface height of the dielectric layer 610 is relatively greater than the top surface height of the hard mask layer 320, as Figure 6A shown. In this way, the grooves between the fin structures 345 are overfilled with the dielectric layer 610 to ensure that the grooves are completely filled with the dielectric layer 610. Then, the planarization tool 110 can perform a planarization or polishing operation (such as a CMP operation) to planarize the dielectric layer 610.

[0191] The liner 605 and the dielectric layer 610 can each comprise a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorinated silicon glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. In some embodiments, the dielectric material 610 can comprise a multi-layer structure, such as having one or more liner layers.

[0192] Figure 6B A perspective view and a cross-sectional view along line A-A of the semiconductor device 200 are shown. As Figure 6B shown, a re-etch operation is performed to remove a portion of the dielectric layer 610. The etch tool 108 can etch the dielectric layer 610 in the re-etch operation to reduce the height of the top surface of the dielectric layer 610. Specifically, the etch tool 108 etches the dielectric layer 610 such that the height of the portion of the dielectric layer 610 between the fin structures 345 is less than the top surface height of the hard mask layer 320. In some embodiments, the etch tool 108 etches the dielectric layer 610 such that the height of the portion of the dielectric layer 610 between the fin structures 345 is approximately equal to the top surface height of the uppermost second layer 315 of the portion 340.

[0193] Figure 6C A perspective view and a cross-sectional view along line A-A of the semiconductor device 200 are shown. As Figure 6CAs shown, a high-k dielectric layer 615 is deposited on a portion of the dielectric layer 610 between the fin structures 345. The deposition tool 102 can deposit high-k dielectric materials, such as hafnium oxide (HfOx) and / or other high-k dielectric materials, using CVD techniques, PVD techniques, ALD techniques, and / or other deposition techniques. The portion of the dielectric layer 610 between the fin structures 345 and the high-k dielectric layer 615 between the fin structures 345 are referred to as a hybrid fin structure 620 (or a dummy fin structure). In some embodiments, a planarization tool 110 can perform a planarization operation to planarize the high-k dielectric layer 615 such that the top surface height of the high-k dielectric layer 615 is substantially equal to the top surface height of the hard mask layer 320.

[0194] Next, as Figure 6C shown, the hard mask layer 320 is removed. Removing the hard mask layer 320 can include using etching techniques (e.g., plasma etching techniques, wet chemical etching techniques, and / or other types of etching techniques) or other removal techniques.

[0195] As described above, Figures 6A to 6C is provided as an example, and other examples may be different from Figures 6A to 6C those discussed. The exemplary embodiment 600 can include additional operations, fewer operations, different operations, and / or a different order of operations compared to those described in connection with Figures 6A to 6C this.

[0196] Figure 7A and Figure 7B are schematic diagrams of an exemplary embodiment 700 of a dummy gate formation process described herein. The exemplary embodiment 700 includes an example of forming a dummy gate structure for the semiconductor device 200 or a portion thereof. The semiconductor device 200 can include one or more additional devices, structures, and / or layers not shown in Figure 7A and Figure 7B this. Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices can be formed in the same layer as the electronic device including the semiconductor device 200. In some embodiments, the operations described in connection with the exemplary embodiment 700 are performed after the operations in connection with Figures 3A to 6C this.

[0197] Figure 7A shows a perspective view of a semiconductor device. As Figure 7AAs shown, a dummy gate structure 705 (also referred to as a dummy gate stack or a temporary gate structure) is formed on the fin structure 345 and on the hybrid fin structure 620. The dummy gate structure 705 is to be replaced by a replacement gate structure or a replacement gate stack (such as the gate structure 240) in a subsequent processing stage of the semiconductor device 200. The portion of the fin structure 345 under the dummy gate structure 705 may be referred to as the channel region. The dummy gate structure 705 may also define the source / drain (S / D) regions of the fin structure 345, such as the regions adjacent to and on opposite sides of the channel region of the fin structure 345.

[0198] The dummy gate structure 705 may include a gate electrode layer 710, a hard mask layer 715 on the gate electrode layer 710, and a spacer layer 720 on the opposite side of the gate electrode layer 710 and on the opposite side of the hard mask layer 715. The dummy gate structure 705 may be formed on a gate dielectric layer 725 between the top second layer 315 and the dummy gate structure 705 and between the hybrid fin structure 620 and the dummy gate structure 705. The gate electrode layer 710 includes polysilicon (PO) or other materials. The hard mask layer includes one or more layers, such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO2) or other materials) and a nitride layer formed on the oxide layer (e.g., a pad nitride layer that may include silicon nitride such as Si3N4, or other materials). The spacer layer 720 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 725 may include silicon oxide (e.g., SiO x , such as SiO2), silicon nitride (e.g., Si x N y , such as Si3N4), high-k materials, and / or other suitable materials.

[0199] The dummy gate structure 705 may use a variety of semiconductor process technologies such as deposition (e.g., by a deposition tool 102), patterning (e.g., by an exposure tool 104 and a development tool 106), and / or etching (e.g., by an etching tool 108), etc. Examples include CVD, PVD, ALD, thermal oxidation, electron beam evaporation, photolithography, electron beam lithography, photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (spin drying and / or hard baking), dry etching (e.g., reactive ion etching), and / or wet etching, etc.

[0200] In some embodiments, the gate dielectric layer 725 is conformally deposited on the semiconductor device 200 and selectively removed from portions of the semiconductor device 200, such as the source / drain regions. The gate electrode layer 710 is then deposited on the remaining portion of the gate dielectric layer 725. The hard mask layer 715 is then deposited on the gate electrode layer 710. The spacer layer 720 can be conformally deposited in a manner similar to the gate dielectric layer 725 and subjected to a re-etch to leave the spacer layer 720 on the sidewalls of the dummy gate structure 705. In some embodiments, the spacer layer 720 includes multiple spacer layers. For example, the spacer layer 720 can include a sealing spacer layer formed on the sidewalls of the dummy gate structure 705 and a bulk spacer layer formed on the sealing spacer layer. The sealing spacer layer and the bulk spacer layer can be formed of similar materials or different materials. In some embodiments, the bulk spacer layer is formed without being subjected to the plasma surface treatment used for the sealing spacer layer. In some embodiments, the bulk spacer layer is formed with a thickness relatively greater than that of the sealing spacer layer. In some embodiments, the gate dielectric layer 725 is omitted from the dummy gate structure formation process and formed in the replacement gate process.

[0201] Figure 7A Also shown are reference cross-sections used in the subsequent figures herein. Cross-section A-A is in the x-z plane (referred to as the y-section) that spans the fin structures 345 and the hybrid fin structures 620 in the source / drain regions of the semiconductor device 200. Cross-section B-B is in the y-z plane (referred to as the x-section) perpendicular to cross-section A-A and spans the dummy gate structure 705 in the source / drain regions of the semiconductor device 200. Cross-section C-C is in the x-z plane parallel to cross-section A-A and perpendicular to cross-section B-B and along the dummy gate structure 705. These reference cross-sections are used in the subsequent figures for clarity. For ease of illustration, in some figures, the reference numerals of the components or features depicted therein are omitted so as not to obscure other components or features.

[0202] Figure 7B Including cross-sectional views along Figure 7A cross-sectional planes A-A, B-B, and C-C as shown. As Figure 7B shown in cross-sectional planes B-B and C-C as Figure 7B shown, the dummy gate structure 705 is formed on the fin structure 345. As

[0203] As described above, Figure 7A and Figure 7B are provided as examples, and other examples can be different from those Figure 7A and Figure 7B discussed inFigure 7A and Figure 7B additional operations, fewer operations, different operations, and / or different sequences of operations as described therein.

[0204] Figures 8A to 8E is a schematic diagram of an exemplary embodiment 800 of the source / drain region formation process described herein. Exemplary embodiment 800 includes an example of a semiconductor device 200 forming source / drain recesses and internal spacers 245. Figures 8A to 8E from Figure 7A depicted from a plurality of viewpoints depicted in, including Figure 7A the viewpoint of cross-sectional plane A-A in, Figure 7A the viewpoint of cross-sectional plane B-B in, and Figure 7A the viewpoint of cross-sectional plane C-C in. In some embodiments, the operations described in conjunction with exemplary embodiment 800 are performed after the operations in conjunction with Figures 3A to 7B .

[0205] As Figure 8A shown in cross-sectional plane A-A and cross-sectional plane B-B in, source / drain recesses 805 are formed on portions 340 of fin structures 345 during an etching operation. Source / drain recesses 805 are formed to provide space for source / drain regions 225 to be formed on the opposite side of dummy gate structures 705. The etching operation can be performed by an etching tool 108 and can be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes plasma etching techniques, wet chemical etching techniques, and / or other types of etching techniques.

[0206] Source / drain recesses 805 also extend into portions of the convex regions 210 of fin structures 345. This results in the formation of multiple convex regions 210 in each fin structure 345, and the sidewalls of each portion of source / drain recess 805 under portion 340 correspond to the sidewalls of convex region 210. Source / drain recesses 805 can penetrate into the well regions (e.g., P-well, N-well) of fin structures 345. In embodiments where the semiconductor substrate 205 includes silicon (Si) material having a (100) orientation, a (111) plane is formed at the bottom of source / drain recess 805, resulting in a V-shaped or triangular cross-section being formed at the bottom of source / drain recess 805. In some embodiments, wet etching using tetramethylammonium hydroxide (TMAH) and / or chemical dry etching using hydrochloric acid (HCl) are employed to form the V-shaped cross-section. However, the cross-section at the bottom of source / drain recess 805 can also include other shapes, such as circular or semi-circular, etc.

[0207] As Figure 8AAs shown by cross-sectional planes B-B and C-C in, after the etching operation to form the source / drain recesses 805, portions of the first layer 310 and portions of the second layer 315 of the layer stack 305 remain in the dummy gate structure 705. The portion of the second layer 315 under the dummy gate structure 705 forms the nanostructure channel 220 of the nanostructure transistor of the semiconductor device 200. The nanostructure channel 220 extends between adjacent source / drain recesses 805 and between adjacent hybrid fin structures 620.

[0208] As Figure 8B As shown by cross-sectional plane B-B in, the first layer 310 is etched laterally during the etching operation (e.g., along a direction approximately parallel to the length of the first layer 310), and cavities 810 are formed between portions of the nanostructure channel 220. Specifically, the etching tool 108 etches the ends of the first layer 310 under the dummy gate structure 705 laterally through the source / drain recesses 805. In an embodiment where the first layer 310 is silicon germanium (SiGe) and the second layer 315 is silicon (Si), the etching tool 108 can use a wet etchant, e.g., a mixed solution containing hydrogen peroxide (H2O2), acetic acid (CH3COOH), and / or hydrofluoric acid (HF), to selectively etch the first layer 310, and then clean with water (H-2-O). The mixed solution and water can be provided into the source / drain recesses 805 to etch the first layer 310 from the source / drain recesses 805. In some embodiments, etching with the mixed solution and cleaning with water are repeated about 10 times to about 20 times. In some embodiments, the etching time of the mixed solution is in the range of about 1 minute to about 2 minutes. The mixed solution can be used at a temperature in the range of about 60 degrees Celsius to about 90 degrees Celsius. However, other parameter values of the etching operation are also within the scope of this disclosure.

[0209] The cavity 810 can be formed in a generally curved shape, a generally concave shape, a generally triangular shape, a generally square shape, or other shapes. In some embodiments, the depth of one or more cavities 810 (e.g., the dimension by which the cavity extends from the source / drain recess 805 into the first layer 310) ranges from about 0.5 nanometers to about 5 nanometers. In some embodiments, the depth of one or more cavities 810 ranges from about 1 nanometer to about 3 nanometers. However, other values of the depth of the cavity 810 are also within the scope of this disclosure. In some embodiments, the etch tool 108 forms the cavity 810 with a length (e.g., the dimension by which the cavity extends from the nanostructure channel 220 under the first layer 310 into another nanostructure channel 220 above the first layer 310) such that the cavity 810 partially extends into the side of the nanochannel 220 (e.g., such that the width and length of the cavity 810 are greater than the thickness of the first layer 310). In this way, the internal spacer formed within the cavity 810 can extend into the portion of the end of the nanostructure channel 220. In some embodiments, forming the cavity 810 causes thinning of the coated sidewalls 510 in the source / drain recess 805.

[0210] As Figure 8C shown in cross-sectional planes A-A and B-B in x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or other dielectric materials. The insulating layer 815 may comprise a material different from the spacer layer 720.

[0211] The deposition tool 102 forms the insulating layer 815 with a thickness sufficient to fill the cavity 810 between the nanostructure channels 220. For example, the insulating layer 815 can be formed with a thickness in the range of about 1 nanometer to about 10 nanometers. As another example, the insulating layer 815 can be formed with a thickness in the range of about 2 nanometers to about 5 nanometers. However, other values of the thickness of the insulating layer 815 are also within the scope of this disclosure.

[0212] As Figure 8D shown in cross-sectional planes A-A and B-B in Figure 8DAs further shown by cross-sectional plane A-A in [FIGURE REFERENCE], the coated sidewalls 510 can also be removed from the source / drain recesses 805 during the etching operation to partially remove the insulating layer 815.

[0213] In some embodiments, the etching operation can cause the surface of the inner spacer 245 facing the source / drain recesses 805 to bend or dent. The depth of the dent in the inner spacer 245 can range from about 0.2 nanometers to about 3 nanometers. By another example, the depth of the dent in the inner spacer 245 can range from about 0.5 nanometers to 2 nanometers. By yet another example, the depth of the dent in the inner spacer 245 can be in the range of less than about 0.5 nanometers. In some embodiments, the surface of the inner spacer 245 facing the source / drain recesses 805 is approximately flat, such that the surfaces of the inner spacer 245 and the ends of the nanostructure channels 220 are generally smooth and conforming.

[0214] As Figure 8E As shown by cross-sectional plane A-A and cross-sectional plane B-B in [FIGURE REFERENCE], one or more layers fill the source / drain recesses 805 to form source / drain regions 225 in the source / drain recesses 805. For example, the deposition tool 102 can deposit a buffer layer 230 at the bottom of the source / drain recesses 805, the deposition tool 102 can deposit the source / drain regions 225 on the buffer layer 230, and the deposition tool 102 can deposit a capping layer 235 on the source / drain regions 225. The buffer layer 230 can include silicon (Si), boron-doped silicon (SiB), additional dopants, and / or other materials. The buffer layer 230 can be included to reduce, minimize, and avoid dopant migration and leakage current from the source / drain regions 225 to the adjacent protrusion regions 210, which could otherwise cause short-channel effects in the semiconductor device 200. Thus, the buffer layer 230 can enhance the performance of the semiconductor device 200 and / or increase the yield of the semiconductor device 200.

[0215] The source / drain 225 can include one or more layers of epitaxially grown material. For example, the deposition tool 102 can epitaxially grow the first layer (referred to as L1) of the source / drain regions 225 on the buffer layer 230, and can epitaxially grow the second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain regions 225 on the first layer. The first layer can include a lightly doped silicon (e.g., doped with boron (B), phosphorus (P), and / or other dopants), and can be included as a shielding layer to reduce short-channel effects in the semiconductor device and reduce dopant push or migration into the nanostructure channels 220. The second layer can include highly doped silicon or highly doped silicon germanium. The second layer can be included to provide compressive stress in the source / drain regions 225 to reduce boron loss.

[0216] As Figure 8EFurther shown, the hybrid fin structure 620 is formed such that the hybrid fin structure 620 extends onto the top of the source / drain region 225. Specifically, the top surface of the high-k layer 615 of the hybrid fin structure 620 may be located at a height greater than the top of the source / drain region in the semiconductor device 200. In some embodiments, the bottom surface of the high-k layer 615 of the hybrid fin structure 620 may be located at a height greater than the top of the source / drain region 225. As Figure 9G detailed in the related content, the relatively large height of the hybrid fin structure 620 can reduce the tortuosity of the active region isolation recesses formed between adjacent source / drain regions 225. Therefore, the relatively large height of the hybrid fin structure 620 can reduce the critical dimension load and / or can reduce the epitaxial damage of the source / drain regions 225 on the opposite side of the active region isolation recesses.

[0217] As described above, Figures 8A to 8E is provided as an example, and other examples may be different from those discussed in Figures 8A to 8E . The exemplary embodiment 800 may include additional operations, fewer operations, different operations, and / or a different order of operations compared to those described in conjunction with Figures 8A to 8E .

[0218] Figures 9A to 9I FIG. is a schematic diagram of an example of the active region isolation structure formation process described herein. The exemplary embodiment 900 includes an example of forming an active region isolation structure (such as a CPODE structure) in the semiconductor device 200 before a replacement gate process (described in the related content) that replaces the dummy gate structure 705 with the gate structure 240 (metal gate structure) of the semiconductor device 200. Therefore, the exemplary embodiment 900 may be referred to as a front-end (FEOL) CPODE process. The active region isolation structure may be formed along the dummy gate structure 705 to create an electrically isolated region in the stack of the nanostructure channels 220 under one or more protrusion regions 210 and / or one or more gate structures 220. Therefore, the active region isolation structure enables the underlying nanostructure channels 220 to be divided into several (electrically isolated) nanostructure channels 220. Figures 10A to 10D is illustrated from multiple perspectives shown in

[0219] Figures 9A to 9I by Figure 7A , including the perspective of the cross-sectional plane A-A shown in Figure 7A , the perspective of the cross-sectional plane B-B shown in Figure 7A and the perspective of the cross-sectional plane C-C shown in Figure 7A . In some embodiments, the operations described in conjunction with the exemplary embodiment 900 are performed after the operations in conjunction with Figures 3A to 8E . As shown in Figure 9A , the FEOL CPODE process may be in conjunction with Figures 8A to 8EAfter the described source / drain region formation process.

[0220] As Figure 9B shown, a hard mask layer 905 may be formed on the semiconductor device 200. The hard mask layer 905 may be formed to use a pattern to etch the dummy gate structure 705 to form a recess in which the active region isolation structure will be formed. The hard mask layer 905 may comprise a dielectric material such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), high-k dielectric materials, and / or other suitable dielectric materials. The deposition tool 102 may deposit the hard mask layer 905 using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, another deposition technique described in conjunction with Figure 1 and / or other suitable deposition techniques. In some embodiments, the planarization tool 110 may be used to planarize the hard mask layer 905 after depositing the hard mask layer 905.

[0221] As Figure 9C shown, a patterned stack 910 may be formed on the hard mask layer 905. The patterned stack 910 may be used to pattern the hard mask layer 905 to form active region isolation recesses through the dummy gate structure 705. The patterned stack 910 may comprise one or more mask layers, such as an underlying layer 915, an intermediate layer 920, and a top layer 925. The underlying layer 915 may comprise a carbon-containing material and / or other suitable materials. The intermediate layer 920 may comprise an oxide-containing material and / or other suitable materials. The top layer 925 may comprise a photoresist layer used to transfer the pattern 930 to the underlying layer 915 and the intermediate layer 920. The different materials of the underlying layer 915 and the intermediate layer 920 provide an etch selectivity between the underlying layer 915 and the intermediate layer 920, enabling the aspect ratio of the pattern 930 to be tightly controlled.

[0222] The deposition tool 102 may deposit the underlying layer 915 and the intermediate layer 920 using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, another deposition technique described in conjunction with Figure 1 and / or other suitable deposition techniques. In some embodiments, the planarization tool 110 may be used to planarize the underlying layer 915 and / or the intermediate layer 920 after depositing the underlying layer 915 and / or the intermediate layer 920. The deposition tool 102 may deposit the top layer 925 using spin coating techniques and / or other suitable deposition techniques.

[0223] As Figure 9CAs shown, the pattern 930 can be formed in the top layer 925. In some embodiments, a wet cleaning operation can be performed before forming the pattern 930. The top layer 925 can be exposed to a radiation source using an exposure tool 104 to form the pattern 930, and a developing tool 106 can be used to develop and remove portions of the top layer 925 to expose the pattern 930. The pattern 930 can be formed over a portion of the dummy gate structure 705.

[0224] As Figure 9D shown, the pattern 930 is transferred to the bottom layer 915 and the middle layer 920 of the patterned stack 910. An etching tool 108 can etch the bottom layer 915 and the middle layer 920 according to the pattern 930 in the top layer 925 to transfer the pattern 930 to the bottom layer 915 and the middle layer 920. In some embodiments, the etching operation includes dry etching (e.g., plasma dry etching). In some embodiments, the etching operation includes another etching operation, such as a wet chemical etching operation.

[0225] As Figure 9D Further shown, the pattern 930 in the bottom layer 915 and the middle layer 920 can be used to form active region isolation recesses 935 (e.g., CPODE recesses) in the hard mask layer 905. An etching tool 108 can be used to etch the hard mask layer 905 according to the pattern 930 in the bottom layer 915 and the middle layer 920 to form the active region isolation recesses 935. In some embodiments, the etching operation includes dry etching (e.g., plasma dry etching). In some embodiments, the etching operation includes another etching operation, such as a wet chemical etching operation. The etching operation can terminate at the dummy gate structure 705.

[0226] As Figure 9E shown, after forming the active region isolation recesses 935, a photoresist removal tool can be used to remove the remaining portions of the patterned stack 910 (e.g., using a chemical remover, plasma ashing, and / or other techniques). In some embodiments, a wet cleaning operation can be performed after forming the active region isolation recesses 935.

[0227] As Figure 9F shown, the dummy gate structure 705 can be etched to extend the active region isolation recesses 935 into the STI region 215 under the dummy gate structure 705. The etching can terminate at the gate dielectric layer 725. The etching operation can expose the high-k layer 610 of the hybrid fin structure 620 through the active region isolation structure 935. An etching tool 108 can be used to etch the dummy gate structure 705. In some embodiments, the etching operation includes dry etching (e.g., plasma dry etching). In some embodiments, the etching operation includes another etching operation, such as a wet chemical etching operation.

[0228] As Figure 9GAs shown, the nanostructured channel 220 and the first layer 310 (e.g., a sacrificial silicon germanium (SiGe) layer) between adjacent source / drain regions 225 on the opposite side of the active region isolation recess 935 can be removed after etching the sacrificial gate structure 705. In addition, the protrusion region 210 under the nanostructured channel 220 can be removed by the active region isolation structure 965. The STI region 215 exposed in the active region isolation structure 935 under the hybrid gate structure 620 can be retained together with the dielectric layer 610 of the hybrid gate structure 620 and the coated sidewalls 510 exposed in the active region isolation structure 935.

[0229] The active region isolation recess 935 extends under the source / drain region 255 and into the region originally occupied by the removed protrusion region 210. In some embodiments, the bottom surface of the active region isolation recess 935 can be coplanar with the bottom surface of the STI region 215. In some embodiments, the bottom surface of the active region isolation recess 935 can extend under the bottom surface of the STI region 215.

[0230] In some embodiments, remote coupled plasma (RCP) is used in the etching tool 108 to remove the protrusion region 210, the nanostructured channel 220, and the first layer 310. The plasma can be a hydrogen bromide-based plasma etchant and / or other plasma-based etchants with added oxygen (O2) and / or carbon dioxide (CO2). The plasma can be generated by an inductively coupled plasma (ICP) manufacturing apparatus, a resonant antenna plasma source driven by a radio frequency (RF) power generator, and / or other plasma-based etching tools. The RF power generator can use a frequency that is a multiple of 13.56 MHz (e.g., 13.56 MHz, 27 MHz). The RF power generator can be operated to provide a source power in the range of approximately 100 watts to approximately 2500 watts. However, other values in this range are also within the scope of this disclosure. In some embodiments, pulsed plasma etching with a duty cycle in the range of approximately 10% to approximately 100% can be performed. However, other values in this range are also within the scope of this disclosure. The RF bias power from the RF power generator to the pedestal in the processing chamber of the etching tool 108 can be in the range of approximately 10 watts to approximately 2000 watts. However, other values in this range are also within the scope of this disclosure. The processing chamber of the etching tool 108 can be operated at a pressure in the range of approximately 3 millitorr (mTorr) to approximately 150 millitorr. However, other values in this range are also within the scope of this disclosure. The processing chamber of the etching tool 108 can be operated at a temperature in the range of approximately 20 degrees Celsius to approximately 150 degrees Celsius. However, other values in this range are also within the scope of this disclosure.

[0231] In some embodiments, during the etching operations for removing the protrusion region 210, the nanostructure channels 220, and the first layer 310, one or more methane (CH4)-based deposition operations may be performed to protect the hard mask layer 905. A passivation operation, such as a silicon tetrachloride (SiCl4) passivation operation or an oxygen (O2) passivation operation, may be performed to form a passivation layer to reduce the likelihood and extent of etching into layers other than the protrusion region 210, the nanostructure channels 220, and the first layer 310. After the passivation operation, a breakthrough operation using tetrafluoromethane (CF4), trifluoromethane (CF3), difluoromethane (CF2), and / or hexafluoroethane (C2F6) may be performed to remove the passivation layer from the bottom surface of the active region isolation structure 935, enabling further etching of the active region isolation structure 935.

[0232] The hybrid fin structure 620 extending to the top surface of the source / drain region 225 may reduce the tortuosity of the active region isolation recess 935. Thus, removing the hybrid fin structure 620 extending to the top surface of the source / drain region 225 may reduce the critical dimension load and / or reduce the epitaxial damage to the source / drain region 225 on the opposite side of the active region isolation recess 935. Specifically, the hybrid fin structure 620 extending to the top surface of the source / drain region 225 causes the width of the active channel isolation recess 935 to be greater than the height reduction of the top surface of the source / drain region 225 in the semiconductor device 200. As shown in the cross-sectional plane C-C in Figure 9G , the width of the active region isolation recess 935 decreases at the high-k dielectric layer 615 of the hybrid fin structure 620. Accordingly, the density of the etchant flow (e.g., ions and radicals in the etchant) in the active region isolation recess 935 and the pressure in the active region isolation recess 935 increase at the height of the high-k dielectric layer 615 in the active region isolation recess 935. The increased etchant flow density and pressure may otherwise cause an increase in the etching rate in the width reduction region of the active region isolation recess 935, especially if the width reduction occurs at the height of the source / drain region 225 (which would occur otherwise if the hybrid fin structure 620 is below the source / drain region 225 in the semiconductor device 200). However, the high-k dielectric layer 615, due to its high-k dielectric material, can withstand the increased etchant flow density and pressure. Specifically, the high-k dielectric material of the high-k dielectric layer 615 can withstand etching because the etchant used to etch the protrusion region 210, the first layer 310, and the nanostructure channels 220 is selected to etch silicon (or silicon-containing materials) and may not be effective in etching the high-k dielectric material of the high-k dielectric layer 615 of the hybrid fin structure 620. Thus, the hybrid fin structure 620 extending to the top surface of the source / drain region 225 enables the hybrid fin structure to protect the source / drain region 225 (which may be formed of a silicon-containing material) from etching, thereby reducing the critical dimension load and / or reducing the epitaxial damage to the source / drain region 225.

[0233] As shown inFigure 9H As shown, the active region isolation structure 940 may be formed within the active region isolation recess 935. Specifically, the active region isolation structure 940 may be formed on the STI region 215 and on the hybrid fin structure 620 exposed in the active region isolation recess 935.

[0234] Forming the active region isolation structure 940 may include forming a dielectric liner 945 of the active region isolation structure 940 in the active region isolation recess 935 and filling the remaining volume of the active region isolation recess 935 with a dielectric layer 950 on the dielectric liner 945. The dielectric liner 945 may be conformally deposited on the sidewalls of the active region isolation recess 935 (corresponding to the sidewalls of the STI region 215, the dielectric layer 610 of the hybrid fin structure 620, the high-k dielectric layer 615 of the hybrid fin structure 620, and the dummy gate structure 705 exposed in the active region isolation recess 935). The dielectric liner may also be conformally deposited on the bottom surface of the active region isolation recess 935 corresponding to the semiconductor substrate 205. The deposition tool 102 may use PVD technology, ALD technology, CVD technology, oxidation technology, another deposition technology described in conjunction with Figure 1 and / or other suitable deposition technologies to deposit the dielectric liner 945. The dielectric liner 945 may include a dielectric material such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluorinated silicate glass (FSG), high-k dielectric materials, and / or other suitable dielectric materials.

[0235] The dielectric layer 950 may overfill the active region isolation recess 935 to ensure that the active region isolation recess 935 is completely filled with the dielectric layer 950 and to minimize the formation of gaps and voids in the active region isolation structure 940. The deposition tool 102 may use PVD technology, ALD technology, CVD technology, oxidation technology, another deposition technology described in conjunction with Figure 1 and / or other suitable deposition technologies to deposit the dielectric layer 950. The dielectric layer 950 may include a dielectric material such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluorinated silicate glass (FSG), high-k dielectric materials, and / or other suitable dielectric materials.

[0236] Such as Figure 9IAs shown, a planarization operation may be performed after forming the multiple layers of the active region isolation structure 940 to planarize the semiconductor device 200. The planarization tool 110 may be used to planarize the semiconductor device 200 to remove the hard mask layer 905 (except for the portion of the hard mask layer 905 that is below the top surface of the dummy gate structure 705) to remove excess material of the dielectric liner 945 and / or remove excess material of the dielectric layer 950.

[0237] As described above, Figures 9A to 9I is provided as an example, and other examples may differ from Figures 9A to 9I those discussed in. The exemplary embodiment 900 may include additional operations, fewer operations, different operations, and / or a different order of operations compared to that described in conjunction with Figures 9A to 9I those.

[0238] Figures 10A to 10D is a schematic diagram of an example of a replacement gate process (RGP) described herein. The exemplary embodiment 1000 includes an example of a replacement gate process in which a gate structure 240 (e.g., a replacement gate structure) replaces the dummy gate structure 705 of the semiconductor device 200. Figures 10A to 10D is illustrated by multiple perspectives shown in Figure 7A including the perspective of the cross-sectional plane A-A shown in Figure 7A including the perspective of the cross-sectional plane B-B shown in Figure 7A including the perspective of the cross-sectional plane C-C shown in Figure 7A In some embodiments, the operations described in conjunction with the exemplary embodiment 1000 are performed after the operations in conjunction with Figures 3A to 9I those.

[0239] As Figure 10A shown by the cross-sectional plane A-A and the cross-sectional plane B-B in, the ILD layer 250 is formed over the source / drain regions 225. The ILD layer 250 fills the spaces between the dummy gate structures 705, between the hybrid fin structures 620, and over the source / drain regions 225. The ILD layer is formed to prevent the source / drain regions 225 from being damaged during the replacement gate process. The ILD layer 250 may be referred to as the ILD0 layer or another ILD layer.

[0240] In some embodiments, prior to forming the ILD layer 250, a contact etch stop layer (CESL) is conformally deposited over the source / drain regions 225, over the dummy gate structures 705, and over the spacer layer 720. The ILD layer 250 is then formed over the CESL. The CESL may provide a mechanism for stopping etching when forming contacts or vias to the source / drain regions 225. The CESL may be formed of a dielectric material having a different etch selectivity from adjacent layers or components. The CESL may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Additionally, the CESL may include or may be silicon nitride (Six N y ) silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon carbon oxide (SiCO), or a combination thereof, etc. The CESL can be deposited by a deposition process such as ALD, CVD, or other deposition techniques.

[0241] As Figure 10B shown in cross-sectional planes B-B and C-C in [reference], a dummy gate operation (e.g., with one or more semiconductor processing tools 102 to 112) is performed to remove the dummy gate structure 705 from the semiconductor device 200. Removing the dummy gate structure 705 leaves an opening 1005 (or recess) between the ILD layers 250 on the source / drain regions 225 and between the hybrid fin structures 620. The dummy gate structure 705 can be removed in one or more etching operations. The etching operation can include plasma etching techniques, wet chemical etching techniques, and / or other types of etching techniques.

[0242] As Figure 10C shown in cross-sectional planes B-B and C-C in [reference], a nanostructure release operation (e.g., SiGe release operation) is performed to remove the first layer 310 (e.g., silicon germanium layer). This creates an opening 1005 between the nanostructure channels 220 (e.g., in the region surrounding the nanostructure channels 220). The nanostructure release operation can include performing an etching operation with the etching tool 108 to selectively remove the first layer 310 based on the etching selectivity between the material of the first layer 310 and the material of the nanostructure channels 220 and between the material of the first layer 310 and the material of the inner spacers 245. The inner spacers 245 can act as an etch stop layer in the etching operation to protect the source / drain regions 225 from etching. As Figure 10C further shown in [reference], the sidewall coating 510 is removed in the nanostructure release operation, thus providing access to the perimeter of the nanostructure channels 220 and enabling a replacement gate structure (e.g., gate structure 240) to be formed completely around the nanostructure channels 220.

[0243] As Figure 10DAs shown by cross-sectional planes B-B and C-C in, instead of the gate operation continuing while the deposition tool 102 and / or the plating tool 112 form a gate structure 240 (e.g., a replacement gate structure) in the opening 1005 between the source / drain regions 225 and between the hybrid fin structures 620. Specifically, the gate structure 240 fills the region between the nanostructure channels 220 and the region surrounding the nanostructure channels 220 that was originally occupied by the first layer 310 and the coated sidewalls 510, such that the gate structure 240 completely encapsulates and surrounds the nanostructure channels 240. The gate structure 240 may include a metal gate structure. Before forming the gate structure 240, a conformal high-k liner 1010 may be deposited on the nanostructure channels 220 and the sidewalls. The high-k liner 1010 may be a gate dielectric layer between the gate structure 240 and the nanostructure channels 220. The gate structure 240 may include additional layers, such as an interface layer, a work function tuning layer, and / or a metal electrode structure, etc.

[0244] As Figure 10D As further shown by cross-sectional plane C-C in, the coating layer 505 is removed from the top of the STI region 215 to avoid the coated sidewalls 510 including a pedestal between the protruding regions 210 adjacent below the hybrid fin structures 620, such that the gate structure 240 can be formed without the gate structure 240 including a pedestal under the hybrid fin structures 620. In other words, since the gate structure 240 is formed in the region originally occupied by the coated sidewalls 510, the absence of a pedestal of the coated sidewalls 510 under the hybrid fin structures 620 also results in the absence of a pedestal of the gate structure 240 under the hybrid fin structures 620. This reduces and / or avoids a short circuit between the gate structure 240 and the source / drain regions 225 under the hybrid fin structures.

[0245] As described above, Figures 10A to 10D is provided as an example, and other examples may be different from Figures 10A to 10D those discussed in. The exemplary embodiment 1000 may include additional operations, fewer operations, different operations, and / or a different order of operations compared to Figures 10A to 10D that described in connection with

[0246] Figures 11A to 11ISchematic diagram of exemplary embodiment 1100 of an active region isolation structure formed as described herein. Exemplary embodiment 1100 includes an example of forming an active region isolation structure (such as a CPODE structure) in semiconductor device 200 after a replacement gate process that replaces dummy gate structure 705 of semiconductor device 200 with gate structure 240. Thus, exemplary embodiment 1100 may be referred to as a MEOL CPODE process. The active region isolation structure may be formed along gate structure 240 to form electrical isolation in a stack of one or more protrusion regions 210 and / or one or more nanostructure channels 220 under gate structure 240. Thus, the active region isolation structure enables the nanostructure channels 220 thereunder to be separated into multiple (electrically isolated) nanostructure channels 220.

[0247] Figures 11A to 11I is depicted by Figure 7A multiple perspectives shown in Figure 7A the perspective of cross-sectional plane A-A shown in Figure 7A the perspective of cross-sectional plane B-B shown in Figure 7A and the perspective of cross-sectional plane C-C shown in Figures 3A to 10D . In some embodiments, the operations described in conjunction with exemplary embodiment 1100 are performed after the operations in conjunction with

[0248] As Figure 11A shown, a hard mask layer 1105 may be formed on semiconductor device 200. The hard mask layer 1105 may be formed to enable the gate structure 240 to be etched using a pattern to form a recess in which the active region isolation structure is formed. The hard mask layer 1105 may include a dielectric material such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluorinated silicate glass (FSG), high-k dielectric materials, and / or other suitable dielectric materials. Deposition tool 102 may deposit the hard mask layer 1105 using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, another deposition technique described in conjunction with Figure 1 and / or other suitable deposition techniques. In some embodiments, planarization tool 110 may be used to planarize the hard mask layer 1105 after depositing the hard mask layer 1105.

[0249] As Figure 11AAs further shown, a gate isolation structure 1110 (e.g., a sliced metal gate (CMG) isolation structure or other types of gate isolation structures) may be formed through the gate structure 240 to segment or divide the gate structure 240 into a plurality of electrically isolated gate structures 240. The gate isolation structure 1110 enables the gate structure 240 to operate independently, such that a plurality of transistors can be formed along the gate structure 240. The gate isolation structure 1110 may extend in a direction (e.g., the Y-axis direction) approximately perpendicular to the gate structure 240 (such as the X-axis direction).

[0250] To form the gate isolation structure 1110, a gate isolation recess may be formed through the gate structure 240 and into one or more STI regions 215 under the gate structure. In some embodiments, a pattern in a photoresist layer may be used to etch the gate structure 240 and the STI regions 215 to form the gate isolation recess. In these embodiments, a deposition tool 102 may be used to form the photoresist layer on the gate structure 240. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove a portion of the photoresist layer to expose the pattern. An etching tool 108 may be used to etch the gate structure 240 and the STI regions 215 according to the pattern to form the gate isolation recess in the gate structure 240 and the STI regions 215. In some embodiments, the etching operation may include plasma etching techniques, wet chemical etching techniques, and / or other types of etching techniques. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using chemical desorption, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for forming the gate isolation recess according to the pattern.

[0251] The deposition tool 102 may utilize PVD techniques, ALD techniques, CVD techniques, oxidation techniques, another deposition technique described in conjunction with Figure 1 and / or other suitable deposition techniques to deposit the material of the gate isolation structure 1110 into the gate isolation recess. In some embodiments, the gate isolation structure 1110 may be formed in one or more deposition operations in the same set as the hard mask layer 1105, such that the gate isolation structure 1110 and the hard mask layer 1105 may be formed of the same material. For example, the deposition tool 102 may deposit the material of the gate isolation structure 1110 in the gate isolation recess, and continue to deposit an excess of the material on the gate structure 240 to form the hard mask layer 1105 after the gate isolation recess is filled.

[0252] As Figure 11BAs shown, the patterned stack 1120 can be formed on the hard mask layer 1105. The patterned stack 1120 can be used to pattern the hard mask layer to form active region isolation recesses between the gate isolation structures 1110. The patterned stack can include one or more mask layers, such as the bottom layer 1125, the middle layer 1130, and the top layer 1135. The bottom layer 1125 can include a carbon-containing material and / or other suitable materials. The middle layer 1130 can include an oxide-containing material and / or other suitable materials. The top layer 1135 can include a photoresist layer used to transfer the pattern 1140 to the bottom layer 1125 and the middle layer 1130. The different materials of the bottom layer 1125 and the middle layer 1130 provide different etching selectivities between the bottom layer 1125 and the middle layer 1130, enabling the aspect ratio of the pattern 1140 to be tightly controlled.

[0253] The deposition tool 102 can be used to deposit the bottom layer 1125 and the middle layer 1130 using PVD technology, ALD technology, CVD technology, oxidation technology, another deposition technology described in conjunction with Figure 1 and / or other suitable deposition technologies. In some embodiments, the planarization tool 110 can be used to planarize the bottom layer 1120 and / or the middle layer 1130 after the deposition of the bottom layer 1125 and the middle layer 1130. The deposition tool 102 can be used to form the top layer 1135 using spin coating and / or other suitable techniques.

[0254] As Figure 11B further shown, the pattern 1140 can be formed in the top layer 1135. In some embodiments, a wet cleaning operation can be performed before forming the pattern 1140. The pattern 1140 can be exposed to a radiation source using the exposure tool 104 to expose the top layer 1135 to form the pattern 1140, and developed using the development tool 106 to remove portions of the top layer 1135 to expose the pattern 1140. The pattern 1140 can be formed over a portion between the gate isolation structures 1110 of the gate structure 240.

[0255] As Figure 11C shown, the pattern 1140 is transferred to the bottom layer 1125 and the middle layer 1130 of the patterned stack 1120. The etching tool 108 can be used to etch the bottom layer 1125 and the middle layer 1130 according to the pattern 1140 in the top layer 1135 to transfer the pattern 1140 to the bottom layer 1125 and the middle layer 1130. In some embodiments, the etching operation includes dry etching (such as a plasma etching operation). In some embodiments, the etching operation includes other types of etching operations, such as a wet chemical etching operation.

[0256] As Figure 11CFurther shown, the patterns 1140 in the bottom layer 1125 and the middle layer 1130 can be used to form active region isolation recesses 1145 (e.g., CPODE recesses) in the hard mask layer 1105. An etching tool 108 can be used to etch the hard mask layer 1105 according to the patterns 1140 in the bottom layer 1125 and the middle layer 1130 to form the active region isolation recesses 1145. In some embodiments, the etching operation includes dry etching (e.g., plasma dry etching). In some embodiments, the etching operation includes another etching operation, such as a wet chemical etching operation. The etching operation can terminate at the gate structure 240. In some embodiments, after forming the active region isolation recesses 1145, a photoresist removal tool can be used to remove the remaining portions of the patterned stack 1120 (e.g., using chemical desorption, plasma ashing, and / or other techniques). In some embodiments, a wet cleaning operation can be performed after forming the active region isolation recesses 1145.

[0257] As Figure 11D shown in, the gate structure 240 can be etched to extend the active region isolation recesses 1145 into the STI region 215 under the gate structure 240. The active region isolation recesses 1145 can be formed through the gate structure 240 between the gate isolation structures 1110. The etching operation can remove the portions of the high-k liner 1010 between the gate isolation structures 1110.

[0258] The gate structure 240 can be etched using the gate isolation structures 1110 and the hard mask layer 1105 as self-aligned patterns based on the etching selectivity between the gate structure 240, the gate isolation structures 1110, and the hard mask layer 1105. In other words, no other mask layer / patterning layer is required, and the hard mask layer 1105 and the gate isolation structures 1110 control the position of etching the gate structure 240. An etching tool 108 can be used to etch the gate structure 240 and the high-k liner 1010. In some embodiments, the etching operation includes dry etching (e.g., plasma dry etching). In some embodiments, the etching operation includes another etching operation, such as a wet chemical etching operation.

[0259] The nanostructure channels 220 between the gate isolation structures 1110 can be exposed in the active region isolation recesses 1145 after etching the gate structure 240 and the high-k liner 1010. In addition, the portions under the nanostructure channels 220 between the gate isolation structures 1110 in the protrusion region 210 can be exposed in the active region isolation recesses 1145 after etching the gate structure 240 and the high-k liner 1010. In some embodiments, a wet cleaning operation can be performed after etching the gate structure 240 and the high-k liner 1010.

[0260] As Figure 11EAs shown, between the gate isolation structures 1110, the nanostructured channel 220 exposed in the active region isolation recess 1145 can be removed after etching the gate structure 240 and the high-k liner 1010. In addition, the protrusion region 210 under the nanostructured channel 220 can be removed through the active region isolation recess 1145. A low-selectivity etching technique can be used to remove the protrusion region 210, the STI region 215, and the nanostructured channel 220. The low-selectivity etching technique can include using an etchant in the etching tool 108 that can etch the protrusion region 210, the STI region 215, and the nanostructured channel 220 at a similar etching rate.

[0261] The active region isolation recess 1145 extends into and into the semiconductor substrate 205. As Figure 11E shown, the bottom surface of the active region isolation recess 1145 can have regions of different profiles or segments. For example, the protrusion segment 1150 (e.g., the segment where the protrusion region 210 is removed) can be raised above the inner STI segment 1155 (the segment where the STI region 215 is removed from the sidewall adjacent to the active region isolation recess 1145) and the outer STI segment 1160 (the segment where the STI region 215 is removed from the protrusion region 210). This can occur due to the different etching rates of the protrusion region 210 and the STI region 215. In addition, the nanostructured channel 220 can impede the etchant from reaching the underlying protrusion region 210, causing a delay in the etching of the protrusion region 210 and potentially causing the protrusion segment 1150 to be higher than the inner STI segment 1155 and the outer STI segment 1160.

[0262] In some embodiments, remote coupled plasma (RCP) is used in the etching tool 108 to remove the protrusion region 210, the STI region 215, and the nanostructured channel 220. The plasma can be a hydrogen bromide (HBr)-based plasma etchant, a chlorine (Cl2)-based plasma etchant, a boron trichloride (BCl3)-based plasma etchant, and / or other oxygen (O2)- and / or carbon dioxide (CO2)-containing plasma-based etchants. The higher the concentration of BCl3 or Cl2 in the plasma-based etchant, the smaller the etching selectivity between the protrusion region 210 (e.g., silicon) and the STI region 215 (e.g., silicon dioxide).

[0263] Plasma can be generated by an inductively coupled plasma (ICP) manufacturing apparatus, a resonant antenna plasma source driven by an RF power generator, and / or other plasma-based etching tools. The RF power generator can use frequencies that are multiples of 13.56 MHz (e.g., 13.56 MHz, 27 MHz). The RF power generator can be operated to provide source power in the range of approximately 100 watts to approximately 2500 watts. However, other values within this range are also within the scope of this disclosure. In some embodiments, pulsed plasma etching with a duty cycle in the range of approximately 10% to approximately 100% can be performed. However, other values within this range are also within the scope of this disclosure. The RF bias power from the RF power generator to the pedestal in the processing chamber of the etching tool 108 can be in the range of approximately 10 watts to approximately 2000 watts. However, other values within this range are also within the scope of this disclosure. The processing chamber of the etching tool 108 can be operated at a pressure in the range of approximately 3 millitorr (mTorr) to approximately 150 mTorr. However, other values within this range are also within the scope of this disclosure. The processing chamber of the etching tool 108 can be operated at a temperature in the range of approximately 20 degrees Celsius to approximately 150 degrees Celsius. However, other values within this range are also within the scope of this disclosure.

[0264] In some embodiments, one or more methane (CH4)-based deposition operations can be performed to protect the hard mask layer 1105 during the etching operations that remove the protrusion region 210, the STI region 215, and the nanostructure channels 220. Passivation operations, such as silicon tetrachloride (SiCl4) passivation operations or oxygen (O2) passivation operations, can be performed to form a passivation layer to reduce the likelihood and extent of etching into layers other than the protrusion region 210, the STI region 215, and the nanostructure channels 220. After the passivation operation, a breakthrough operation using tetrafluoromethane (CF4), trifluoromethane (CF3), difluoromethane (CF2), and / or hexafluoroethane (C2F6) can be performed to remove the passivation layer from the bottom surface of the active region isolation recess 1145, enabling further etching of the active region isolation recess 1145.

[0265] Removing the STI region 215 from the active region isolation recess 1145 can reduce the tortuosity of the active region isolation recess 1145. Accordingly, removing the STI region 215 from the active region isolation recess 1145 can reduce the critical dimension load and / or can reduce epitaxial damage to the source / drain regions 225 located on the opposite side of the active region isolation recess 1145. Specifically, removing the STI region 215 from the active region isolation recess 1145 reduces the number and severity of width variations in the active region isolation recess 1145. In other words, removing the STI region 215 from the active region isolation recess 1145 makes the width between the top and bottom of the active region isolation recess 1145 more consistent. The consistent width of the active region isolation recess 1145 reduces and / or minimizes the volume reduction from the top to the bottom of the active region isolation recess 1145, resulting in a more stable and consistent etchant flow density (e.g., ions and free radicals in the etchant) and a more stable and consistent pressure (e.g., compared to not removing the STI region 215) between the top and bottom of the active region isolation recess 1145. The more stable and consistent etchant flow density and pressure between the top and bottom of the active region isolation recess 1145 make the etch rate more stable at and below the height of the source / drain regions 225, which can reduce the critical dimension load and / or can reduce epitaxial damage to the source / drain regions 225.

[0266] As Figure 11F shown, a dielectric liner 1165 of the active region isolation structure 1115 can be formed in the active region isolation recess 1145. The dielectric liner 1165 can be conformally deposited on the sidewalls of the active region isolation recess 1145 (corresponding to the sidewalls of the gate isolation structure 1110 exposed in the active region isolation recess 1145). The dielectric liner 1165 can be conformally deposited on the bottom surface of the active region isolation recess 1165, including the protrusion section 1150, the internal STI section 1155, and the external STI section 1160. The deposition tool 102 can use PVD technology, ALD technology, CVD technology, oxidation technology, another deposition technology described in conjunction with Figure 1 and / or other suitable deposition technologies to deposit the dielectric liner 1165. The dielectric liner 1165 can comprise a dielectric material such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluorinated silicate glass (FSG), high-k dielectric materials, and / or other suitable dielectric materials.

[0267] As Figure 11GAs shown, the active region isolation recess 1145 can be filled with a dielectric layer 1170 on the dielectric liner 1165 of the active region isolation structure 1115. The active region isolation recess 1145 can be overfilled with the dielectric layer 1170 to ensure that the active region isolation recess 1145 is completely filled with the dielectric layer 1170 and to minimize the formation of gaps and voids in the active region isolation structure 1115. The deposition tool 102 can utilize PVD technology, ALD technology, CVD technology, oxidation technology, another deposition technology described in conjunction with Figure 1 and / or other suitable deposition technologies to deposit the dielectric layer 1170. The dielectric layer 1170 can comprise a dielectric material such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluorinated silicate glass (FSG), high-k dielectric materials, and / or other suitable dielectric materials.

[0268] Such as Figure 11H As shown, a planarization operation can be performed after forming several layers of the active region isolation structure 1115 to planarize the semiconductor device 200. The planarization tool 110 can be used to planarize the semiconductor device 200 to remove the hard mask layer 1105, remove excess material of the dielectric liner 1165, and / or remove excess material of the dielectric layer 1170.

[0269] The semiconductor device 200 can comprise a plurality of first nanostructure channels 220a on a first protrusion region 210a extending above the semiconductor substrate 205, and a plurality of second nanostructure channels 220b on a second protrusion region 210b extending above the semiconductor substrate 205. The first nanostructure channels 220a and the second nanostructure channels 220b are arranged in a direction perpendicular to the semiconductor substrate 205 (e.g., the Z-axis direction). The semiconductor device 200 can comprise a first gate structure 240a surrounding each first nanostructure channel 220a, and a second gate structure 240b surrounding each second nanostructure channel 220b. The semiconductor device 200 can comprise a first gate isolation structure 1110a and a second gate isolation structure 1110b between the first gate structure 240a and the second gate structure 240b. The semiconductor device 200 can comprise an active region isolation structure 1115 (e.g., a CPODE structure) between the gate isolation structures 1110a and 1110b. The active region isolation structure 1115 can be located between the first gate structure 240a and the first gate isolation structure 1110a, and between the second gate structure 240b and the second gate isolation structure 1110b. The bottom of the active region isolation structure 1115 can comprise a protrusion section 1150 extending into the semiconductor substrate 205 and into STI sections (e.g., an internal STI section 1155, an external STI section 1160) under one or more protrusion sections 1150.

[0270] Figure 11I Shows a top view of the semiconductor device 200. As Figure 11I shown, the nanostructure channels 220 may extend in the Y direction in the semiconductor device 200, and the gate structures 240 may extend in the X direction in the semiconductor device 200. The source / drain regions 225 may be recessed in one or more groups of nanostructure channels 220 such that the source / drain regions 225 are adjacent to the end regions of one or more groups of nanostructure channels 220. The gate isolation structures 1110a and 1110b may extend in the Y direction and may extend across one or more gate structures 240. The gate isolation structures 1110a and 1110b may divide one or more gate structures 240 into multiple gate structures, such as gate structures 240a and 240b. The gate isolation structures 1110a and 1110b may segment the gate structure 240 into multiple gate structures, such as gate structure 240a and gate structure 240b. The active region isolation structure 1115 segments one or more nanostructure channels 220c into portions on opposite sides of the multiple active region isolation structures 1115.

[0271] As described above, Figures 11A to 11I the number and arrangement of the operations shown are presented as one or more examples. Other examples may differ from Figures 10A to 10D those discussed in Figures 11A to 11I In practice, there may be additional operations and devices, fewer operations and devices, different operations and devices, or differently arranged operations and devices compared to

[0272] Figure 12 is a schematic diagram of a demonstration embodiment 1200 of the semiconductor device 200 described herein. Figure 12 is in a region where Figures 9A to 9I the FEOL CPODE process has been performed to form the active region isolation structure 940 of the semiconductor device 200. Figure 12 The left side of Figure 12 depicts that region of the semiconductor device in the Y-Z plane, and

[0273] As Figure 12 shown, the semiconductor device 200 may include one or more dimensions such as dimension D1, dimension D2, dimension D3, dimension D4, dimension D5, dimension D6, dimension D7, dimension D8, dimension D9, and dimension D10, etc.

[0274] The dimension D1 may correspond to the Y - axis width (sometimes referred to as the critical dimension or CD) of the height of the active region isolation structure 940 at the top of the hybrid fin structure 620 (e.g., the top surface height of the high - dielectric - constant layer 615 of the hybrid fin structure 620). In some embodiments, the dimension D1 may be in the range of approximately 22.9 nanometers to approximately 24.5 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0275] The dimension D2 may correspond to the Y - axis width of the height of the active region isolation structure 940 at the top of the top - most nanostructure channel 220. In some embodiments, the dimension D2 may be in the range of approximately 17.1 nanometers to approximately 19.3 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0276] The dimension D3 may correspond to the Y - axis width of the height of the active region isolation structure 940 at the bottom nanostructure channel 220. In some embodiments, the dimension D3 may be in the range of approximately 15.7 nanometers to approximately 18.6 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0277] The dimension D4 may correspond to the Y - axis width of the height of the active region isolation structure 940 below the bottom nanostructure channel 220 and the hybrid fin structure 620. In some embodiments, the dimension D4 may be in the range of approximately 18 nanometers to approximately 20 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0278] The dimensions D5 and D6 may correspond to the Z - axis depth, height, or thickness of the active region isolation structure 940 from the top of the STI region 215 to the top - most nanostructure channel 220. In some embodiments, the dimension D5 (in the Y - Z plane) may be in the range of approximately 63.7 nanometers to approximately 73.3 nanometers. However, other values and / or ranges are also within the scope of this disclosure. In some embodiments, the dimension D6 (in the Y - X plane) may be in the range of approximately 65.4 nanometers to approximately 72.8 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0279] The dimensions D7 and D8 may correspond to the Z - axis depth, height, or thickness of the active region isolation structure 940 to the top - most nanostructure channel 220. In some embodiments, the dimension D7 (in the Y - Z plane) may be in the range of approximately 153.3 nanometers to approximately 172.1 nanometers. However, other values and / or ranges are also within the scope of this disclosure. In some embodiments, the dimension D6 (in the Y - X plane) may be in the range of approximately 157.7 nanometers to approximately 169.4 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0280] The dimension D9 may correspond to the Z - axis thickness of the high - dielectric - constant layer 615 of the hybrid fin structure 620. In some embodiments, the dimension D9 may be in the range of approximately 22.9 nanometers to approximately 34.5 nanometers. However, other values and / or ranges are also within the scope of the present disclosure.

[0281] The dimension D10 may correspond to the total Z - axis thickness of the STI region 215 and the dielectric layer 610 of the hybrid fin structure 620. In some embodiments, the dimension D10 may be in the range of approximately 143.1 nanometers to approximately 143.9 nanometers. However, other values and / or ranges are also within the scope of the present disclosure.

[0282] As described above, Figure 12 Provided as an example, other examples may be different from Figure 12 those related.

[0283] Figure 13 FIG. 1300 is a schematic diagram of an exemplary embodiment of the semiconductor device 200 described herein. Figure 12 is a semiconductor device 200 in which the Figures 11A to 11I MEOL CPODE process is performed in a region to form the active region isolation structure 1115. Figure 13 The left side of FIG. depicts this region of the semiconductor device in the Y - Z plane, and Figure 13 the right side of FIG. depicts this region of the semiconductor device in the Z - X plane.

[0284] As Figure 13 shown, the semiconductor device 200 may include one or more dimensions such as dimension D11, dimension D12, dimension D13, dimension D14, dimension D15, dimension D16, dimension D17, dimension D18, and dimension D19, etc.

[0285] The dimension D11 may correspond to the Y - axis width of the height of the nanostructure channel 220 at the top of the active region isolation structure 1115. In some embodiments, the dimension D11 may be in the range of approximately 17.4 nanometers to approximately 19.6 nanometers. However, other values and / or ranges are also within the scope of the present disclosure.

[0286] The dimension D12 may correspond to the Y - axis width of the height of the nanostructure channel 220 at the bottom of the active region isolation structure 1115. In some embodiments, the dimension D12 may be in the range of approximately 14.9 nanometers to approximately 18.7 nanometers. However, other values and / or ranges are also within the scope of the present disclosure.

[0287] The dimension D13 may correspond to the Z - axis depth, height, or thickness from the active region isolation structure 1115 to the top - most nanostructure channel 220. In some embodiments, the dimension D13 may be in the range of approximately 170.3 nanometers to approximately 178.3 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0288] The dimension D14 may correspond to the angle between the sidewalls of the active region isolation structure 1115. In some embodiments, the dimension D14 may be in the range of approximately 5.7 degrees to approximately 6.7 degrees. However, other values and / or ranges are also within the scope of this disclosure.

[0289] The dimension D15 may correspond to the X - axis width of the height of the active region isolation structure 1115 at the top - most nanostructure channel 220. In some embodiments, the dimension D15 may be in the range of approximately 135.7 nanometers to approximately 138.5 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0290] The dimension D16 may correspond to the X - axis width of the height of the active region isolation structure 1115 at the bottom nanostructure channel 220. In some embodiments, the dimension D16 may be in the range of approximately 137.2 nanometers to approximately 138.3 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0291] The dimension D17 may correspond to the Z - axis depth, height, or thickness from the top of the external STI section 1160 (e.g., the section where the STI region is removed) of the active region isolation structure 1115 to the top - most nanostructure channel 220. In some embodiments, the dimension D17 may be in the range of approximately 145.8 nanometers to approximately 155.0 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0292] The dimension D18 may correspond to the Z - axis depth, height, or thickness from the top of the protrusion section 1150 (e.g., the section where the protrusion region is removed) of the active region isolation structure 1115 to the top - most nanostructure channel 220. In some embodiments, the dimension D18 may be in the range of approximately 127.2 nanometers to approximately 138.8 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0293] The dimension D19 may correspond to the Z - axis depth, height, or thickness from the top of the internal STI section 1155 (e.g., the section of the internal STI region) of the active region isolation structure 1115 to the top - most nanostructure channel 220. In some embodiments, the dimension D19 may be in the range of approximately 169.3 nanometers to approximately 178.6 nanometers. However, other values and / or ranges are also within the scope of this disclosure.

[0294] As described above,Figure 13 Provided as an example, other examples may differ from those Figure 13 described herein.

[0295] Figure 14 FIG. is a schematic diagram of an example component of the apparatus 1400 described herein. In some embodiments, one or more semiconductor processing tools 102 to 112 and / or wafer / die transfer tools 114 may include one or more apparatuses 1400 and / or one or more components of the apparatus 1400. As Figure 14 shown, the apparatus 1400 may include a port 1410, a processor 1420, a memory 1430, an input component 1440, an output component 1450, and / or a communication component 1460.

[0296] The port 1410 may include components that enable wired and / or wireless communication between multiple components of one or more apparatuses 1400. The port 1410 may couple Figure 14 one or more components, for example, by operative coupling, communication coupling, electrical coupling, and / or electro - coupling. For example, the port 1410 may include electrical connections (such as wires) and / or wireless ports. The processor 1420 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field - programmable gate array, an application - specific integrated circuit, and / or other types of processing components. The processor 1420 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, the processor 1420 may include one or more processors programmable to perform one or more operations or processes described elsewhere herein.

[0297] The memory 1430 may include volatile and / or non - volatile memory. For example, the memory 1430 may include random access memory (RAM), read - only memory (ROM), a hard disk drive, and / or other types of memory (such as flash memory, magnetic memory, and / or optical memory). The memory 1430 may include built - in memory (such as RAM, ROM, or a hard disk drive) or removable memory (such as removable via a universal serial bus). The memory 1430 may be a non - transitory computer - readable medium. The memory 1430 may store information related to the operation of the apparatus 1400, one or more instructions, and / or software (such as one or more software applications). In some embodiments, the memory 1430 may include one or more memories (such as communication - coupled) to one or more processors (such as the processor 1420), for example, via the port 1410. The communication coupling between the processor 1420 and the memory 1430 may enable the processor 1420 to read and process information stored in the memory 1430 and / or store information in the memory 1430.

[0298] The input component 1440 may enable the device 1400 to receive inputs, such as user inputs and / or sensed inputs. For example, the input component 1440 may include a touch screen, a keyboard, a keypad, a mouse, buttons, a microphone, switches, sensors, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. The output component 1450 may enable the device 1400 to provide outputs, such as via a display, a speaker, and / or a light emitting diode. The communication component 1460 may enable the device 1400 to communicate with other devices via a wired connection and / or a wireless connection. For example, the communication component 1400 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0299] The device 1400 may perform one or more of the operations or processes described herein. For example, a non-transitory computer-readable medium (such as the memory 1430) may store a set of instructions (such as one or more instructions or program codes) for execution by the processor 1420. The processor 1420 may execute the set of instructions to perform one or more of the operations or processes described herein. In some embodiments, execution of the set of instructions by the processor 1420 causes one or more of the processors 1420 and / or the device 1400 to perform one or more of the operations or processes described herein. In some embodiments, hardwired circuitry may be used in place of or in combination with the instructions to perform the operations or processes described herein. Additionally or alternatively, the processor 1420 may be configured to perform one or more of the operations or processes described herein. Accordingly, the embodiments described herein are not limited to any specific combination of hardwired circuitry or software.

[0300] Figure 14 The number and arrangement of components shown are provided as an example. The device 1400 may include additional components, fewer components, different components, or differently arranged components compared to those shown. Additionally or alternatively, a set of components (such as one or more components) of the device 1400 may perform one or more of the functions described as being performed by another set of components. Figure 14 compared to those shown. Additionally or alternatively, a set of components (such as one or more components) of the device 1400 may perform one or more of the functions described as being performed by another set of components.

[0301] Figure 15 is a flowchart of an example process 1500 for forming a semiconductor device described herein. In some embodiments, Figure 15 one or more process blocks of Figure 15 are performed using one or more semiconductor processing tools (such as one or more of the semiconductor processing tools 102 to 112). Additionally or alternatively,

[0302] such as Figure 15As shown, process 1500 may include forming a plurality of nanostructure layers (block 1510) on a semiconductor substrate of a semiconductor device in a direction perpendicular to the semiconductor substrate. For example, one or more semiconductor processing tools 102 to 112 may be used to form a plurality of nanostructure layers (such as layer stack 305) on the semiconductor substrate 205 of semiconductor device 200 in a direction perpendicular to semiconductor substrate 205. In some embodiments, the plurality of nanostructure layers include a plurality of sacrificial layers (such as first layer 310) and a plurality of channel layers (such as second layer 315) interleaved.

[0303] As Figure 15 As further shown, process 1500 may include etching the plurality of nanostructure layers and the semiconductor substrate to form a plurality of protrusion regions and a plurality of layer stacks on the plurality of protrusion regions (block 1520). For example, one or more semiconductor processing tools 102 to 112 may be used to etch the plurality of nanostructure layers and semiconductor substrate 205 to form a plurality of protrusion regions 210 and a plurality of layer stacks (such as portion 340 of layer stack 305) on the plurality of protrusion regions 210, as described herein. In some embodiments, the plurality of layer stacks include corresponding portions of the plurality of sacrificial layers and corresponding portions of the plurality of channel regions.

[0304] As Figure 15 As further shown, process 1500 may include forming STI regions and hybrid fin structures on the STI regions between adjacent layer stacks of the plurality of layer stacks (block 1530). For example, one or more semiconductor processing tools 102 to 112 may be used to form STI regions 215 and hybrid fin structures 620 on the STI regions 215 between adjacent layer stacks of the plurality of layer stacks, as described herein.

[0305] As Figure 15 As further shown, process 1500 may include forming dummy gate structures on the plurality of layer stacks and the hybrid fin structures (block 1540). For example, one or more semiconductor processing tools 102 to 112 may be used to form dummy gate structures 705 on the plurality of layer stacks and hybrid fin structures 620, as described herein.

[0306] As Figure 15 As further shown, process 1500 may include removing portions of the plurality of nanostructure layers to form one or more recesses adjacent to one or more sides of the dummy gate structure (block 1550). For example, one or more semiconductor processing tools 102 to 112 may be used to remove portions of the plurality of nanostructure layers to form one or more recesses (such as source / drain recesses 805) adjacent to one or more sides of the dummy gate structure, as described herein.

[0307] As Figure 15Further shown, process 1500 may include forming one or more source / drain regions (block 1560) within one or more recesses. For example, one or more semiconductor processing tools 102 to 112 may be used to form one or more source / drain regions 225 within one or more recesses as described herein. In some embodiments, the top surface of one of the hybrid fin structures 620 is at a height greater than the top surface of one of the source / drain regions 225 in the semiconductor device 200.

[0308] Process 1500 may include additional embodiments, such as a single embodiment or any combination of the processes described below or elsewhere herein.

[0309] In a first embodiment, process 1500 includes removing a portion of the dummy gate structure 705, a portion of the underlying stack of the dummy gate structure 705, and a portion of the lower protrusion region 210 of the stack to form an active region isolation recess 935 and forming an active region isolation structure 940 in the active region isolation recess 935.

[0310] In a second embodiment, alone or in combination with the first embodiment, removing a portion of the dummy gate structure 705, a portion of the stack, and a portion of the protrusion region 210 includes performing a first etch operation to remove a portion of the dummy gate structure 705 and performing a second etch operation after the first etch operation to remove the stack and a portion of the protrusion region 210.

[0311] In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 1500 includes performing a third etch operation before the first etch operation to remove the hard mask layer 905 on a portion of the dummy gate structure.

[0312] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the high-k layer 610 of a subset of the hybrid fin structures 620 is exposed in the active region isolation recess 935 after the first etch operation.

[0313] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the low-k layer (e.g., dielectric layer 610) of a subset of the hybrid fin structures 620 is exposed in the active region isolation recess 935 after the second etch operation.

[0314] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the active region isolation recess 935 extends under the bottom surface of the hybrid fin structures 620.

[0315] Even Figure 15 Showing the blocks of process 1500, in some embodiments, process 1500 includes with Figure 15Additional blocks, fewer blocks, or differently arranged blocks compared to those depicted. Additionally or alternatively, two or more blocks of process 1500 may be performed in parallel.

[0316] Figure 16 is a flow chart of an example process 1600 for forming a semiconductor device described herein. In some embodiments, Figure 16 one or more process blocks of are performed using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102 to 112). Additionally or alternatively, Figure 16 one or more process blocks of may be performed using components of one or more devices 1400, such as ports 1410, processor 1420, memory 1430, input components 1440, output components 1450, and / or communication components 1460.

[0317] As Figure 16 shown, process 1600 may include forming a plurality of nanostructure layers (block 1610) on a semiconductor substrate in a direction perpendicular to the semiconductor substrate. For example, one or more of semiconductor processing tools 102 to 112 may be used to form a plurality of nanostructure layers (e.g., layer stack 305) on semiconductor substrate 205 in a direction perpendicular to semiconductor substrate 205, as described herein. In some embodiments, the plurality of nanostructure layers includes a plurality of sacrificial layers (e.g., first layer 310) and a plurality of channel layers (e.g., second layer 315) interleaved.

[0318] As Figure 16 further shown, process 1600 may include forming a dummy gate structure (block 1620) on the plurality of nanostructures. For example, one or more of semiconductor processing tools 102 to 112 may be used to form a dummy gate structure 705 on the plurality of nanostructures, as described herein.

[0319] As Figure 16 further shown, process 1600 may include removing a plurality of portions of the plurality of nanostructures to form one or more recesses (block 1630) adjacent to one or more sides of the dummy gate structure. For example, one or more of semiconductor processing tools 102 to 112 may be used to remove a plurality of portions of the plurality of nanostructures to form one or more recesses (e.g., source / drain recesses 805) adjacent to one or more sides of dummy gate structure 705, as described herein.

[0320] As Figure 16 further shown, process 1600 may include forming one or more source / drain regions (block 1640) within the one or more recesses. For example, one or more of semiconductor processing tools 102 to 112 may be used to form one or more source / drain regions 225 within the one or more recesses.

[0321] As Figure 16 Further shown, process 1600 may include, after forming one or more source / drain regions, replacing a plurality of portions of the dummy gate structure and the sacrificial layer under the dummy gate structure with a metal gate structure (block 1650). For example, one or more semiconductor processing tools 102 to 112 may be used to replace a plurality of portions of the dummy gate structure 705 and the sacrificial layer under the dummy gate structure 705 with a metal gate structure (such as gate structure 240) after forming one or more source / drain regions 225, as described herein. In some embodiments, the metal gate structure surrounds at least four sides of the channel layer.

[0322] As Figure 16 Further shown, process 1600 may include forming an active region isolation recess after replacing a plurality of portions of the dummy gate structure and the sacrificial layer under the dummy gate structure with a metal gate structure, and removing a portion of the metal gate structure, a plurality of portions of the channel layers surrounded by the metal gate structure, a plurality of protrusion regions extending above the semiconductor substrate under the plurality of portions of the channel layers, and shallow trench isolation (STI) regions between the plurality of protrusion regions (block 1660). For example, one or more semiconductor processing tools 102 to 112 may be used to form an active region isolation recess 1145 after replacing a plurality of portions of the dummy gate structure 705 and the sacrificial layer under the dummy gate structure 705 with a metal gate structure, and remove a portion of the metal gate structure, a plurality of portions of the channel layers surrounded by the metal gate structure, a plurality of protrusion regions 210 extending above the semiconductor substrate 205 under the plurality of portions of the channel layers, and shallow trench isolation (STI) regions 215 between the plurality of protrusion regions 210, as described herein.

[0323] As Figure 16 Further shown, process 1600 may include forming an active region isolation structure within the active region isolation recess (block 1670). For example, one or more semiconductor processing tools 102 to 112 may be used to form an active region isolation structure 1115 within the active region isolation recess 1145, as described herein.

[0324] Process 1600 may include additional embodiments, such as a single embodiment or any combination related to the processes described below or elsewhere herein.

[0325] In a first embodiment, process 1600 includes removing a portion of the metal gate structure to form a gate isolation recess in the metal gate structure before removing a portion of the metal gate structure to form the active region isolation recess, and forming a gate isolation structure 1110 in the gate isolation recess before removing a portion of the metal gate structure to form the active region isolation recess 1145.

[0326] In a second embodiment, either alone or in combination with the first embodiment, removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, a plurality of protrusion regions 210, and the STI regions 215 includes removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, a plurality of protrusion regions 210, and the STI regions 215 according to the gate isolation structure 1110.

[0327] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, process 1600 includes removing other portions of a plurality of metal gate structures to form a plurality of gate isolation recesses in the metal gate structures before removing a portion of the metal gate structure to form the active region isolation recess 1145, and forming a plurality of gate isolation structures 1110 in the plurality of gate isolation recesses before removing a portion of the metal gate structure to form the active region isolation recess 1145.

[0328] In a fourth embodiment, either alone or in combination with one or more of the first to third embodiments, removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, a plurality of protrusion regions 210, and the STI regions 215 includes removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, a plurality of protrusion regions 210, and the STI regions 215 from between a plurality of gate isolation structures 1110.

[0329] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, forming the active region isolation structure includes forming a dielectric liner 1165 on sidewalls of a plurality of gate isolation structures 1110 in the active region isolation recess 1145, and filling the active region isolation recess with a dielectric layer 1170 on the dielectric liner 1165.

[0330] In a sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, forming a plurality of gate isolation structures 1110 includes forming a plurality of gate isolation structures 1110 such that the plurality of gate isolation structures 1110 extend in a first direction across the metal gate, wherein forming the active region isolation structure 1115 such that the active region isolation structure 1115 extends in a second direction along which the metal gate extends.

[0331] Even if Figure 16 showing blocks of process 1600, in some embodiments, process 1600 includes additional blocks, fewer blocks, or differently arranged blocks compared to that depicted in Figure 16 In addition or alternatively, two or more blocks of process 1600 may be performed in parallel.

[0332] In this way, the present disclosure describes a CPODE process in which one or more semiconductor device parameters are tuned to reduce the likelihood of etching into source / drain regions formed on the opposite side of a CPODE structure formed in a semiconductor device, to reduce the likelihood of deep loading in the semiconductor device and / or to reduce the likelihood of gate deformation, etc. Accordingly, the CPODE process of the present disclosure can reduce the likelihood of epitaxial damage to the source / drain regions, can reduce the leakage current between the source / drain, and / or can reduce the likelihood of transistor threshold voltage shift in the semiconductor device. The reduced likelihood of transistor threshold voltage shift in the semiconductor device can provide more consistent and / or faster switching speeds for the transistors, more consistent and / or lower power consumption, and / or improved semiconductor device performance, etc.

[0333] As detailed above, some embodiments described herein provide a method. The method includes forming a plurality of nanostructure layers on a semiconductor substrate of a semiconductor device in a direction perpendicular to the semiconductor substrate, wherein the nanostructure layers include a plurality of sacrificial layers and overlap with a plurality of channel layers; etching the nanostructure layers and the semiconductor substrate to form a plurality of protrusion regions and a plurality of layer stacks located in the protrusion regions, wherein the layer stacks include corresponding sacrificial layers and portions of the channel layers; forming a plurality of shallow trench isolation (STI) regions between adjacent layer stacks in the layer stacks and a plurality of hybrid fin structures located on the shallow trench isolation regions; forming a dummy gate structure on the layer stacks and the hybrid fin structures; removing a portion of the nanostructure layers to form one or more recesses adjacent to one or more sides of the dummy gate structure; and forming one or more source / drain regions in the one or more recesses, wherein the top surface of one of the hybrid fin structures is located at a height greater than that of one of the one or more source / drain regions in the semiconductor device.

[0334] In some embodiments, to form an active region isolation recess, a portion of the dummy gate structure, a portion of one of the layer stacks under the portion of the dummy gate structure, and a portion of one of the protrusion regions under the portion of the layer stacks are removed, and an active region isolation structure is formed in the active region isolation recess. In some embodiments, removing the portion of the dummy gate structure, the portion of the layer stack, and the portion of the protrusion region includes performing a first etching operation to remove the portion of the dummy gate structure, and after the first etching operation, performing a second etching operation to remove the portion of the layer stack and the portion of the protrusion region. In some embodiments, before performing the first etching operation, a third etching operation is performed to remove a hard mask layer on the portion of the dummy gate structure. In some embodiments, a plurality of high-k layers of a subset of the hybrid fin structures are exposed in the active region isolation recess after the first etching operation. In some embodiments, a plurality of low-k layers of a subset of the hybrid fin structures are exposed in the active region isolation recess after the second etching operation. In some embodiments, the active region isolation recess extends below the plurality of bottom surfaces of the hybrid fin structures.

[0335] As described in detail above, some embodiments described herein provide a method. The method includes forming a plurality of nanostructure layers on a semiconductor substrate in a direction perpendicular to the semiconductor substrate, wherein the nanostructure layer includes a sacrificial layer, overlapping with a plurality of channel layers, forming a dummy gate structure on the nanostructure layer, removing a portion of the nanostructure layer to form one or more recesses adjacent to one or more sides of the dummy gate structure, forming one or more source / drain regions in the one or more recesses, after forming the one or more source / drain regions, replacing the dummy gate structure and the portion of the sacrificial layer under the dummy gate structure with a metal gate structure, wherein the metal gate structure surrounds at least four sides of the channel layer, after replacing the dummy gate structure and the portion of the sacrificial layer under the dummy gate structure with a metal gate structure, to form an active region isolation recess, removing a portion of the metal gate structure, a plurality of portions of the channel layer surrounded by the metal gate structure, a plurality of protrusion regions extending above the semiconductor substrate under the portion of the channel layer, and a shallow trench isolation structure between the protrusion regions, and forming an active region isolation structure in the active region isolation recess.

[0336] In some embodiments, before removing a portion of the metal gate structure to form the active region isolation recess, another portion of the metal gate structure is removed to form a gate isolation recess in the metal gate structure and before removing a portion of the metal gate structure to form the active region isolation recess, a gate isolation structure is formed in the gate isolation recess. In some embodiments, removing a portion of the metal gate structure, a plurality of portions of the channel layer surrounded by the metal gate structure, the protrusion regions, and the shallow trench isolation structure includes removing a portion of the metal gate structure, a plurality of portions of the channel layer surrounded by the metal gate structure, the protrusion regions, and the shallow trench isolation structure according to the gate isolation structure. In some embodiments, before removing a portion of the metal gate structure to form the active region isolation recess, a plurality of other portions of the metal gate structure are removed to form a plurality of gate isolation recesses in the metal gate structure and before removing a portion of the metal gate structure to form the active region isolation recess, a plurality of gate isolation structures are formed in the gate isolation recesses. In some embodiments, removing a portion of the metal gate structure, a plurality of portions of the channel layer surrounded by the metal gate structure, the protrusion regions, and the shallow trench isolation structure includes removing a portion of the metal gate structure, a plurality of portions of the channel layer surrounded by the metal gate structure, the protrusion regions, and the shallow trench isolation structure from between the gate isolation structures. In some embodiments, a dielectric liner is formed on a plurality of sidewalls of the active region isolation structure in the active region isolation recess and the active region isolation recess is filled with a dielectric layer on the dielectric liner. In some embodiments, the gate isolation structure is formed such that the gate isolation structure extends across the metal gate in a first direction, wherein forming the active region isolation structure includes forming the active region isolation structure such that the active region isolation structure extends in a second direction along which the metal gate structure extends.

[0337] As detailed above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a semiconductor device including a plurality of first nanostructure channels located on a first protrusion region extending onto a semiconductor substrate, wherein the first nanostructure channels are arranged in a direction perpendicular to the semiconductor substrate, a plurality of second nanostructure channels located on a second protrusion region extending onto the semiconductor substrate, wherein the second nanostructure channels are arranged in a direction perpendicular to the semiconductor substrate, a first metal gate structure surrounding each first nanostructure channel, a second metal gate structure surrounding each second nanostructure channel, a gate isolation structure located between the first metal gate structure and the second metal gate structure, and an active region isolation structure located between the gate isolation structure and the second metal gate structure. Wherein the dielectric liner of the active region isolation structure is directly included on the sidewall of the gate isolation structure, and the bottom of the active region isolation structure includes a protrusion section extending into the semiconductor substrate and one or more shallow trench isolation sections located under the protrusion section.

[0338] In some embodiments, the semiconductor device includes a source / drain region adjacent to the first nanostructure channel and a hybrid fin structure, wherein the hybrid fin structure is located between the first nanostructure channel and the second nanostructure channel, and the top surface of the hybrid fin structure is at a height greater than the top surface of the source / drain region in the semiconductor device. In some embodiments, the first metal gate structure directly contacts the other sidewall of the gate isolation structure. In some embodiments, the semiconductor device includes another gate isolation structure located between the active region isolation structure and the second metal gate structure. In some embodiments, the second metal gate structure directly contacts the sidewall of the other gate isolation structure. In some embodiments, the dielectric liner of the active isolation structure directly contacts the other sidewall of the other gate isolation structure.

[0339] As used herein, depending on the context, "meeting a threshold" may mean a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, and so on.

[0340] The foregoing has outlined the features of several embodiments in order that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same purposes and / or obtaining the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, Comprising: A plurality of first nanostructure channels located on a first protrusion region extending onto a semiconductor substrate, wherein the plurality of first nanostructure channels are arranged in a direction perpendicular to the semiconductor substrate; A plurality of second nanostructure channels located on a second protrusion region extending onto the semiconductor substrate, wherein the plurality of second nanostructure channels are arranged in the direction perpendicular to the semiconductor substrate; A first metal gate structure surrounding each of the plurality of first nanostructure channels; A second metal gate structure surrounding each of the plurality of second nanostructure channels; A gate isolation structure located between the first metal gate structure and the second metal gate structure; And An active region isolation structure located between the gate isolation structure and the second metal gate structure, wherein a dielectric liner of the active region isolation structure is directly included on a sidewall of the gate isolation structure, and wherein a bottom of the active region isolation structure comprises: A protrusion section extending into the semiconductor substrate; and One or more shallow trench isolation sections located under the protrusion section.

2. The semiconductor device according to claim 1, characterized in that, Further comprising: A source / drain region adjacent to the plurality of first nanostructure channels; and A hybrid fin structure located between the plurality of first nanostructure channels and the plurality of second nanostructure channels, wherein a top surface of the hybrid fin structure is at a height greater than a top surface of the source / drain region in the semiconductor device.

3. The semiconductor device according to claim 1, wherein The first metal gate structure directly contacts the other sidewall of the gate isolation structure.

4. The semiconductor device according to claim 1, wherein, Further comprising: Another gate isolation structure located between the active region isolation structure and the second metal gate structure.

5. The semiconductor device according to claim 4, wherein, The second metal gate structure directly contacts a sidewall of the another gate isolation structure.

6. The semiconductor device according to claim 5, wherein, The dielectric liner of the active region isolation structure directly contacts the other sidewall of the another gate isolation structure.

7. A semiconductor device, characterized in that, Comprising: A plurality of first nanostructure channels located on a first protrusion region extending onto a semiconductor substrate, wherein the plurality of first nanostructure channels are arranged in a direction perpendicular to the semiconductor substrate; A plurality of second nanostructure channels located on a second protrusion region extending onto the semiconductor substrate, wherein the plurality of second nanostructure channels are arranged in the direction perpendicular to the semiconductor substrate; A source / drain region adjacent to the plurality of first nanostructure channels; A first metal gate structure surrounding each of the plurality of first nanostructure channels; A second metal gate structure surrounding each of the plurality of second nanostructure channels; A gate isolation structure located between the first metal gate structure and the second metal gate structure; And An active region isolation structure located between the gate isolation structure and the second metal gate structure, wherein a dielectric liner of the active region isolation structure is directly included on a sidewall of the gate isolation structure.

8. The semiconductor device according to claim 7, wherein, The first metal gate structure directly contacts the other sidewall of the gate isolation structure.

9. The semiconductor device according to claim 7, wherein, Further comprising: Another gate isolation structure located between the active region isolation structure and the second metal gate structure.

10. A semiconductor device, characterized in that, Comprising: A plurality of first nanostructure channels are located on a first convex region extending onto a semiconductor substrate, wherein the plurality of first nanostructure channels are arranged in a direction perpendicular to the semiconductor substrate; A plurality of second nanostructure channels are located on a second convex region extending onto the semiconductor substrate, wherein the plurality of second nanostructure channels are arranged in the direction perpendicular to the semiconductor substrate; A hybrid fin structure is located between the plurality of first nanostructure channels and the plurality of second nanostructure channels; A first metal gate structure surrounds each of the plurality of first nanostructure channels; A second metal gate structure surrounds each of the plurality of second nanostructure channels; A gate isolation structure is located between the first metal gate structure and the second metal gate structure; And An active region isolation structure is located between the gate isolation structure and the second metal gate structure, wherein a dielectric liner of the active region isolation structure is directly included on a sidewall of the gate isolation structure.

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