SiC VDMOSFET structure with high short circuit resistance
By designing parabolic trench and source trench structures in SiC VDMOSFETs, combining conductive columns and depletion layers, the electric field concentration problem of SiC VDMOSFETs during short circuits is solved, and the device's short-circuit resistance and reliability are improved.
Patent Information
- Application Number
- CN202421679137.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-16
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-07-16
AI Technical Summary
When the load is short-circuited, SiC VDMOSFET is prone to breakdown due to concentrated electric field strength, which is insufficient short-circuit bearing capacity, which affects its reliability and safe operation.
The design of parabolic trench with low middle sides high on both sides is combined with a structure of N+ region, P-base region and P+ region, adding source grooves and conductive columns to form a depletion layer to reduce electric field aggregation and reduce ohmic contact resistance.
Improves the short-circuit resistance of SiC VDMOSFETs, enhances the stability and reliability of the device, while reducing cell size and resistance.
Smart Images
Figure CN223157522U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of metal-oxide-semiconductor field-effect transistors, and more specifically discloses a SiC VDMOSFET structure with high short-circuit resistance ability. Background Art
[0002] With the rapid development of power electronics technology, silicon carbide power devices have become a promising technology, and there is an increasing interest in reducing energy consumption and operating at high switching frequencies.
[0003] Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has low switching losses, high switching frequencies, high breakdown voltages, and excellent temperature characteristics, which greatly reduces the performance requirements for heat sinks in high-power power electronics applications, resulting in a significant improvement in the conversion efficiency, power density, and stability of the entire power electronics device. However, short-circuit faults are one of the important reasons for the failure of SiC VDMOSFET, seriously hindering its application.
[0004] As a power switching device, the electric field intensity at the bottom corner of the U-shaped or concave-shaped trench of SiC VDMOS is large, and the electrical stress is concentrated, which easily causes reliability problems and even breakdown and device failure.
[0005] When the load is short-circuited, the device bears high-power short-circuit stress, and the weak short-circuit withstand ability poses new challenges to short-circuit protection technology, threatening the safe operation of SiC VDMOSFET. Summary of the Invention
[0006] The utility model provides a SiC VDMOSFET structure with high short-circuit resistance ability, which can solve the problems raised in the above background art.
[0007] To solve the above technical problems, according to one aspect of the present utility model, more specifically, a SiC VDMOSFET structure with high short-circuit resistance includes a source electrode, a gate electrode, and a drain electrode. The upper surface of the drain electrode is paved with an N+ substrate. The upper surface of the N+ substrate has a buffer layer. An N- drift region is epitaxially grown above the buffer layer. The upper surface of the N- drift region is concavely formed with a trench. The gate electrode is doped inside the trench. N+ regions are provided on both the left and right sides of the trench. A P- base region is provided below each N+ region. A P+ region is provided on the side of the N- drift region away from the trench, and the depth of the P+ region is greater than the depth of the P- base region, and the depth of the P+ region is equal to the depth of the trench. Source electrode grooves grounded are provided on both sides inside the N- drift region. P- doping is injected below the inside of the source electrode groove. A P- semiconductor is implanted on the inner side wall of the source electrode groove. A conductive column is provided above the P- doping inside the source electrode groove. The source electrode is horizontally paved above the N- drift region. An oxidation insulating layer is embedded inside the source electrode.
[0008] In some embodiments, preferably, the lower surface of the oxidation insulating layer contacts the gate electrode and above part of the N+ regions.
[0009] In some embodiments, preferably, the left and right sides of the lower surface of the source electrode bulge downward, and the bulging parts are triangular pyramids. The lower surface of the triangular pyramids is connected to the conductive column.
[0010] In some embodiments, preferably, the drain electrode is one of titanium nickel silver, aluminum silicon copper, and nickel palladium gold. The current direction of the SiC VDMOSFET is from the drain electrode upward and then out from the lead of the source electrode.
[0011] In some embodiments, preferably, the trench is in a parabolic shape with a lower middle and higher sides.
[0012] In some embodiments, preferably, the P- doping is made of silicon carbide material.
[0013] In some embodiments, preferably, the conductive column is surrounded by the P- semiconductor and the P- doping at the bottom.
[0014] In some embodiments, preferably, the electrons in the N+ region and the holes in the P- base region are combined to form a depletion layer at the interface between the N+ region and the P- base region.
[0015] The beneficial effect of the SiC VDMOSFET structure with high short-circuit resistance of the present utility model is as follows:
[0016] In the present utility model, the parabolic trench reduces the electric field concentration near the gate electrode.
[0017] The source electrode groove and the conductive column in the present utility model greatly reduce the source ohmic contact resistance of the device.
[0018] The source electrode groove in the present utility model increases the reliability of the device to a certain extent.
[0019] The structural layout of the present utility model greatly reduces the cell size of the device and at the same time increases the short-circuit tolerance of the device. Brief Description of the Drawings
[0020] The present utility model will be further described in detail below with reference to the drawings and specific implementation methods.
[0021] Figure 1 is a schematic structural diagram of the present utility model;
[0022] Figure 2 is a schematic structural diagram of the present utility model.
[0023] In the figure: 1. Source electrode; 2. Oxide insulating layer; 3. Gate electrode; 4. N+ region; 5. P- base region; 6. P+ region; 7. Groove; 8. Source electrode groove; 9. P- semiconductor; 10. Conductive column; 11. P- doping; 12. Drain electrode; 13. N+ substrate; 14. Buffer layer; 15. N- drift region. Specific Embodiments
[0024] The present utility model will be described in detail below with reference to the drawings and embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0025] According to the appendix Figure 1-2, a SiC VDMOSFET structure with high short - circuit resistance is provided, including a source 1, a gate 3, and a drain 12. The upper surface of the drain 12 is tiled with an N+ substrate 13. There is a buffer layer 14 on the upper surface of the N+ substrate 13. An N - drift region 15 is epitaxially grown above the buffer layer 14. A groove 7 is formed in a concave shape on the upper surface of the N - drift region 15. The gate 3 is doped inside the groove 7. N+ regions 4 are provided on the left and right sides of the groove 7. A P - base region 5 is arranged below each N+ region 4. A P+ region 6 is arranged on the side of the N - drift region 15 far from the groove 7, which can improve the robustness of the SiC VDMOSFET structure. At the position far from the groove 7, the threshold voltage of the P+ region 6 rises sharply; and the depth of the P+ region 6 is greater than the depth of the P - base region 5, which can reduce the electric field at the corner of the groove 7; and the depth of the P+ region 6 is equal to the depth of the groove 7. Source trenches 8 grounded are arranged on both sides inside the N - drift region 15. P - doping 11 is injected below the inside of the source trench 8. A P - semiconductor 9 is implanted on the inner side wall of the source trench 8. A conductive column 10 is arranged above the P - doping 11 inside the source trench 8; there are source trenches 8 on both sides of the groove 7 of the gate 3. However, there is a grounded source trench 8 on both sides of each groove 7, and its extension depth into the N - drift region 15 is greater than the depth of the groove 7, which can better protect the oxide insulation layer and reduce the gate 3 resistance; the source 1 is horizontally tiled above the N - drift region 15, and an oxide insulation layer 2 is embedded inside the source 1.
[0026] In this embodiment, the designed SiC VDMOSFET structure improves the on - resistance of the device, reduces the electric - field concentration problem, improves the gate stability, thereby enhancing the overall reliability of the device and enabling the device to have short - circuit resistance.
[0027] Specifically, the lower surface of the oxide insulation layer 2 contacts the gate 3 and the upper part of some N+ regions 4, and the thickness of the oxide insulation layer 2 is 3 - 5μm.
[0028] Specifically, the left and right sides of the lower surface of the source 1 bulge downward, and the bulging part is a triangular pyramid. The lower surface of the triangular pyramid is connected to the conductive column 10. The conductive column 10 is beneficial to improving the conductivity of the SiC VDMOSFET device, and the material of the conductive column 10 is graphene.
[0029] Specifically, the drain 12 is one of titanium - nickel - silver, aluminum - silicon - copper, and nickel - palladium - gold. The current direction of the SiC VDMOSFET is from the drain 12 upward and then out from the lead of the source 1.
[0030] Specifically, the groove 7 is in a parabolic shape with a lower middle and higher sides, which can relieve the electric - field concentration problem at the corner of the traditional groove 7 and prevent the SiC VDMOSFET structure from being broken down.
[0031] Specifically, the P-doping 11 is made of silicon carbide.
[0032] Specifically, the conductive column 10 is surrounded by the P-semiconductor 9 and the P-doping 11 at the bottom.
[0033] Specifically, the electrons in the N+ region 4 and the holes in the P-base region 5 are combined, and a depletion layer is formed at the interface between the N+ region 4 and the P-base region 5. The concentrations of semiconductor holes and electrons in the P-base region 5 and the N+ region 4 are different, and their respective majority carriers begin to diffuse. As a result, a space charge region is formed between the two semiconductors, and a built-in electric field pointing from the n-region to the p-region is formed and continuously strengthened. As a result, the drift effect on the carriers is strengthened, and finally a dynamic equilibrium state is reached. At this time, there is neither diffusion current nor drift current in the space charge region, and the depletion layer is formed.
[0034] The working principle of the present utility model is as follows:
[0035] Designing the trench 7 into a parabola shape with an upward opening can effectively reduce the aggregation of the electric field and improve the stability of the device;
[0036] By designing the P+ injection region as shown in the figure, when the device is turned off, the depletion layer generated by the P+ region 6 can quickly wrap the gate 3, reduce the electric field strength at the gate oxide when the device is blocked, and improve the reliability of the device.
[0037] Increase of the source electrode groove: It blocks the lateral diffusion of carriers in the drift region, improves the reliability of the device; increases the area of ohmic contact, and due to the internal graphene conductive column, greatly reduces the influence of the source electrode ohmic contact on the device resistance.
[0038] As shown in the structural layout in the figure, it can greatly reduce the cell size of the device, almost double the current density of the device, and increase the short-circuit withstand ability.
[0039] All electrical components mentioned in this article are electrical components existing in reality.
[0040] Of course, the above description is not a limitation to the present utility model, and the present utility model is not limited to the above examples. Changes, modifications, additions or substitutions made by those of ordinary skill in the art within the essence of the present utility model also belong to the protection scope of the present utility model.
Claims
1. SiC VDMOSFET structure with high short-circuit resistance, comprising a source electrode (1), a gate electrode (3) and a drain electrode (12), characterized in that: The upper surface of the drain (12) is covered with an N+ substrate (13). The upper surface of the N+ substrate (13) has a buffer layer (14). An N- drift region (15) is epitaxially grown above the buffer layer (14). A groove (7) is formed in a concave shape on the upper surface of the N- drift region (15). The gate (3) is doped inside the groove (7). N+ regions (4) are provided on the left and right sides of the groove (7). A P- base region (5) is provided below each N+ region (4). A P+ region (6) is provided on the side of the N- drift region (15) away from the groove (7). The depth of the P+ region (6) is greater than that of the P- base region (5), and the depth of the P+ region (6) is equal to the depth of the groove (7). Source trenches (8) grounded are provided on both sides inside the N- drift region (15). P- doping (11) is injected below the inside of the source trenches (8). A P- semiconductor (9) is implanted on the inner sidewall of the source trenches (8). A conductive column (10) is provided inside the source trenches (8) and above the P- doping (11). The source (1) is horizontally laid above the N- drift region (15). An oxide insulating layer (2) is embedded inside the source (1).
2. The SiC VDMOSFET structure with high short-circuit resistance according to claim 1, characterized in that: The lower surface of the oxide insulating layer (2) is in contact with the gate (3) and above part of the N+ regions (4).
3. The SiC VDMOSFET structure with high short-circuit resistance according to claim 1, characterized in that: The left and right sides of the lower surface of the source (1) protrude downward, and the protruding parts are triangular pyramids. The lower surface of the triangular pyramids is connected to the conductive columns (10).
4. The SiC VDMOSFET structure with high short - circuit resistance according to claim 1, characterized in that: The drain (12) is one of titanium nickel silver, aluminum silicon copper, and nickel palladium gold. The current direction of the SiC VDMOSFET is from the drain (12) upward and then out from the lead of the source (1).
5. The SiC VDMOSFET structure with high short-circuit resistance according to claim 1, characterized in that: The groove (7) is in a parabolic shape with a lower middle and higher sides.
6. The SiC VDMOSFET structure with high short-circuit resistance according to claim 1, characterized in that: The P- doping (11) is made of silicon carbide material.
7. The SiC VDMOSFET structure with high short - circuit resistance according to claim 1, characterized in that: The conductive column (10) is surrounded by the P- semiconductor (9) and the P- doping (11) at the bottom.
8. The SiC VDMOSFET structure with high short-circuit resistance according to claim 1, characterized in that: The electrons in the N+ regions (4) are combined with the holes in the P- base regions (5), and a depletion layer is formed at the interface between the N+ regions (4) and the P- base regions (5).