NAND wiring segment impedance structure

Abstract

The utility model discloses an NAND wiring segment impedance structure, which comprises an SOC chip, an NAND particle and an NAND bus connected between the SOC chip and the NAND particle, the NAND particle comprises a plurality of crystal grains, the NAND bus comprises a first segment of wiring and a second segment of wiring, the first segment of wiring is respectively connected with the SOC chip and the second segment of wiring, the second segment of wiring is respectively connected with the first segment of wiring and the NAND particle, and the first segment of wiring is connected with the NAND particle. And the impedance of the first section of wire is greater than that of the second section of wire. According to the utility model, the impedance of the first section of wiring is designed to be greater than that of the second section of wiring, so that the allowance in the reading direction is increased, the allowance in the writing direction is reduced, the reading and writing performance is more balanced, the system bottleneck caused by the reading and writing performance difference is reduced, the user experience and satisfaction are improved, impedance matching is facilitated before a signal enters an NAND bus, and the signal transmission efficiency is improved. And signal reflection and attenuation are reduced, so that signal integrity is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of solid state drives, in particular to a segmented impedance structure for NAND traces. Background Art

[0002] In the design of solid state drives (SSDs), with the continuous progress of NAND Flash technology and the continuous increase in the rate and number of grains of NAND particles, higher requirements are put forward for the performance of the NAND bus. Especially in the design of high-density SSDs, such as when using high-capacity, double-sided ODP (Over-Drive Performance) particles, the SOC needs to manage up to 8 or more grains simultaneously, which greatly challenges the signal integrity and transmission efficiency of the NAND bus.

[0003] Traditional NAND buses often use a single impedance value for global control, which can meet the requirements in point-to-point or low-load scenarios. However, in the design of SSDs with multiple grains and high loads, due to the complexity of the physical layout between grains and the signal transmission path, the margin differences in the read and write directions of the traditional impedance control method are relatively large. Especially in long-distance and high-density traces, the stub effect is significantly enhanced, resulting in frequent problems such as signal attenuation and reflection, seriously reducing the performance of the NAND bus. Summary of the Utility Model

[0004] The purpose of the utility model is to overcome the deficiencies of the prior art and provide a segmented impedance structure for NAND traces, so as to solve the problem that traditional NAND buses often use a single impedance value for global control. In the design of SSDs with multiple grains and high loads, due to the complexity of the physical layout between grains and the signal transmission path, the traditional impedance control method is unable to cope, especially in long-distance and high-density traces, the stub effect is significantly enhanced, resulting in frequent problems such as signal attenuation and reflection, seriously reducing the performance of the NAND bus.

[0005] To achieve the above purpose, the utility model adopts the following technical solutions:

[0006] An embodiment of the utility model provides a segmented impedance structure for NAND traces, which includes: an SOC chip, NAND particles, and a NAND bus connected between the SOC chip and the NAND particles. The NAND particles include multiple grains. The NAND bus includes a first segment of trace and a second segment of trace. The first segment of trace is respectively connected to the SOC chip and the second segment of trace. The second segment of trace is respectively connected to the first segment of trace and the NAND particles. The impedance of the first segment of trace is greater than the impedance of the second segment of trace.

[0007] Among them, the impedance of the first section of the trace is greater than or equal to 50 Ω and less than or equal to 60 Ω.

[0008] Among them, the impedance of the second section of the trace is greater than or equal to 30 Ω and less than or equal to 40 Ω.

[0009] Among them, the impedance difference between the first section of the trace and the second section of the trace is 10 Ω.

[0010] Among them, the impedance of the first section of the trace is 50 Ω, and the impedance of the second section of the trace is 40 Ω.

[0011] Among them, the second section of the trace includes: a third section of the trace, a fourth section of the trace, and a fifth section of the trace. The third section of the trace is respectively connected to the first section of the trace and the fourth section of the trace. The fifth section of the trace is respectively connected to the fourth section of the trace and the NAND chip. The first section of the trace, the third section of the trace, the fourth section of the trace, and the fifth section of the trace are connected in sequence and the impedance decreases in a stepped manner.

[0012] Among them, the impedance of the third section of the trace is 45 Ω.

[0013] Among them, the impedance of the fourth section of the trace is 40 Ω.

[0014] Among them, the impedance of the fifth section of the trace is 35 Ω.

[0015] Compared with the prior art, the NAND trace segmented impedance structure of the present utility model designs the impedance of the first section of the trace to be greater than that of the second section of the trace, so that the margin in the read direction is increased and the margin in the write direction is reduced, making the read and write performance more balanced, reducing the system bottleneck caused by the difference in read and write performance, improving the user experience and satisfaction, and helping to perform impedance matching before the signal enters the NAND bus, reducing signal reflection and attenuation, thereby improving signal integrity.

[0016] The above description is only an overview of the technical solution of the present utility model. In order to be able to understand the technical means of the present utility model more clearly, it can be implemented according to the content of the description. And in order to make the above and other purposes, features and advantages of the present utility model more obvious and understandable, the following preferred embodiments are specifically described in detail as follows. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0018] Figure 1This is a schematic diagram of a segmented impedance structure for NAND traces of the present utility model;

[0019] Figure 2 This is an analysis diagram of the simulation effect of a segmented impedance structure for NAND traces of the present utility model in the write direction;

[0020] Figure 3 This is an analysis diagram of the simulation effect of a segmented impedance structure for NAND traces of the present utility model in the read direction;

[0021] Explanation of the markings in the figure:

[0022] 1. SOC chip; 20. First-segment trace; 30. Second-segment trace; 40. NAND flash memory chip; 41. Die. Specific embodiments

[0023] In order to make the objectives, technical solutions and advantages of the present utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0025] In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present utility model.

[0026] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, "a plurality" means two or more unless otherwise specifically defined.

[0027] In this utility model, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. For those skilled in the art, the specific meanings of the above terms in this utility model can be understood according to specific circumstances.

[0028] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0029] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0030] As SSD product speeds continue to increase, the number of NAND chips within a device continues to grow, placing increasing demands on NAND bus performance. This is especially true in applications with multiple NAND chips and a high number of chips, where read and write margins vary significantly. This results in unbalanced read and write performance. This balance not only directly impacts data access speed but also the stability and reliability of the entire system, a challenge faced by existing technologies. To address this, the inventors have proposed an improved solution for balancing read and write margins, which is detailed in the following embodiments.

[0031] See also Figures 1 to 3, an embodiment of the present invention discloses a NAND trace segmented impedance structure, which includes: an embodiment of the present invention provides a NAND trace segmented impedance structure, which includes: a SOC chip 10, a NAND particle 40, and a NAND bus connected between the SOC chip 10 and the NAND particle 40, the NAND particle 40 includes a plurality of grains 41, the NAND bus includes a first trace segment 20 and a second trace segment 30, the first trace segment 20 is respectively connected to the SOC chip 10 and the second trace segment 30, the second trace segment 30 is respectively connected to the first trace segment 20 and the NAND particle 40, and the impedance of the first trace segment 20 is greater than the impedance of the second trace segment 30.

[0032] It can be understood that in this embodiment, by designing the impedance of the first section of the trace 20 to be greater than that of the second section of the trace 30, the electrical characteristics of the read and write operations are specifically adjusted without affecting the overall signal transmission quality. During the read operation, the larger impedance can provide a more stable signal, increase the margin in the read direction, and thus improve the accuracy and stability of the read data; and during the write operation, although the impedance reduction may cause a reduction in the signal margin, since the write operation usually has a higher tolerance for signal quality, this design can still ensure effective data writing. In high-speed signal transmission, since the first section of the trace 20 adopts a higher impedance design, it can suppress the reflection of the signal during the transmission process to a certain extent, reduce signal loss and interference, and improve signal integrity.

[0033] Furthermore, the impedance of the first trace 20 is greater than or equal to 50Ω and less than or equal to 60Ω.

[0034] Furthermore, the impedance of the second trace 30 is greater than or equal to 30Ω and less than or equal to 40Ω.

[0035] Furthermore, the impedance difference between the first section of the trace 20 and the second section of the trace 30 is 10Ω.

[0036] Preferably, the impedance of the first section of the trace 20 is 50Ω, and the impedance of the second section of the trace 30 is 40Ω.

[0037] As can be understood, this embodiment achieves balanced read and write performance and optimized signal transmission by precisely controlling the impedance values and their difference between the first and second trace segments 20 and 30. Specifically, the 50Ω impedance of the first trace segment 20 provides a stable signal environment for read operations, while the 40Ω impedance of the second trace segment 30 facilitates smooth write operations. Furthermore, the 10Ω impedance difference ensures signal stability and reliability during transmission, reducing the risk of signal reflections and crosstalk. This not only improves the performance of the NAND storage system but also reduces subsequent maintenance and upgrade costs.

[0038] likeFigure 2 and Figure 3 as shown Figure 2 is the simulation effect analysis diagram of the write direction of this application at a transmission rate of 1600 MHz, Figure 3 is the simulation effect analysis diagram of the read direction of this application at a transmission rate of 1600 MHz. As can be seen from Figure 2 and Figure 3 it can be seen that at a transmission rate of 1600 MHz, the differences between the high voltage and the standard interval (VIH Delta) in the read direction and the write direction of this application are 135 mV and 136 mV respectively, and the differences between the low voltage and the standard interval (VIL Delta) are 140 mV and 139 mV respectively. It can be seen from this that the read-write direction margins of this application are similar at a transmission rate of 1600 MHz, achieving balanced read-write performance.

[0039] Further, the second section of the trace 30 includes: the third section of the trace, the fourth section of the trace, and the fifth section of the trace. The third section of the trace is respectively connected to the first section of the trace 20 and the fourth section of the trace, and the fifth section of the trace is respectively connected to the fourth section of the trace and the NAND chip 40. The first section of the trace 20, the third section of the trace, the fourth section of the trace, and the fifth section of the trace are connected in sequence and the impedance decreases in a stepped manner.

[0040] Among them, the impedance of the third section of the trace is 45 Ω.

[0041] Among them, the impedance of the fourth section of the trace is 40 Ω.

[0042] Among them, the impedance of the fifth section of the trace is 35 Ω.

[0043] In this embodiment, the first section of the trace 20 (50 Ω), the third section of the trace (45 Ω), the fourth section of the trace (40 Ω), and the fifth section of the trace (35 Ω) are connected in sequence, and the impedance decreases in a stepped manner. This design not only optimizes the signal transmission path, but also reduces signal reflection and attenuation by gradually reducing the impedance, thereby improving the integrity and stability of signal transmission.

[0044] Compared with the prior art, the NAND trace segmented impedance structure of the present utility model makes the margin in the read direction increase and the margin in the write direction decrease by designing the impedance of the first section of the trace to be greater than that of the second section of the trace, making the read-write performance more balanced, reducing the system bottleneck caused by the read-write performance difference, improving the user experience and satisfaction, and helping to perform impedance matching before the signal enters the NAND bus, reducing signal reflection and attenuation, thereby improving signal integrity.

[0045] The above are only specific embodiments of the present utility model, but the protection scope of the present utility model is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present utility model can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model shall be subject to the protection scope of the claims.

Claims

1. A segmented impedance structure for NAND traces, characterized in that Comprising: An SOC chip, NAND flash memory chips, and a NAND bus connected between the SOC chip and the NAND flash memory chips. The NAND flash memory chips include a plurality of die. The NAND bus includes a first-section trace and a second-section trace. The first-section trace is respectively connected to the SOC chip and the second-section trace. The second-section trace is respectively connected to the first-section trace and the NAND flash memory chips. The impedance of the first-section trace is greater than the impedance of the second-section trace.

2. A NAND trace segmented impedance structure according to claim 1, characterized in that: The impedance of the first-section trace is greater than or equal to 50 Ω and less than or equal to 60 Ω.

3. The NAND trace segmented impedance structure according to claim 1, characterized in that The impedance of the second-section trace is greater than or equal to 30 Ω and less than or equal to 40 Ω.

4. The NAND trace segmented impedance structure according to claim 1, wherein: The impedance difference between the first-section trace and the second-section trace is 10 Ω.

5. The NAND trace segmented impedance structure according to claim 1, wherein: The impedance of the first-section trace is 50 Ω, and the impedance of the second-section trace is 40 Ω.

6. A segmented impedance structure of NAND traces according to claim 1, characterized in that, The second-section trace includes a third-section trace, a fourth-section trace, and a fifth-section trace. The third-section trace is respectively connected to the first-section trace and the fourth-section trace. The fifth-section trace is respectively connected to the fourth-section trace and the NAND flash memory chips. The first-section trace, the third-section trace, the fourth-section trace, and the fifth-section trace are connected in sequence and the impedance decreases in a stepped manner.

7. A NAND trace segmented impedance structure according to claim 6, characterized in that, The impedance of the third-section trace is 45 Ω.

8. A NAND trace segmented impedance structure according to claim 7, characterized in that: The impedance of the fourth-section trace is 40 Ω.

9. The NAND trace segmented impedance structure according to claim 8, wherein The impedance of the fifth-section trace is 35 Ω.

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