Xintf bus interface controller based on FPGA

Abstract

The utility model discloses an FPGA-based Xintf bus interface controller, which comprises a dual-port RAM module, a DSP chip assembly, an FPGA chip, an Xintf interface control line management module, an Xintf interface data writing management module and an Xintf interface data reading management module, the FPGA chip is connected with the Xintf interface control line management module, the FPGA chip is connected with a daughter card through an Xintf bus, and the daughter card is connected with the DSP chip assembly. The FPGA chip is used for releasing the daughter card bus to the authorized DSP chip according to the authority state of the DSP chip assembly to realize daughter card conduction connection; the system has the advantages of being high in flexibility, expandability, reconfigurability and parallel processing capacity, function expansion can be conducted on the Xintf asynchronous bus of the DSP chip through the FPGA chip, access control over external expansion chips of various function types is achieved, diversification of external expansion interface access is achieved, function expansion of external expansion chip access control logic is achieved through the FPGA, and the system is convenient to use. And the method has higher flexibility and expandability.

Description

Technical Field

[0001] The utility model relates to the technical field of Xintf bus interface controllers, and particularly relates to an Xintf bus interface controller based on FPGA. Background Technique

[0002] With the diversified and complex development of the functions of application devices in the aerospace field, while the performance requirements for the operating frequency, number of cores, computing power, etc. of the processor are getting higher and higher, the types of peripheral interfaces and peripheral devices are in increasing demand, especially in the case of applying the DSP28335 processor in the control field.

[0003] Although the DSP processor has a variety of built-in basic peripherals, such as ADC, SCI, SPI, etc., under the application background of dual-redundancy control, large data storage, high-precision acquisition, and complex bus communication, it is necessary to externally expand SRAM, Flash, ADC, MIL-1394 communication, and the bus permission control logic processing between dual redundancies for the DSP processor. At the same time, to meet the requirements of the device information response time, a parallel interface is required to implement the information access of the externally expanded chips. Although the DSP28335 has a built-in Xintf asynchronous bus (parallel interface), relying solely on the Xintf bus of the DSP to achieve the above functional requirements has problems such as complex external circuit design, low reliability, and low operating efficiency. Content of the Utility Model

[0004] The purpose of the utility model is to provide an Xintf bus interface controller based on FPGA to solve the problems of complex circuit, low reliability, and low operating efficiency proposed in the above background technique.

[0005] To achieve the above purpose, the utility model provides the following technical solutions:

[0006] An Xintf bus interface controller based on FPGA includes a dual-port RAM module, a DSP chip component, an FPGA chip, an Xintf interface control line management module, an Xintf interface write data management module, and an Xintf interface read data management module; the DSP chip component and the FPGA chip are connected to each other through a parallel asynchronous bus, the FPGA chip is connected to the Xintf interface control line management module, and the FPGA chip is connected to a daughter card through the Xintf bus;

[0007] The output end of the DSP chip component is connected to externally expanded chips such as AD, RAM, and Flash. The daughter card is accessed by the bus of the DSP chip component, and AD, RAM, and Flash are all accessed by one-to-one buses; the FPGA chip is used to release the daughter card bus to the DSP chip with permission according to the permission state of the DSP chip component to realize the conduction connection of the daughter card;

[0008] The Xintf interface control line management module controls the operations of the DSP chip component, the FPGA chip, the Xintf interface read data management module, and the Xintf interface write data management module respectively. The Xintf interface read data management module is used to control the DSP chip component to read data signals and write them into the dual-port RAM module, and the Xintf interface write data management module is used to control the DSP data information of the DSP chip component to be written into the dual-port RAM module.

[0009] Furthermore, the DSP chip component includes a first DSP chip and a second DSP chip. The Xintf buses of the first DSP chip and the second DSP chip are both connected to the AD, RAM, Flash, and FPGA chips. The Xintf bus includes a data bus, an address bus, a read control signal, a write control signal, and a chip select signal.

[0010] Furthermore, the daughter card uses a MIL-1394 daughter card, which is separately connected to the FPGA chip and is interconnected with the DSP chip bus with control authority through the internal logic of the FPGA chip.

[0011] Furthermore, the chip select signals of the externally expanded chips AD, RAM, Flash, and the daughter card are all controlled by the FPGA chip.

[0012] The beneficial effects of the present utility model are as follows:

[0013] 1. The present utility model has the characteristics of high flexibility, scalability, reconfigurability, and strong parallel processing ability. It can expand the functions of the Xintf asynchronous bus of the DSP chip through the FPGA chip, realize the access control of various types of externally expanded chips, expand the functional requirements of various peripherals, realize the diversification of external expansion interface access, and the access control logic of the externally expanded chips is realized by the FPGA to expand functions, with higher flexibility and scalability. It can continuously increase the types and quantities of peripheral chips according to the application requirements of the device, only need to make adaptive adjustments to the FPGA software, reduce costs and the risks of technology development and application, improve the processing efficiency of bus data through the dual-port RAM, and is conducive to the popularization and use of the Xintf bus interface controller based on the FPGA.

[0014] 2. The present utility model has the characteristics of simple and reliable circuits. The main functions are realized by the FPGA chip, and the logic control can be adjusted according to the actual application requirements, with high flexibility, configurability, and portability, which has reference significance for the bus expansion of other types of processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a principle block diagram of the signal cross-linking of the Xintf bus interface controller of the present utility model;

[0016] Figure 2 This is the principle block diagram of the Xintf bus interface controller of the present utility model.

[0017] In the figure: 1 Xintf interface control line management module, 2 Xintf interface write data management module, 3 Xintf interface read data management module, 4 dual-port RAM module, 5 first DSP chip, 6 second DSP chip, 7 FPGA chip, 8 daughter card. Detailed implementation manners

[0018] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.

[0019] Please refer to Figure 1-2 , which provides a technical solution for the present utility model. An Xintf bus interface controller based on FPGA includes a dual-port RAM module 4, a DSP chip component, an FPGA chip 7, an Xintf interface control line management module 1, an Xintf interface write data management module 2, and an Xintf interface read data management module 3; the DSP chip component is interconnected with the FPGA chip 7 through a parallel asynchronous bus, the FPGA chip 7 is connected to the Xintf interface control line management module 1, and the FPGA chip 7 is connected to a daughter card 8 through the Xintf bus; wherein, the parallel asynchronous bus includes a data bus XD, an address bus XA, a read control signal / RD, a write control signal / WR, and a chip select control signal / CS.

[0020] It should be noted that the output end of the DSP chip component is connected to external expansion chips such as AD, RAM, and Flash. The daughter card 8 is accessed by the bus of the DSP chip component, and AD, RAM, and Flash are all accessed by one-to-one buses. The FPGA chip 7 is used to release the bus of the daughter card 8 to the DSP chip with permissions according to the permission status of the DSP chip component to realize the conduction connection of the daughter card 8. The chip select signals of the external expansion chips AD, RAM, Flash, and the daughter card are all controlled by the FPGA chip 7. The mentioned DSP chip component includes a first DSP chip 5 and a second DSP chip 6. The Xintf buses of the first DSP chip 5 and the second DSP chip 6 are all connected to AD, RAM, Flash, and the FPGA chip 7. The Xintf bus includes a data bus, an address bus, a read control signal, a write control signal, and a chip select signal. Among them, the logical timing control of the first DSP chip 5 and the second DSP chip 6 is realized by the FPGA chip 7, mainly including the address division control of the external expansion space, the chip select access enable control, and the bus access permission switching control. Among them, the first DSP chip 5 and the second DSP chip 6 adopt, but are not limited to, the DSP-28335 type processor.

[0021] In this embodiment, the mentioned Xintf interface control line management module 1 controls the operations of the DSP chip component, the FPGA chip 7, the Xintf interface read data management module 3, and the Xintf interface write data management module 2 respectively. The Xintf interface read data management module 3 is used to control the DSP chip component to read data signals and write them into the dual-port RAM module 4, and the Xintf interface write data management module 2 is used to control the DSP data information of the DSP chip component to be written into the dual-port RAM module 4.

[0022] In this embodiment, the daughter card 8 adopts a MIL-1394 daughter card. The daughter card 8 is separately connected to the FPGA chip 7 and is interconnected with the bus of the DSP chip with control permissions through the internal logic of the FPGA chip 7.

[0023] The Xintf bus interface controller based on FPGA. The mentioned Xintf interface control line management module 1 realizes the bus control logic of FPGA, Flash, RAM, AD, and MIL-1394 according to the external Xintf bus access address situation of the FPGA chip 7. The specific logic is as follows: perform two-level cache synchronization processing on the externally input chip select, read, and write signals; perform enable control on each externally expanded chip according to the chip select signal; when it is determined to access AD, RAM, or Flash, the FPGA chip 7 releases the bus authority to the first DSP chip 5, the second DSP chip 6, and the peripheral chips Flash, RAM, and AD; when it is determined to access the FPGA chip 7, the FPGA chip 7 obtains the bus response authority; when it is determined to access the MIL-1394 daughter card, the FPGA chip 7 releases the MIL-1394 daughter card bus to the DSP chip component with control authority according to the authority status of the first DSP chip 5 and the second DSP chip 6, realizing single access to the MIL-1394 daughter card.

[0024] Among them, the mentioned Xintf interface read data management module 3: for the input read signal, identify the rising edge, generate a write enable B single-pulse signal as the enable signal, and control the DSP chip component to read data information and write it into the dual-port RAM module 4; if the enable B signal is valid, assign the relevant data register to the variable RAMB data according to the Xintf bus interface address and store it in the Xintf-RAM, including but not limited to AD data and communication data.

[0025] Among them, the mentioned Xintf interface write data management module 2: for the RAMA data write enable signal, identify the rising edge, generate an XintfRam_WEA single-pulse signal as the enable signal, and control the DSP data information to be written into the dual-port RAMA; and generate an XintfRam_RDA read signal with a delay of two clock cycles to control the FPGA to read the data written by the DSP into the Xintf-RAM; if the XintfRam_RDA read enable signal is valid, read the relevant data from the Xintf-RAMA according to the Xintf bus interface address; The dual-port RAM module 4 of the Xintf interface: uses the FIFO Generator IP core, dual-port RAM type, 16-bit wide data, and 1024 depth.

[0026] In summary, the Xintf bus interface controller based on FPGA has the characteristics of simple and reliable circuit. Its main functions are implemented by the FPGA chip, and the logic control can be adjusted according to actual application requirements. It has high flexibility, configurability and portability, and has reference significance for the bus expansion of other types of processors. By flexibly allocating the access address space of the DSP bus, the functional requirements of expanding multiple peripherals are realized. At the same time, through the dual-port RAM, the processing efficiency of the bus data is improved. In terms of hardware, mainly peripheral chips such as DSP and FPGA are interconnected through an asynchronous bus, and the logic and timing control are carried out through the FPGA software to realize the functional expansion of the DSP asynchronous bus.

[0027] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0028] The above embodiments only represent the preferred implementation modes of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. In the present invention, unless otherwise clearly defined and limited, terms such as "installation", "connection", "connection", "fixation" and other terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. Among them, there are various detachable installation methods. For example, it can be through the cooperation of plugging and buckling, or through the way of bolt connection, etc.

[0029] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An Xintf bus interface controller based on FPGA, characterized in that: It includes a dual-port RAM module, a DSP chip component, an FPGA chip, an Xintf interface control line management module, an Xintf interface write data management module, and an Xintf interface read data management module; the DSP chip component and the FPGA chip are interconnected through a parallel asynchronous bus, the FPGA chip is connected to the Xintf interface control line management module, and the FPGA chip is connected to a daughter card through the Xintf bus; The output end of the DSP chip component is connected with external expansion chips such as AD, RAM, and Flash. The daughter card is accessed by the bus of the DSP chip component, and AD, RAM, and Flash are all accessed by one-to-one buses; the FPGA chip is used to release the daughter card bus to the DSP chip with permission according to the permission status of the DSP chip component to realize the conduction connection of the daughter card; The Xintf interface control line management module controls the operation of the DSP chip component, the FPGA chip, the Xintf interface read data management module, and the Xintf interface write data management module respectively. The Xintf interface read data management module is used to control the DSP chip component to read data signals and write them into the dual-port RAM module, and the Xintf interface write data management module is used to control the DSP data information of the DSP chip component to be written into the dual-port RAM module.

2. The Xintf bus interface controller based on FPGA according to claim 1, wherein: The DSP chip component includes a first DSP chip and a second DSP chip. The Xintf buses of the first DSP chip and the second DSP chip are all connected to AD, RAM, Flash, and the FPGA chip. The Xintf bus includes a data bus, an address bus, a read control signal, a write control signal, and a chip select signal.

3. The Xintf bus interface controller based on FPGA according to claim 1, characterized in that: The daughter card uses a MIL-1394 daughter card, which is separately connected to the FPGA chip and is interconnected with the bus of the DSP chip with control permission through the internal logic of the FPGA chip.

4. The Xintf bus interface controller based on FPGA according to claim 1, characterized in that: The chip select signals of the external expansion chips AD, RAM, Flash, and the daughter card are all controlled by the FPGA chip.

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