Charge pump circuit with low output ripple and PCB
By introducing a delay unit and an inverter circuit into the charge pump circuit, delaying signal transmission, the output ripple high and leakage problems of the cross-coupled charge pump circuit are solved, and low output ripple and stable voltage conversion are achieved.
Patent Information
- Application Number
- CN202422218220.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2025-07-29
- Estimated Expiration
- 2034-09-10
AI Technical Summary
The existing cross-coupled charge pump circuit has problems with high output ripple and leakage risk.
The first and second delay units are introduced into the charge pump circuit, and signal transmission is delayed through the inverter circuit, preventing the substrate voltage from being lower than the source voltage, avoiding charge leakage, and shaping the voltage signal to reduce output ripple.
It effectively reduces the output voltage ripple, prevents charge leakage and circuit damage, and improves the stability and reliability of the charge pump circuit.
Smart Images
Figure CN223168228U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power management of analog integrated circuits, in particular to a charge pump circuit with low output ripple and a PCB board. Background Art
[0002] Charge pump circuits are widely used in low-power and low-current applications, such as power supply for portable electronic devices, LED driving, etc., mainly for voltage conversion.
[0003] The cross-coupled charge pump circuit is a commonly used charge pump circuit structure, which can make up for the consumption disadvantage of the threshold voltage. The circuit structure is as Figure 1 shown: It includes two NMOS transistors NM1 and NM2, and the gate-drain electrodes of the two NOMS transistors are cross-connected; four PMOS transistors PM1, PM2, PM3, PM4, and the gate-drain electrodes of the four PMOS transistors are cross-connected; it also includes two capacitors C1 and C2, and the two capacitors are respectively connected to the clock signal CLK1 and the complementary clock signal CLK2. During operation, on the one hand, the voltage is boosted by the continuous alternating charging and discharging of capacitors C1 and C2; on the other hand, a substrate selection circuit is formed by four PMOS transistors, and the substrate end is externally connected to capacitor C B to keep the substrate of the PMOS transistor at the highest potential during the clock cycle, avoiding charge leakage.
[0004] For the above-mentioned cross-coupled charge pump circuit, a substrate selection circuit is designed to solve the problem of charge leakage, but this structure will also cause the output ripple of the charge pump circuit to be relatively high, and there may be a situation where the substrate end voltage is less than the source end voltage during the circuit startup process, and there is still a risk of leakage. Summary of the Utility Model
[0005] Aiming at the deficiencies in the prior art, the utility model provides a charge pump circuit with low output ripple, which solves the problems of high output ripple and leakage existing in the cross-coupled charge pump circuit in the prior art.
[0006] According to an embodiment of the utility model, in a first aspect, a charge pump circuit with low output ripple is provided, including a first charge and discharge circuit and a second charge and discharge circuit for accessing the original input voltage, a substrate selection circuit, and an input clock signal. A first delay unit is further included between the first charge and discharge circuit and the substrate selection circuit, and a second delay unit is further included between the second charge and discharge circuit and the substrate selection circuit;
[0007] The first charge and discharge circuit and the second charge and discharge circuit are complementary in state;
[0008] The two inputs of the first delay unit are the voltage signals output by the first charge-discharge circuit, which are used to delay the transmission time of the voltage signals output by the first charge-discharge circuit to the substrate selection circuit;
[0009] The two inputs of the second delay unit are the voltage signals output by the second charge-discharge circuit, which are used to delay the transmission time of the voltage signals output by the second charge-discharge circuit to the substrate selection circuit;
[0010] The substrate selection circuit is used to select the higher one of the voltage signals output by the first charge-discharge circuit and the second charge-discharge circuit as the substrate voltage, and output the transformed original input voltage to the load;
[0011] Wherein, both the first delay unit and the second delay unit include inverter circuits.
[0012] Optionally, the first delay unit is a first logic OR gate, and the second delay unit is a second logic OR gate.
[0013] Optionally, the first delay unit is a first logic OR gate constructed using an inverter and a NOR gate, and the second delay unit is a second logic OR gate constructed using an inverter and a NOR gate.
[0014] Optionally, the first charge-discharge circuit includes a first NMOS transistor and a first capacitor, and the second charge-discharge circuit includes a second NMOS transistor and a second capacitor;
[0015] The drain of the first NMOS transistor is connected to the drain of the second NMOS transistor and is connected to the original input voltage; the source of the first NMOS transistor is connected to the upper plate of the first capacitor, the source of the second NMOS transistor is connected to the upper plate of the second capacitor, the gate of the first NMOS transistor is also connected to the source of the second NMOS transistor, and the gate of the second NMOS transistor is also connected to the source of the first NMOS transistor;
[0016] The lower plates of the first capacitor and the second capacitor are simultaneously connected to the input clock signal;
[0017] The upper plate of the first capacitor is also connected to one input of the first logic OR gate, and the lower plate of the first capacitor is also connected to the other input of the first logic OR gate;
[0018] The upper plate of the second capacitor is also connected to one input of the second logic OR gate, and the lower plate of the second capacitor is also connected to the other input of the second logic OR gate.
[0019] Optionally, the substrate selection circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a third capacitor;
[0020] The source of the first PMOS transistor is connected to the output of the first logic gate, the gate of the first PMOS transistor is connected to the output of the second logic gate, and the substrate of the first PMOS transistor is connected to the upper plate of the third capacitor; the source of the second PMOS transistor is connected to the output of the second logic gate, and the substrate of the second PMOS transistor is connected to the upper plate of the third capacitor; the drains of the first PMOS transistor and the second PMOS transistor are connected and then output the transformed original input voltage to the load;
[0021] The source of the third PMOS transistor is connected to the source of the second NMOS transistor. The substrate and the drain of the third PMOS transistor are connected and then connected to the upper plate of the third capacitor, and the gate of the third PMOS transistor is also connected to the source of the first NMOS transistor; the source of the fourth PMOS transistor is connected to the source of the first NMOS transistor. The substrate and the drain of the fourth PMOS transistor are connected and then connected to the upper plate of the third capacitor, and the gate of the fourth PMOS transistor is also connected to the source of the second NMOS transistor;
[0022] The lower plate of the third capacitor is grounded.
[0023] Optionally, the input clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in anti-phase with each other;
[0024] The lower plate of the first capacitor accesses the first clock signal, and the lower plate of the second capacitor accesses the second clock signal.
[0025] Optionally, when the first clock signal is at a high level and the second clock signal is at a low level, the first charge and discharge circuit is in a discharge state, and the second charge and discharge circuit is in a charge state; the first charge and discharge circuit outputs a high-voltage pulse to the first logic gate through the first capacitor.
[0026] Optionally, when the first clock signal is at a low level and the second clock signal is at a high level, the first charge and discharge circuit is in a charge state, and the second charge and discharge circuit is in a discharge state; the second charge and discharge circuit outputs a high-voltage pulse to the second logic gate through the second capacitor.
[0027] Optionally, it further includes a two-phase non-overlapping clock generation circuit, and the two-phase non-overlapping clock generation circuit generates the input clock signal.
[0028] The second aspect provides a PCB board, including the charge pump circuit with low output ripple as described above.
[0029] The technical principle of the present utility model is as follows: Under the control of the input clock signal, the first charge and discharge circuit and the second charge and discharge circuit continuously and alternately charge and discharge to achieve a boost conversion of the original input voltage. Before the substrate selection circuit selects the one with a higher output voltage signal from the first charge and discharge circuit and the second charge and discharge circuit as the substrate voltage, a first delay unit is introduced to delay the time when the voltage signal output by the first charge and discharge circuit is transmitted to the substrate selection circuit. At the same time, a second delay unit is also introduced to delay the time when the voltage signal output by the second charge and discharge circuit is transmitted to the substrate selection circuit. Finally, the substrate selection circuit outputs the converted original input voltage to the load.
[0030] Compared with the prior art, the present utility model has the following beneficial effects: By introducing the first delay unit and the second delay unit, the switching speed of the substrate selection circuit is delayed, preventing the situation where the substrate voltage may be lower than the source voltage during the circuit startup process, thereby avoiding defects such as charge leakage and circuit damage caused by the conduction of parasitic transistors. At the same time, there are inverter circuits in the first delay unit and the second delay unit, which can perform sharp pulse shaping on the voltage signals output by the first charge and discharge circuit and the second charge and discharge circuit, thereby reducing the final output voltage ripple. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 is a schematic circuit diagram of a conventional cross-coupled charge pump circuit;
[0032] Figure 2 is a schematic composition diagram of the charge pump circuit with low output ripple according to an embodiment of the present utility model;
[0033] Figure 3 is a schematic circuit diagram of the charge pump circuit with low output ripple according to an embodiment of the present utility model;
[0034] Figure 4 is an output voltage ripple diagram of a conventional cross-coupled charge pump circuit;
[0035] Figure 5 is an output voltage ripple diagram of the charge pump circuit with low output ripple according to an embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0036] The technical solutions in the present utility model will be further described below with reference to the drawings and embodiments.
[0037] As Figure 2As shown in the figure, an embodiment of the present utility model provides a charge pump circuit with low output ripple, which includes a first charge and discharge circuit 11, a second charge and discharge circuit 12, a substrate selection circuit 13 and an input clock signal. A first delay unit 14 is further included between the first charge and discharge circuit 11 and the substrate selection circuit 13, and a second delay unit 15 is further included between the second charge and discharge circuit 12 and the substrate selection circuit 13. Figure 2 Among them, the connection relationships of the above-mentioned various parts are as follows: The first charge and discharge circuit 11 and the second charge and discharge circuit 12 are connected to the original input voltage VIN. The first charge and discharge circuit 11 is connected to the first delay unit 14, and the two inputs of the first delay unit 14 are voltage signals output by the first charge and discharge circuit 11. The second charge and discharge circuit 12 is connected to the second delay unit 15, and the two inputs of the second delay unit 15 are voltage signals output by the second charge and discharge circuit 12. The first delay unit 14 and the second delay unit 15 are connected to the substrate selection circuit 13, and the output of the substrate selection circuit 13 is connected to the load.
[0038] The detailed working process of this embodiment is as follows: The states of the first charge and discharge circuit 11 and the second charge and discharge circuit 12 are complementary. Under the control of the input clock signal, the first charge and discharge circuit 11 and the second charge and discharge circuit 12 continuously and alternately charge and discharge to realize the boost conversion of the original input voltage VIN. Before the substrate selection circuit 13 selects the higher one of the voltage signals output by the first charge and discharge circuit 11 and the second charge and discharge circuit 12 as the substrate voltage, the first delay unit 14 is introduced to delay the time when the voltage signal output by the first charge and discharge circuit 11 is transmitted to the substrate selection circuit 13. At the same time, the second delay unit 15 is also introduced to delay the time when the voltage signal output by the second charge and discharge circuit 12 is transmitted to the substrate selection circuit 13, preventing the situation that the substrate voltage may be lower than the source voltage during the startup process of the circuit, thereby avoiding defects such as charge leakage and circuit damage caused by the conduction of parasitic transistors. At the same time, inverter circuits also exist in the first delay unit 14 and the second delay unit 15, which can shape the sharp pulses of the voltage signals output by the first charge and discharge circuit 11 and the second charge and discharge circuit 12, thereby reducing the final output voltage ripple.
[0039] In an embodiment of the present utility model, the first delay unit and the second delay unit can be a digital circuit delay unit, a VCDL delay unit circuit, etc. As Figure 3 shown, in a better implementation manner, the first delay unit 14 is a first logic OR gate OR1, and the second delay unit 15 is a second logic OR gate OR2. Or, the first delay unit 14 is an equivalent circuit of the first logic OR gate OR1, such as the first logic OR gate OR1 constructed by using an inverter and a NOR gate, and the second delay unit 15 is an equivalent circuit of the second logic OR gate OR2, such as the second logic OR gate OR2 constructed by using an inverter and a NOR gate.
[0040] Through the above-mentioned first logic OR gate OR1 and second logic OR gate OR2, on the one hand, logical judgments are added between the first charge and discharge circuit 11 and the substrate selection circuit 13, and logical judgments are added between the second charge and discharge circuit 12 and the substrate selection circuit 13, achieving the purpose of increasing signal delay. On the other hand, by using a logic OR gate, it meets the design of having inverter circuits in the first delay unit 14 and the second delay unit 15, and can perform sharp pulse shaping on the voltage signals output by the first charge and discharge circuit 11 and the second charge and discharge circuit 12.
[0041] It can be understood that the implementation of obtaining a logic OR gate by constructing an equivalent circuit using an inverter and a NAND gate is as follows: in the first logic OR gate, the output of the NAND gate is connected to an inverter; in the second logic OR gate, the output of the NAND gate is connected to an inverter.
[0042] In the embodiment of the present invention, the first charge and discharge circuit 11 includes a first NMOS transistor NM1 and a first capacitor C1, the second charge and discharge circuit 12 includes a second NMOS transistor NM2 and a second capacitor C2, and the gate-drain electrodes of the first NMOS transistor NM1 and the second NMOS transistor NM2 are cross-connected.
[0043] Please refer to Figure 3 , the embodiment of the present invention also shows the detailed circuit structures of the first charge and discharge circuit 11 and the second charge and discharge circuit 12. Figure 3 In, the drain of the first NMOS transistor NM1 is connected to the drain of the second NMOS transistor NM2 and is connected to the original input voltage VIN; the source of the first NMOS transistor NM1 is connected to the upper plate of the first capacitor C1, the source of the second NMOS transistor NM2 is connected to the upper plate of the second capacitor C2, the gate of the first NMOS transistor NM1 is also connected to the source of the second NMOS transistor NM2, and the gate of the second NMOS transistor NM2 is also connected to the source of the first NMOS transistor NM1; the lower plates of the first capacitor C1 and the second capacitor C2 are simultaneously connected to the input clock signal.
[0044] In a specific application, according to the characteristics that the first capacitor C1 and the second capacitor C2 have the function of storing charges, when the first charge and discharge circuit 11 is in a discharge state, a voltage signal is output by the first capacitor C1; when the second charge and discharge circuit 12 is in a discharge state, a voltage signal is output by the second capacitor C2. And as Figure 3As shown in the figure, the first charge and discharge circuit 11 is connected to the first logic OR gate OR1 as follows: the upper plate of the first capacitor C1 is connected to one input of the first logic OR gate OR1, and the lower plate of the first capacitor C1 is also connected to the other input of the first logic OR gate OR1. The second charge and discharge circuit 12 is connected to the second logic OR gate OR2 as follows: the upper plate of the second capacitor C2 is connected to one input of the second logic OR gate OR2, and the lower plate of the second capacitor C2 is also connected to the other input of the second logic OR gate OR2. On this basis, the highest potential of the first logic OR gate OR1 is connected to the upper plate of the first capacitor C1, and the lowest potential is connected to the lower plate of the first capacitor C1, so that the potential of the first logic OR gate OR1 is consistent with the potential of the upper plate of the first capacitor C1, mainly the highest potential or the lowest potential is consistent, so that the first logic OR gate OR1 only delays the signal and does not cause signal distortion. Similarly, the highest potential of the second logic OR gate OR2 is connected to the upper plate of the second capacitor C2, and the lowest potential is connected to the lower plate of the second capacitor C2, so that the potential of the second logic OR gate OR2 is consistent with the potential of the upper plate of the second capacitor C2, so that the second logic OR gate OR2 only delays the signal and does not cause signal distortion.
[0045] In the embodiment of the present invention, the substrate selection circuit 13 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, and a third capacitor CB; and the gate-drain electrodes of the first PMOS transistor PM1 and the second PMOS transistor PM2 are cross-connected.
[0046] Please refer to Figure 3 , the embodiment of the present invention also gives the detailed circuit structure of the substrate selection circuit 13. Figure 3In the circuit, the source of the first PMOS transistor PM1 is connected to the output of the first logic gate, the gate of the first PMOS transistor PM1 is connected to the output of the second logic gate, and the substrate of the first PMOS transistor PM1 is connected to the upper plate of the third capacitor CB; the source of the second PMOS transistor PM2 is connected to the output of the second logic gate, and the substrate of the second PMOS transistor PM2 is connected to the upper plate of the third capacitor CB; the drains of the first PMOS transistor PM1 and the second PMOS transistor PM2 are connected and then output the transformed original input voltage VOUT to the load; the source of the third PMOS transistor PM3 is connected to the source of the second NMOS transistor NM2, and the substrate and the drain of the third PMOS transistor PM3 are connected and then connected to the upper plate of the third capacitor CB, and the gate of the third PMOS transistor PM3 is also connected to the source of the first NMOS transistor NM1; the source of the fourth PMOS transistor PM4 is connected to the source of the first NMOS transistor NM1, and the substrate and the drain of the fourth PMOS transistor PM4 are connected and then connected to the upper plate of the third capacitor CB, and the gate of the fourth PMOS transistor PM4 is also connected to the source of the second NMOS transistor NM2; the lower plate of the third capacitor CB is grounded. It can be seen that the source of the second NMOS transistor NM2 is connected to the source of the first PMOS transistor PM1, the source of the third PMOS transistor PM3, and the gate of the second PMOS transistor PM2 through the first logic OR gate OR1, and the source of the second NMOS transistor NM2 is connected to the source of the second PMOS transistor PM2, the source of the fourth PMOS transistor PM4, and the gate of the first PMOS transistor PM1 through the second logic OR gate OR2. Then, under the control of the input clock signal, the first PMOS transistor PM1 and the third PMOS transistor PM3 of the substrate selection circuit 13 are turned on, or the second PMOS transistor PM2 and the fourth PMOS transistor PM4 are turned on. In the above two cases, the circuit will charge the third capacitor CB and the load at the same time. And since the upper plate of the third capacitor CB is connected to the substrates of the first PMOS transistor PM1 and the second PMOS transistor PM2, and the drains of the third PMOS transistor PM3 and the fourth PMOS transistor PM4, when the second PMOS transistor PM2 and the fourth PMOS transistor PM4 are turned on, the substrate of the second PMOS transistor PM2 will be at the highest potential, and when the first PMOS transistor PM1 and the third PMOS transistor PM3 are turned on, the substrate voltages of the first PMOS transistor PM1 and the third PMOS transistor PM3 will always be at the highest potential.
[0047] It should be noted that Figure 3 in the example, the output of the substrate selection circuit 13, that is, the output after the drains of the first PMOS transistor PM and the second PMOS transistor PM2 are connected, is represented as VOUT. VOUT is the transformed original input voltage, and the load is represented by an inductor ROUT and a capacitor CO;
[0048] The embodiments of the present utility model also give an example of the clock signal to illustrate two conduction situations of the first NMOS transistor NM1, the second NMOS transistor NM2, the first PMOS transistor PM1 to the fourth PMOS transistor PM4.
[0049] As Figure 3 shown, the input clock signal includes a first clock signal CLK1 and a second clock signal CLK2, and the first clock signal CLK1 and the second clock signal CLK2 are in antiphase with each other; the lower plate of the first capacitor C1 is connected to the first clock signal CLK1, and the lower plate of the second capacitor C2 is connected to the second clock signal CLK2.
[0050] In a preferred implementation manner, it further includes a two-phase non-overlapping clock generation circuit, and the two-phase non-overlapping clock generation circuit generates the above-mentioned input clock signal, that is, the first clock signal CLK1 and the second clock signal CLK2 that are in antiphase with each other.
[0051] Exemplarily, when the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level, the first charge and discharge circuit 11 is in a discharge state, and the second charge and discharge circuit 12 is in a charging state. Combining Figure 3 , according to the characteristic of the capacitor storing charge, the voltage of the upper plate of the first capacitor C1 is VDD, then the source voltage of the first NMOS transistor NM1 rises to 2VDD, and the source of the first NOS transistor is connected to the gate of the second NMOS transistor NM2, so the second NMOS transistor NM2 is turned on, and the original input voltage VIN also charges the second capacitor C2, and the voltage of the lower plate of the second capacitor C2 is 0. After a period of time, the voltage of the upper plate of the second capacitor C2 rises to VDD. Finally, the source voltage of the first NMOS transistor NM1 is 2VDD, and the source voltage of the second NMOS transistor NM2 is VDD. Since the source of the second NMOS transistor NM2 is also connected to the source of the first PMOS transistor PM1, the source of the third PMOS transistor PM3, and the gate of the second PMOS transistor PM2 through the first logic OR gate OR1, and the source of the first NMOS transistor NM1 is connected to the source of the second PMOS transistor PM2, the source of the fourth PMOS transistor PM4, and the gate of the first PMOS transistor PM1 through the second logic OR gate OR2. Therefore, at this time, the gate voltages of the second PMOS transistor PM2 and the fourth PMOS transistor PM4 are VDD, which is less than the source voltage of 2VDD, so they are turned on, and the circuit will charge the third capacitor CBCB and the load Co at the same time. In addition, since the upper plate of the third capacitor CB is connected to the substrate of the first PMOS transistor PM1, the substrate of the second PMOS transistor PM2, and the drain of the second PMOS transistor PM2, the drain of the fourth PMOS transistor PM4, the substrate of the second PMOS transistor PM2 is at the highest potential at this time.
[0052] The first charge-discharge circuit 11 outputs a high-voltage pulse to the first logic gate through the first capacitor C1; when the first clock signal CLK1 is at a low level and the second clock signal CLK2 is at a high level, the first charge-discharge circuit 11 is in a charging state, and the second charge-discharge circuit 12 is in a discharging state; the second charge-discharge circuit 12 outputs a high-voltage pulse to the second logic gate through the second capacitor C2. Combining Figure 3 , according to the characteristic of the capacitor storing charge, if the voltage of the upper plate of the capacitor C2 is VDD, the source voltage of the second NMOS transistor NM2 is raised to 2VDD. The source of the second NMOS transistor NM2 is connected to the gate of the first NMOS transistor NM1. At this time, the first NMOS transistor NM1 is turned on, and the original voltage input charges the first capacitor C1. The voltage of the lower plate of the first capacitor C1 is 0. After a period of time, the voltage of the upper plate of the first capacitor C1 is VDD. Finally, the source voltage of the first NMOS transistor NM1 is VDD, and the source voltage of the second NMOS transistor NM2 is 2VDD. Since the source of the second NMOS transistor NM2 is also connected to the source of the first PMOS transistor PM1, the source of the third PMOS transistor PM3, and the gate of the second PMOS transistor PM2 through the first logic OR gate OR1, and the source of the first NMOS transistor NM1 is connected to the source of the second PMOS transistor PM2, the source of the fourth PMOS transistor PM4, and the gate of the first PMOS transistor PM1 through the second logic OR gate OR2. At this time, the gate voltages of the first PMOS transistor PM1 and the third PMOS transistor PM3 are VDD, which is less than the source voltage of 2VDD and thus turned on, and the circuit will charge the third capacitor CBCB and the load Co simultaneously. In addition, since the upper plate of the third capacitor CB is connected to the substrate of the first PMOS transistor PM1, the substrate of the second PMOS transistor PM2, and the drains of the second PMOS transistor PM2 and the fourth PMOS transistor PM4, the substrate of the first PMOS transistor PM1 is at the highest potential at this time.
[0053] In the charge pump circuit with low output ripple provided by the embodiment of the present invention, as the clock CLK1 and CLK2 continuously alternate to charge the third capacitor CBCB and the load Co, after a period of time, the original input voltage VIN is stably transformed to 2VDD, and at the same time, the substrate voltages of the first PMOS transistor PM1 and the second PMOS transistor PM2 are always at the highest potential.
[0054] As Figure 4 and Figure 5 shown, the embodiment of the present invention also uses simulation to illustrate the improvement in the performance of suppressing output ripple of the provided charge pump circuit. Among them, Figure 4 is the output ripple simulation diagram of the existing charge pump circuit, Figure 4 in which the horizontal axis represents time, the unit is us, and the vertical axis represents the transformed original input voltage, that is, Figure 1 the VOUT inFigure 4 Point A in it represents the maximum value of the output ripple, point B represents the minimum value of the output ripple, and △ represents the ratio between the two. Figure 5 This is the output ripple simulation diagram of the charge pump circuit according to the embodiment of the present invention. Figure 5 In it, the horizontal axis represents time with the unit of μs, and the vertical axis represents the transformed original input voltage, that is Figure 3 VOUT in it, with the unit of V. Figure 5 Point A in it represents the maximum value of the output ripple, point B represents the minimum value of the output ripple, and △ represents the ratio between the two. Under the same simulation conditions, the simulation results are as shown in Figure 4 and Figure 5 shown: The output voltage ripple of the existing charge pump circuit is about 16 mV, while the output voltage ripple of the charge pump circuit provided by the embodiment of the present invention is about 12 mV. It can be seen that the charge pump circuit with low output ripple of the embodiment of the present invention has improved in the performance of suppressing output ripple.
[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.
Claims
1. A charge pump circuit with low output ripple, characterized in that It includes a first charge-discharge circuit and a second charge-discharge circuit for accessing the original input voltage, a substrate selection circuit, and an input clock signal. A first delay unit is further included between the first charge-discharge circuit and the substrate selection circuit, and a second delay unit is further included between the second charge-discharge circuit and the substrate selection circuit; The states of the first charge-discharge circuit and the second charge-discharge circuit are complementary; Two inputs of the first delay unit are voltage signals output by the first charge-discharge circuit, and are used to delay the time for the voltage signal output by the first charge-discharge circuit to be transmitted to the substrate selection circuit; Two inputs of the second delay unit are voltage signals output by the second charge-discharge circuit, and are used to delay the time for the voltage signal output by the second charge-discharge circuit to be transmitted to the substrate selection circuit; The substrate selection circuit is used to select the one with a higher output voltage signal between the first charge-discharge circuit and the second charge-discharge circuit as the substrate voltage, and output the transformed original input voltage to the load; Wherein, both the first delay unit and the second delay unit include inverter circuits.
2. The charge pump circuit with low output ripple as described in claim 1, wherein The first delay unit is a first logic OR gate, and the second delay unit is a second logic OR gate.
3. The charge pump circuit with low output ripple as described in claim 1, wherein The first delay unit is a first logic OR gate constructed using an inverter and a NOR gate, and the second delay unit is a second logic OR gate constructed using an inverter and a NOR gate.
4. The charge pump circuit with low output ripple as claimed in claim 2, wherein The first charge-discharge circuit includes a first NMOS transistor and a first capacitor, and the second charge-discharge circuit includes a second NMOS transistor and a second capacitor; The drain of the first NMOS transistor is connected to the drain of the second NMOS transistor and accesses the original input voltage; the source of the first NMOS transistor is connected to the upper plate of the first capacitor, the source of the second NMOS transistor is connected to the upper plate of the second capacitor, the gate of the first NMOS transistor is further connected to the source of the second NMOS transistor, and the gate of the second NMOS transistor is further connected to the source of the first NMOS transistor; The lower plates of the first capacitor and the second capacitor are simultaneously connected to the input clock signal; The upper plate of the first capacitor is further connected to one input of the first logic OR gate, and the lower plate of the first capacitor is further connected to the other input of the first logic OR gate; The upper plate of the second capacitor is further connected to one input of the second logic OR gate, and the lower plate of the second capacitor is further connected to the other input of the second logic OR gate.
5. The charge pump circuit with low output ripple as described in claim 4, wherein The substrate selection circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a third capacitor; The source of the first PMOS transistor is connected to the output of the first logic gate, the gate of the first PMOS transistor is connected to the output of the second logic gate, and the substrate of the first PMOS transistor is connected to the upper plate of the third capacitor; the source of the second PMOS transistor is connected to the output of the second logic gate, and the substrate of the second PMOS transistor is connected to the upper plate of the third capacitor; the drains of the first PMOS transistor and the second PMOS transistor are connected and then output the transformed original input voltage to the load; The source of the third PMOS transistor is connected to the source of the second NMOS transistor. The substrate and the drain of the third PMOS transistor are connected and then connected to the upper plate of the third capacitor. The gate of the third PMOS transistor is also connected to the source of the first NMOS transistor; the source of the fourth PMOS transistor is connected to the source of the first NMOS transistor. The substrate and the drain of the fourth PMOS transistor are connected and then connected to the upper plate of the third capacitor. The gate of the fourth PMOS transistor is also connected to the source of the second NMOS transistor; The lower plate of the third capacitor is grounded.
6. The charge pump circuit with low output ripple according to any one of claims 1 to 5, characterized in that, The input clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in anti-phase with each other; The lower plate of the first capacitor is connected to the first clock signal, and the lower plate of the second capacitor is connected to the second clock signal.
7. The charge pump circuit with low output ripple as described in claim 6, wherein When the first clock signal is at a high level and the second clock signal is at a low level, the first charge-discharge circuit is in a discharge state, and the second charge-discharge circuit is in a charge state; the first charge-discharge circuit outputs a high-voltage pulse to the first logic gate through the first capacitor.
8. The charge pump circuit with low output ripple as claimed in claim 6, wherein When the first clock signal is at a low level and the second clock signal is at a high level, the first charge-discharge circuit is in a charge state, and the second charge-discharge circuit is in a discharge state; the second charge-discharge circuit outputs a high-voltage pulse to the second logic gate through the second capacitor.
9. The charge pump circuit with low output ripple according to claim 6, wherein It further includes a two-phase non-overlapping clock generation circuit, and the two-phase non-overlapping clock generation circuit generates the input clock signal.
10. A PCB board, characterized in that, It includes a charge pump circuit with low output ripple as described in any one of claims 1 to 9.