ZYNQ-based ADC all-digital phase discriminator
Through the ADC fully digital phase detector based on ZYNQ, the ZYNQ core module and rotary frequency phase detector are used to replace the traditional logic comparison array, and the deadband, complexity and power consumption problems of the existing digital phase detector are solved, achieving high-precision and low-power phase detector phase detection effect.
Patent Information
- Application Number
- CN202422019758.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2025-07-29
- Estimated Expiration
- 2034-08-20
AI Technical Summary
The existing digital phase detectors have problems such as dead zones, complex circuit structure, many transistors required, large logic delays for multiple inputs, low circuit operating frequency, and large high-frequency dynamic power consumption.
The ZYNQ-based ADC fully digital phase detector is adopted, and the ZYNQ core module, ADC sampling module, rotary frequency phase detector module and frequency source module are used, and the traditional logic comparison array is replaced by rotary frequency phase detector, which achieves high integration through bus interconnection, eliminates the impact of deadband, increases the operating frequency and reduces power consumption.
It realizes a high-precision, low-power, and low-cost digital phase detector, with extremely high theoretical accuracy and reliability, can perform ultra-fine quantization separation and phase adjustment, and improves the reliability and frequency synchronization of the circuit.
Smart Images
Figure CN223168322U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of network communication, in particular to an ADC all-digital phase discriminator based on ZYNQ. Background Art
[0002] At present, traditional digital phase discriminators are basically based on charge pump phase-locked loops. The principle is to use FPGA or logic devices to form an input NAND logic gate array, and obtain a charge pump pulse signal according to the phase comparison result of the reference frequency and the local frequency. There are disadvantages such as dead zones, complex circuit structures, many required transistors, large delays of multi-input logic gates, low circuit operating frequencies, and high high-frequency dynamic power consumption. Content of the Utility Model
[0003] The utility model provides an ADC all-digital phase discriminator based on ZYNQ to solve the problems of dead zones, complex circuit structures, many required transistors, large delays of multi-input logic gates, low circuit operating frequencies, and high high-frequency dynamic power consumption existing in the existing digital phase discriminators.
[0004] The utility model realizes the above purpose through the following technical solutions:
[0005] An ADC all-digital phase discriminator based on ZYNQ, comprising:
[0006] A ZYNQ core module, the output end of the ZYNQ core module is used to be connected to an external interface, and the ZYNQ core module is used for data processing;
[0007] An ADC sampling module, the output end of the ADC sampling module is connected to the input end of the ZYNQ core module, and the ADC sampling module is used for sampling quadrature IQ frequency signals;
[0008] A rotating frequency discriminator and phase discriminator module, the output end of the rotating frequency discriminator and phase discriminator module is connected to the input end of the ADC sampling module, and the rotating frequency discriminator and phase discriminator module is used for generating quadrature IQ frequency signals;
[0009] A frequency source module, the output end of the frequency source module is connected to the receiving end of the rotating frequency discriminator and phase discriminator module, the frequency source module is connected to the ZYNQ core module, and the frequency source module is used for generating a system clock and adjusting the local frequency phase;
[0010] A reference input module, the output end of the reference input module is connected to the input end of the rotating frequency discriminator and phase discriminator module, and the reference input module is used for receiving frequency signals.
[0011] Specifically, the ZYNQ core module includes a ZYNQ chip, a reset chip, a FLASH chip, and an SDRAM chip. The ZYNQ chip is respectively connected to the reset chip, the FLASH chip, and the SDRAM chip.
[0012] Further, a signal receiving end and a signal output end are provided on the reference input module. The signal receiving end is used to receive 1 MHz, 5 MHz, and 10 MHz reference signals. The signal output end is used to output 1 MHz, 5 MHz, and 10 MHz reference signals. The signal output end is connected to the receiving end of the rotation frequency discriminator and phase detector module.
[0013] Further, a control interface is provided on the frequency source module. The control interface is connected to the ZYNQ core module. The control interface is used to receive the feedback signal provided by the ZYNQ core module. The frequency source module is used to generate a standard frequency 10 MHz signal.
[0014] The beneficial effects of the present utility model are as follows:
[0015] The present utility model provides an ADC all-digital phase detector based on ZYNQ, which has a ZYNQ architecture chip with high integration. The internal bus interconnection greatly reduces the hardware design difficulty. The rotation frequency discriminator and phase detector is used to replace the traditional logic comparison array, which has extremely high theoretical accuracy, eliminates the influence of dead zones, increases the operating frequency, and reduces the high-frequency dynamic power consumption. Since the rotation frequency discriminator and phase detector has extremely high theoretical accuracy, the phase difference obtained by phase discrimination can be finely quantized and separated, and extremely small step adjustments can be made at the VCO end to ensure the continuity of the phase, thereby improving the reliability of the digital phase detector. Description of the Drawings
[0016] Figure 1 It is the structural schematic diagram of an ADC all-digital phase detector based on ZYNQ in an embodiment of the present utility model.
[0017] Figure 2 It is the structural schematic diagram of the ZYNQ core module in an embodiment of the present utility model.
[0018] Figure 3 It is the working schematic diagram of an ADC all-digital phase detector based on ZYNQ in an embodiment of the present utility model.
[0019] In the figure: 1 - ZYNQ core module; 11 - ZYNQ chip; 12 - reset chip; 13 - FLASH chip; 14 - SDRAM chip; 2 - ADC sampling module; 3 - rotation frequency discriminator and phase detector module; 4 - frequency source module; 5 - reference input module. Specific Embodiments
[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present utility model clearer, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Apparently, the described embodiments are some, but not all, of the embodiments of the present utility model. Components of the embodiments of the present utility model usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.
[0021] Therefore, the following detailed description of the embodiments of the present utility model provided in the accompanying drawings is not intended to limit the scope of the claimed present utility model, but merely represents selected embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the scope of protection of the present utility model.
[0022] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0023] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship when the product of the present utility model is normally placed, or the orientation or positional relationship commonly understood by those skilled in the art. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present utility model.
[0024] In addition, the terms "first", "second", etc. are only used for descriptive distinction and cannot be understood as indicating or implying relative importance.
[0025] In the description of the present utility model, it should also be noted that unless otherwise clearly specified and defined, terms such as "set", "connect" should be understood in a broad sense. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0026] The following will describe in detail the specific implementation manners of the present utility model with reference to the accompanying drawings.
[0027] As Figure 1 shown, an ADC all-digital phase discriminator based on ZYNQ includes:
[0028] ZYNQ Core Module 1, the output end of the ZYNQ Core Module 1 is used to connect to an external interface, and the ZYNQ Core Module 1 is used for data processing;
[0029] ADC Sampling Module 2, the output end of the ADC Sampling Module 2 is connected to the input end of the ZYNQ Core Module 1, and the ADC Sampling Module 2 is used for sampling quadrature IQ frequency signals;
[0030] Rotary Frequency Discrimination and Phase Discrimination Module 3, the output end of the Rotary Frequency Discrimination and Phase Discrimination Module 3 is connected to the input end of the ADC Sampling Module 2, and the Rotary Frequency Discrimination and Phase Discrimination Module 3 is used for generating quadrature IQ frequency signals;
[0031] Frequency Source Module 4, the output end of the Frequency Source Module 4 is connected to the receiving end of the Rotary Frequency Discrimination and Phase Discrimination Module 3, the Frequency Source Module 4 is connected to the ZYNQ Core Module 1, and the Frequency Source Module 4 is used for generating a system clock and adjusting the local frequency phase;
[0032] Reference Input Module 5, the output end of the Reference Input Module 5 is connected to the receiving end of the Rotary Frequency Discrimination and Phase Discrimination Module 3, and the Reference Input Module 5 is used for receiving frequency signals.
[0033] As Figure 2 shown, in some embodiments, the ZYNQ Core Module 1 includes a ZYNQ chip 11, a reset chip 12, a FLASH chip 13, and an SDRAM chip 14, and the ZYNQ chip 11 is respectively connected to the reset chip 12, the FLASH chip 13, and the SDRAM chip 14.
[0034] As Figure 2 shown, the ADC Sampling Module 2 is used for sampling IQ frequency signals, obtaining the sine value and cosine value of the frequency, and the phase difference quadrant at any moment can be identified by calculating the signs of the outputs I and Q of the phase discriminator. If the phase error is in the first quadrant, then both phase discriminators output positive values. If the sine phase discriminator outputs a positive value and the cosine phase discriminator outputs a negative value, then the phase is in the second quadrant.
[0035] In some embodiments, the Reference Input Module 5 is provided with a signal receiving end and a signal output end. The signal receiving end is used for receiving 1 MHz, 5 MHz, and 10 MHz reference signals, the signal output end is used for outputting 1 MHz, 5 MHz, and 10 MHz reference signals, and the signal output end is connected to the receiving end of the Rotary Frequency Discrimination and Phase Discrimination Module 3.
[0036] In some embodiments, a control interface is provided on the frequency source module 4, and the control interface is connected to the ZYNQ core module 1. The control interface is used to receive the feedback signal provided by the ZYNQ core module 1, and the frequency source module 4 is used to generate a reference frequency 10 MHz signal.
[0037] Among them, the rotary phase discriminator module 3 is used for phase discrimination and frequency measurement, the ADC sampling module 2 is used for digitizing the amplitude-frequency function, and the phase and frequency calculations are completed using the computing power of the ZYNQ core module 1. The frequency source module is used to receive the feedback signal provided by the ZYNQ core module to adjust its own frequency and phase, so as to generate a reference frequency 10 MHz signal with low phase noise and high precision.
[0038] As Figure 3 shown, the core working principle of a ZYNQ-based ADC all-digital phase discriminator of the present invention is as follows:
[0039] The rotary phase discriminator module 3 receives 10 MHz, 5 MHz, 1 MHz from the reference input module 5, and its amplitude-frequency function is expressed as Sin(ω i t+φ d t). It receives 10 MHz from the frequency source module 4 to generate a path of in-phase and a path of 90° quadrature IQ frequency signals 2Sin(ω o t) and 2Cos(ω o t), which are mixed with the input from the reference input module 5. After mixing, the two signals are respectively expressed by the amplitude-frequency functions as Sin[(ω i -ω o )t-φ d t] and Cos[(ω i -ω o )t-φ d t]. According to the description of the amplitude-frequency function, it can be known that this signal provides sufficient phase information and frequency information, and the phase difference between the reference and local frequencies can be obtained using the inverse trigonometric function. Figure 3 In the figure, LPF represents a low-pass filter, and VOC represents a voltage-controlled oscillator. The rotary phase discriminator module 3 multiplies the input signal and the signal generated by the VCO and filters them to extract the information related to the frequency and phase of the input signal. These information can be used to adjust the VCO so that its output signal is synchronized with the frequency and phase of the input signal, thereby achieving the purpose of phase locking.
[0040] In some embodiments, the ZYNQ chip 11 uses a domestic programmable fusion chip based on the TSMC 28nm HPC+ process, integrating a processing system (PS) of a quad-core high-performance processor and 350K programmable logic (PL) with 429 million gate circuits. The quad-core high-performance processor is the core of the processor system, which works in cooperation with on-chip memory, external memory interface DDR, various system function components, I / O peripherals, and the programmable logic part, etc., to jointly form a rich-function on-chip programmable system.
[0041] In some embodiments, the ADC sampling module 2 uses a JAD9268-100 chip. The dual ADC cores adopt a multi-stage differential pipelined architecture and integrate an output error correction logic. Each ADC has a wide bandwidth, a differential sample-and-hold analog input amplifier, and supports various user-selectable input ranges. The integrated voltage reference simplifies the design considerations. A duty cycle stabilizer is provided to compensate for the variation of the ADC clock duty cycle, enabling the converter to maintain excellent performance.
[0042] In some embodiments, the rotation frequency discriminator and phase discriminator module 3 uses a TC4-1T+ transformer and ADG1419 and MAX4635EUB switches to achieve I / Q quadrature transformation.
[0043] In some embodiments, the frequency source module 4 uses a DACSGM5349 frequency source module to convert the digital feedback control signal into an analog voltage-controlled signal. After being buffered by the amplifier SGM8061, the analog voltage-controlled signal is given to the crystal oscillator to adjust the frequency. The SGM431 voltage reference chip powers the chips related to the analog voltage-controlled signal of the frequency source module.
[0044] In some embodiments, the reference input module 5 includes a power divider, a Schmitt trigger, and a power attenuation circuit. The signal input enters the power divider after passing through the power attenuation circuit. The STCP210+ power divider provides one path to the rotation frequency discriminator and phase discriminator module, and the other path passes through the 74ALVC1G17 Schmitt trigger to detect the presence or absence of the signal.
[0045] An all-digital phase detector for ADC based on ZYNQ proposed by the utility model solves the disadvantages of the existing digital phase detector, such as dead zone, complex circuit structure, large number of required transistors, large delay of multi-input logic gates, low operating frequency of the circuit, and high high-frequency dynamic power consumption. The utility model has a ZYNQ architecture chip with high integration, and the internal bus interconnection greatly reduces the hardware design difficulty; the rotating frequency discriminator and phase detector is adopted to replace the traditional logic comparison array, which has extremely high theoretical accuracy, and can be calculated in all frequency quadrants, eliminating the influence of the dead zone, increasing the operating frequency, and reducing the high-frequency dynamic power consumption; due to the extremely high theoretical accuracy of the rotating frequency discriminator and phase detector, the phase difference obtained by phase detection can be super finely quantized and separated, and extremely small step adjustment can be performed at the VCO end to ensure the continuity of the phase, improving the reliability of the digital phase detector. An all-digital phase detector for ADC based on ZYNQ of the utility model has the advantages of high precision, high integration, low power consumption, and low cost.
[0046] The above are only the preferred embodiments of the utility model. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the utility model, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the utility model.
Claims
1. An ADC all-digital phase detector based on ZYNQ, characterized in that: Comprising: A ZYNQ core module (1), the output end of the ZYNQ core module (1) is used to be connected to an external interface, and the ZYNQ core module (1) is used for data processing; An ADC sampling module (2), the output end of the ADC sampling module (2) is connected to the input end of the ZYNQ core module (1), and the ADC sampling module (2) is used for sampling quadrature IQ frequency signals; A rotating frequency discriminator and phase detector module (3), the output end of the rotating frequency discriminator and phase detector module (3) is connected to the input end of the ADC sampling module (2), and the rotating frequency discriminator and phase detector module (3) is used for generating quadrature IQ frequency signals; A frequency source module (4), the output end of the frequency source module (4) is connected to the receiving end of the rotating frequency discriminator and phase detector module (3), the frequency source module (4) is connected to the ZYNQ core module (1), and the frequency source module (4) is used for generating a system clock and adjusting the local frequency phase; A reference input module (5), the output end of the reference input module (5) is connected to the receiving end of the rotating frequency discriminator and phase detector module (3), and the reference input module (5) is used for receiving frequency signals.
2. The all-digital phase detector for ADC based on ZYNQ according to claim 1, wherein The ZYNQ core module (1) includes a ZYNQ chip (11), a reset chip (12), a FLASH chip (13) and an SDRAM chip (14), and the ZYNQ chip (11) is respectively connected to the reset chip (12), the FLASH chip (13) and the SDRAM chip (14).
3. The all-digital phase discriminator of an ADC based on ZYNQ according to claim 1, wherein The reference input module (5) is provided with a signal receiving end and a signal output end. The signal receiving end is used for receiving 1MHz, 5MHz and 10MHz reference signals. The signal output end is used for outputting 1MHz, 5MHz and 10MHz reference signals, and the signal output end is connected to the receiving end of the rotating frequency discriminator and phase detector module (3).
4. The all-digital phase discriminator of an ADC based on ZYNQ according to claim 1, wherein The frequency source module (4) is provided with a control interface, the control interface is connected to the ZYNQ core module (1), the control interface is used for receiving a feedback signal provided by the ZYNQ core module (1), and the frequency source module (4) is used for generating a standard frequency 10MHz signal.