Topological structure and image forming device

Abstract

The utility model discloses a topological structure and an image forming device, the topological structure comprises a main controller, N DDR particles and a wire, the wire comprises P data lines, the data lines are first daisy chain structures, the P first daisy chain structures are used for connecting the main controller and the N DDR particles, and the main controller is connected with the N DDR particles. At least one first daisy chain structure is connected with at least two DDR particles, and N is an even number greater than or equal to 4; p is an even number greater than or equal to 2. The main controller and the DDR particles are connected through the data line of the daisy chain structure, so that the DATA signal quality of the multiplexed DDR particles can be greatly improved, and the overshoot is obviously smaller than that of a T-shaped topological structure.

Description

Technical Field

[0001] The utility model relates to the technical field of image formation, and particularly relates to a topological structure and an image forming apparatus. Background Art

[0002] With the continuous development of image formation technology, the functions of image forming apparatuses have become increasingly diversified. Therefore, it is necessary to select a suitable DDR (Double Data Rate SDRAM) to meet the implementation of the functions of the image forming apparatus. In order to cope with the different requirements of the image forming apparatus for DDR memory, such as different capacities or different speeds, etc., a compatibility design is usually made on the PCB (Printed Circuit Board). In the prior art, a T-shaped topological structure is usually adopted for the DDR memory data lines. However, in actual use, when the DDR memory of the SOC (System on Chip) of the image forming apparatus, for example, has two groups of data lines and needs to externally connect 4 DDR particles or even more DDR particles, when one group of data lines multiplexes two or more DDR particles, when wiring with the usual T-shaped topological structure, the stub lines generated by wiring are too long, resulting in signal reflection, affecting the signal quality, and thus causing poor read and write signals of the data lines regardless of which DDR particle is multiplexed. Summary of the Utility Model

[0003] Aiming at the deficiencies of the prior art, the purpose of the present utility model is to provide a topological structure and an image forming apparatus, which are used to solve the problem that when multiplexing multiple DDR particles, the T-shaped topological structure of the data lines will cause the stub lines to be too long, resulting in signal reflection and affecting the signal quality.

[0004] According to the first aspect of the present utility model, a topological structure is provided, including:

[0005] A main controller;

[0006] N DDR particles, where N is an even number greater than or equal to 4;

[0007] Trace lines, the trace lines include P data lines, the data lines are in a first daisy chain structure, and the P first daisy chain structures are used to connect the main controller and the N DDR particles, and at least one of the first daisy chain structures is connected to at least two of the DDR particles, where P is an even number greater than or equal to 2.

[0008] The topological structure of the present utility model can greatly improve the DATA signal quality of the multiplexed DDR particles by connecting the main controller and the DDR particles through the data lines in the daisy chain structure, and the overshoot is significantly smaller than that of the T-shaped topological structure.

[0009] In some embodiments, the first daisy-chain structure is a FLY-BY structure.

[0010] In some embodiments, the N DDR particles are arranged on the same layer of the PCB board.

[0011] In some embodiments, the N DDR particles are arranged on the same plane of the same layer of the PCB board.

[0012] In some embodiments, the main controller is configured with at least two chip select signals, and the main controller is used to select the corresponding DDR particles through the first daisy-chain structure based on different chip select signals.

[0013] In some embodiments, the main controller is further used to select the DDR particle with the longest trace length in the same first daisy-chain structure based on the chip select signal in the specified response mode.

[0014] In some embodiments, when there are two chip select signals configured by the main controller, one of the chip select signals is a high-level signal, and the other chip select signal is a low-level signal.

[0015] In some embodiments, the trace further includes Q address lines, and the address lines are a second daisy-chain structure. The Q second daisy-chain structures are used to connect the main controller and the N DDR particles, where Q is an integer greater than or equal to 1.

[0016] In some embodiments, the second daisy-chain structure is a FLY-BY structure.

[0017] According to the second aspect of the present invention, an image forming apparatus is provided, and the image forming apparatus includes the above topological structure.

[0018] Compared with the prior art, the topological structure and the image forming apparatus of the present invention can greatly improve the DATA signal quality of the multiplexed DDR particles by connecting the main controller and the DDR particles through the data line of the daisy-chain structure, and the overshoot ratio is significantly smaller than that of the T-shaped topological structure. Description of the Drawings

[0019] Figure 1 It is a module schematic diagram of a T-shaped topological structure in the prior art;

[0020] Figure 2 It is a simulation schematic diagram of a T-shaped topological structure in the prior art;

[0021] Figure 3 It is a module schematic diagram of the topological structure of the present invention;

[0022] Figure 4Schematic diagram of the topological structure of the present utility model;

[0023] Figure 5 Simulation diagram of the topological structure of the present utility model.

[0024] Explanation of the reference numerals in the attached drawings: Main controller 100, DDR memory 200, DDR1 chip 210, DDR2 chip 220, DDR3 chip 230, DDR4 chip 240, trace 300. Specific implementation mode

[0025] The present utility model will be further described in detail below with reference to the accompanying drawings.

[0026] Since the functions of current image forming apparatuses are becoming more and more diversified, there are requirements for different capacities and different speeds for the DDR (Double Data Rate SDRAM) used in the image forming apparatuses. In order to meet the requirements for different capacities and different speeds of the DDR memory, usually the same PCB (Printed Circuit Board) is used for compatible design.

[0027] In the prior art, as Figure 1 shown, usually the main controller 100 reads and writes the DDR memory 200. The main controller 100 may be a SOC (System on Chip). The DDR memory 200 includes multiple DDR chips. When there are two sets of DATA (data lines, including DATA1 and DATA2) connected to the main controller 100, and when it is necessary to externally connect 4 DDR chips or even more DDR chips, when one set of DATA multiplexes two or more DDR chips, the usual wiring method of the PCB board is that DATA takes a T-shaped topological structure.

[0028] There are obvious disadvantages in the T-shaped structure in the prior art. For the sake of easy explanation below, by way of example, taking four DDR chips as an example, as Figure 1 shown, the four DDR chips are successively the DDR1 chip 210, the DDR2 chip 220, the DDR3 chip 230, and the DDR4 chip 240; for DATA, the main controller 100 sends a Data signal through DATA. After the Data signal passes through the trace L1 to the T point (such as the reference numeral 3 in Figure 1 ), due to the multiplexing of the DDR1 chip 210 and the DDR2 chip 220 or the multiplexing of the DDR3 chip 230 and the DDR4 chip 240, when any DDR chip is selected, there will be a relatively long Stub line (such as the trace L2 in Figure 1 ). Figure 1The lengths of the traces L2 at both ends are equal. During read and write operations, large signal reflections will form overshoots, seriously affecting the signal quality and easily causing misjudgment of high and low levels when the rate is relatively high.

[0029] Using simulation software to simulate the write operation of the T-shaped topology structure in the prior art, that is, the main controller 100 sends signals and the DDR particles receive signals. Among them, the waveform diagram of the DATA signal at the DDR particle end is as Figure 2 shown, and its maximum overshoot is 158 mV.

[0030] In the prior art, when the DATA wiring adopts a T-shaped topology structure, due to the too long Stub line, signal reflection occurs, affecting the signal quality, resulting in relatively poor read and write signals of DATA regardless of which DDR particle is multiplexed; that is to say, the T-shaped topology structure of the prior art cannot meet the requirements.

[0031] According to the first aspect of the present invention, Figure 3 and Figure 4 schematically shows a topology structure according to an embodiment of the present invention, which is used to solve the problem that when multiplexing multiple DDR particles, the T-shaped topology structure of the data line will cause the Stub line to be too long, resulting in signal reflection and affecting the signal quality. As Figure 3 and Figure 4 shown, the topology structure includes a main controller 100, a DDR memory 200, and a trace 300.

[0032] The main controller 100 is an M-bit main controller 100. Since the main controller 100 usually has at least two groups of DATA, and each group of DATA needs at least 8 bits to process data, one group is the high-order DATA and the other group is the low-order DATA. Therefore, the data group composed of two groups of DATA needs at least 16 bits. For each additional data group, at least 16 bits need to be added. That is, M is a positive integer multiple of 16 and is greater than or equal to 16; in addition, for each group of DATA, 16 bits can also be used to process data. That is, when both groups of DATA use 16 bits to form a data group for processing, the corresponding M is 32 bits.

[0033] The DDR memory 200 includes N DDR particles. At least two DDR particles are connected to one group of DATA of the main controller 100, and the number of DDR particles in each group of DATA that forms a data group should be kept the same. Therefore, N is an even number greater than or equal to 4.

[0034] The trace 300 includes P data lines for transmitting data information. The data lines are in the first daisy-chain structure. The P first daisy-chain structures are used to connect the main controller 100 and N DDR chips, and at least two DDR chips are connected to one first daisy-chain structure. That is, each first daisy-chain structure (i.e., each data line) corresponds to a group of DATA of the main controller 100, and there are at least two DDR chips in each group of DATA. Since there are at least two groups of DATA lines, P is an even number greater than or equal to 2.

[0035] In this embodiment, by setting the data lines in the daisy-chain structure to connect at least two DDR chips, the multiplexing of multiple DDR chips is realized.

[0036] In an alternative embodiment, the N DDR chips are arranged on the same layer of the PCB board. Further, the N DDR chips are arranged on the same plane of the same layer of the PCB board. Exemplarily, all the N DDR chips can be arranged on the top surface / bottom surface of the PCB board. Arranging the N DDR chips on the same plane of the same layer of the PCB board facilitates the equal-length routing of data on the PCB board layout, reduces the difficulty of routing equal-length data lines on the layout, and fewer PCB board layers can be used; if they are not arranged on the same surface, the difficulty of the layout is greatly increased, and more PCB board layers need to be added. Arranging all of them on the same layer can reduce the number of PCB board layers and the cost of the PCB board.

[0037] In an alternative embodiment, as Figure 3 and Figure 4As shown, the first daisy-chain structure is a FLY-BY structure, that is, the data lines corresponding to each group of DATA of the main controller 100 (i.e., the first daisy-chain structure) are in a FLY-BY structure. For the convenience of description below, by way of example, taking the main controller 100 having two groups of DATA (i.e., DATA1 and DATA2), and each group of DATA connecting two DDR chips as an example, there are correspondingly two FLY-BY structures. The FLY-BY structure includes a trace L3, a trace L4, and a branched trace L5 of the DDR chip. The DDR chips sequentially include a DDR1 chip 210, a DDR2 chip 220, a DDR3 chip 230, and a DDR4 chip 240. Among them, the first group of DATA1 of the main controller 100 is connected to the traces of the DDR1 chip 210 and the DDR2 chip 220 in series, that is, the main controller 100 is connected to the DDR2 chip 220 through the trace L3, and the DDR2 chip 220 is connected to the DDR1 chip 210 through the trace L4. The trace L5 is a stub line generated due to process reasons, and the length of the trace L5 should be controlled within 30 mil. Similarly, the connection of the second group of DATA2 of the main controller 100 to the DDR3 chip 230 and the DDR4 chip 240 can refer to the connection of the first group of DATA1 of the main controller 100 to the DDR1 chip 210 and the DDR2 chip 220.

[0038] In an alternative embodiment, the main controller 100 is configured with at least two chip select signals. The main controller 100 is used to select the corresponding DDR chip through the first daisy-chain structure based on different chip select signals, so that the DDR chip corresponding to the chip select signal is selected. That is, the main controller 100 configures the chip select signals according to the number of DDR chips connected by the first daisy-chain structure, so that each chip select signal corresponds to a DDR chip, so that the main controller 100 transmits the chip select signal to the corresponding DDR chip through the first daisy-chain structure and selects the corresponding DDR chip. For the convenience of description below, by way of example, taking the main controller 100 having two groups of DATA (i.e., DATA1 and DATA2), and each group of DATA connecting two DDR chips through the FLY-BY structure as an example, as Figure 3 and Figure 4As shown, the main controller 100 includes two chip select signals, specifically the first chip select signal and the second chip select signal. The DDR particles sequentially include DDR1 particles 210, DDR2 particles 220, DDR3 particles 230, and DDR4 particles 240. When it is necessary to multiplex the DDR1 particles 210 or DDR2 particles 220 connected to the first group of DATA1 of the main controller 100, the main controller 100 sends the first chip select signal to the DDR1 particles 210 through the first group of DATA1 to select the DDR1 particles 210, or sends the second chip select signal to the DDR2 particles 220 through the first group of DATA1 to select the DDR2 particles 220. Similarly, when it is necessary to multiplex the DDR3 particles 230 or DDR4 particles 240 connected to the second group of DATA2 of the main controller 100, the main controller 100 sends the second chip select signal to the DDR3 particles 230 through the second group of DATA2 to select the DDR3 particles 230, or sends the first chip select signal to the DDR4 particles 240 through the second group of DATA2 to select the DDR4 particles 240.

[0039] Further, when the main controller 100 performs a write operation on the DDR1 particles 210, the main controller 100 sends the first chip select signal to the DDR1 particles 210 through the first group of DATA1 to select the DDR1 particles 210, and closes the DDR2 particles 220. The main controller 100 sends a write signal, and the DDR1 particles 210 receive the write signal to perform the write operation. When the main controller 100 performs a read operation on the DDR1 particles 210, the main controller 100 sends the first chip select signal to the DDR1 particles 210 through the first group of DATA1 to select the DDR1 particles 210, and closes the DDR2 particles 220. The DDR1 particles 210 send a read signal, and the main controller 100 receives the read signal. Correspondingly, when the main controller 100 performs a read / write operation on the DDR2 particles 220, the main controller 100 sends the second chip select signal to the DDR2 particles 220 through the first group of DATA1 to select the DDR2 particles 220, and closes the DDR1 particles 210 to perform the read / write operation. Similarly, when the main controller 100 performs a read / write operation on the DDR4 particles 240, the main controller 100 sends the first chip select signal to the DDR4 particles 240 through the second group of DATA2 to select the DDR4 particles 240, and closes the DDR3 particles 230 to perform the read / write operation. When the main controller 100 performs a read / write operation on the DDR3 particles 230, the main controller 100 sends the second chip select signal to the DDR3 particles 230 through the second group of DATA2 to select the DDR3 particles 230, and closes the DDR4 particles 240 to perform the read / write operation.

[0040] When the main controller 100 multiplexes the first chip select signal to the DDR1 particle 210 through the first group of DATA1, or multiplexes the first chip select signal to the DDR4 particle 240 through the second group of DATA2, whether it is performing a write or read operation, there will inevitably be Stub lines (i.e., Figure 3 and Figure 4 of the trace L5) in the entire link. The trace L5 is shorter than the trace L2 of Figure 1 , and the signal reflection will be smaller; using simulation software to perform simulations under the same conditions, that is, the main controller 100 sends signals and the DDR particle receives signals. The waveform diagram of the DATA signal at the DDR particle end is as shown in Figure 5 , and its maximum overshoot is 43 mV. The topological structure of this embodiment can greatly improve the DATA signal quality of the multiplexed DDR particles, and the overshoot is significantly smaller than the maximum overshoot of 158 mV of the T-shaped topological structure in the prior art.

[0041] In an alternative embodiment, when the main controller 100 configures two chip select signals, one of the chip select signals is a high-level signal, and the other chip select signal is a low-level signal. That is, when the number of DDR particles connected by the first daisy chain structure (such as the FLY-BY structure) is two, it means that only two chip select signals are required to complete the selection control of the two DDR particles. At this time, one of the chip select signals can be configured as a high-level signal, and the other chip select signal can be configured as a low-level signal. When the main controller 100 sends a high-level signal through this first daisy chain structure, one of the DDR particles connected by this first daisy chain structure is selected. On the contrary, when the main controller 100 sends a low-level signal through this first daisy chain structure, the other DDR particle connected by this first daisy chain structure is selected.

[0042] In an alternative embodiment, the main controller 100 is further configured to select the DDR particle with the longest trace length in the same first daisy chain structure based on the chip select signal in a specified response mode, so that the DDR particle is selected. The specified response mode is the high-speed response mode. That is, when the main controller 100 enters the high-speed response mode, since the signal quality of the DDR particle with the longest trace length in the same first daisy chain structure is the best in this first daisy chain structure, the main controller 100 transmits the chip select signal corresponding to this DDR particle to this DDR particle through this first daisy chain structure to select this DDR particle; for the convenience of description below, by way of example, taking the main controller 100 having two groups of DATA (i.e., DATA1 and DATA2), and each group of DATA connecting two DDR particles through the FLY-BY structure as an example, as shown in Figure 3 and Figure 4As shown, the DDR particles include DDR1 particles 210, DDR2 particles 220, DDR3 particles 230, and DDR4 particles 240. The DDR1 particles 210 and DDR4 particles 240 have the longest trace lengths in their respective first daisy-chain structures. After the DDR1 particles 210 and DDR4 particles 240 are selected, their interfering traces are trace L5, while after the DDR2 particles 220 and DDR3 particles 230 are selected, their interfering traces are trace L4. Trace L5 is shorter than trace L4. Therefore, the DDR1 particles 210 and DDR4 particles 240 have the best signal quality in their respective first daisy-chain structures. Thus, when the main controller 100 enters the high-speed response mode, the main controller 100 can send the first chip select signal to the DDR1 particles 210 through the first group of DATA1 to select the DDR1 particles 210, and / or send the first chip select signal to the DDR4 particles 240 through the second group of DATA2 to select the DDR4 particles 240, that is, the main controller 100 can select the DDR1 particles 210 or the DDR4 particles 240, or select both the DDR1 particles 210 and the DDR4 particles 240 at the same time. In addition, when the main controller 100 enters the low-speed response mode, the main controller 100 can select any one or more of the DDR1 particles 210, DDR2 particles 220, DDR3 particles 230, and DDR4 particles 240.

[0043] In an alternative embodiment, a large-capacity DDR memory 200 can be composed by using multiple small-capacity DDR particles. Exemplarily, taking four DDR particles as an example, when the capacity of the DDR memory 200 is 512M, four 128M-capacity DDR particles can be used; when the capacity of the DDR memory 200 is 1GB, four 256M-capacity DDR particles can be used; when the capacity of the DDR memory 200 is 2GB, four 512M-capacity DDR particles can be used; when the capacity of the DDR memory 200 is 4GB, four 1GB-capacity DDR particles can be used. Of course, the capacities of each DDR particle can also be different and can be combined according to actual requirements. By using multiple small-capacity DDR particles to compose various large-capacity DDR memories 200, the cost of the image forming apparatus can be reduced; at the same time, multiple small-capacity DDR particles are used on one PCB board, which can meet the different memory requirements of different image forming apparatus models.

[0044] In an alternative embodiment, the trace 300 further includes Q address lines for transmitting address information. The address lines form a second daisy-chain structure, and the Q second daisy-chain structures are used to connect the main controller 100 and N DDR chips. The second daisy-chain structure is a FLY-BY structure. The number of address lines can be determined according to the number of address lines that the main controller 100 can connect. When the number of address lines that the main controller 100 can connect is one, the main controller 100 and N DDR chips are connected by one FLY-BY structure. When the number of address lines that the main controller 100 can connect is greater than one, the main controller 100 and N DDR chips can be connected by multiple FLY-BY structures. Therefore, Q is an integer greater than or equal to 1.

[0045] According to a second aspect of the present invention, there is provided an image forming apparatus including the above-described topology. The image forming apparatus is configured to perform image forming operations such as scanning, generating, printing, receiving, and transmitting image data. Examples of the image forming apparatus include printers with scanning functions, scanners, copiers, fax machines, and multi-functional peripherals (MFPs) that perform the above functions in a single device.

[0046] The above are only some embodiments of the present invention. For those of ordinary skill in the art, without departing from the creative concept of the present invention, several modifications and improvements can be made, and these all fall within the protection scope of the present invention.

Claims

1. A topological structure, characterized in that, Comprising: A main controller; N DDR particles, where N is an even number greater than or equal to 4; Trace lines, the trace lines include P data lines, the data lines are in a first daisy-chain structure, and the P first daisy-chain structures are used to connect the main controller and the N DDR particles, and at least one of the first daisy-chain structures is connected to at least two of the DDR particles, where P is an even number greater than or equal to 2.

2. The topological structure according to claim 1, characterized in that, The first daisy-chain structure is a FLY-BY structure.

3. The topological structure according to claim 1, characterized in that, The N DDR particles are arranged on the same layer of the PCB board.

4. The topological structure according to claim 3, characterized in that, The N DDR particles are arranged on the same plane of the same layer of the PCB board.

5. The topological structure according to any one of claims 1-4, characterized in that, The main controller is configured with at least two chip select signals, and the main controller is used to select the corresponding DDR particles through the first daisy-chain structure based on different chip select signals.

6. The topological structure according to claim 5, characterized in that The main controller is further used to select the DDR particle with the longest trace line length in the same first daisy-chain structure based on the chip select signal in a specified response mode.

7. The topology according to claim 5, characterized in that, When there are two chip select signals configured by the main controller, one of the chip select signals is a high-level signal, and the other chip select signal is a low-level signal.

8. The topological structure according to any one of claims 1-4, characterized in that, The trace lines further include Q address lines, the address lines are in a second daisy-chain structure, and the Q second daisy-chain structures are used to connect the main controller and the N DDR particles, where Q is an integer greater than or equal to 1.

9. The topological structure according to claim 8, wherein The second daisy-chain structure is a FLY-BY structure.

10. An image forming apparatus, characterized in that, Comprising the topology structure according to any one of claims 1-9.

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