Memristor chip testing device
Through the modularly designed memristor chip test device, the problem of inconvenient replacement of ADC and DAC circuit modules is solved, convenient replacement and expansion are achieved, and chip testing costs are reduced.
Patent Information
- Application Number
- CN202421202958.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-29
- Publication Date
- 2025-08-01
- Estimated Expiration
- 2034-05-29
AI Technical Summary
In traditional memristor chip testing solutions, ADC and DAC circuit modules are inconvenient to replace, resulting in low scalability of the test solution and increasing the chip testing cost.
The memristor chip test device adopts a modular design, including ADC board, DAC board, logic computing board and PXIe chassis, is connected through PCIe2.0 X4, and supports modular replacement and expansion to meet different testing needs.
It realizes convenient replacement of DAC and ADC boards, reduces chip testing costs, and supports diverse chip testing, which is highly scalable.
Smart Images
Figure CN223180342U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of memristor testing, and particularly to a memristor chip testing device. Background Art
[0002] A memristor (Resistive Random Access Memory, Non-volatile Memory, abbreviated as: RRAM) is a new emerging memory technology that competes with mainstream dynamic random access memory DRAM and flash memory FLASH. The difference between RRAM and mainstream storage technologies is that data is stored according to resistance rather than charge, which means that RRAM is not subject to scaling limitations related to charge storage. In addition, RRAM is a non-volatile memory NVM, with advantages such as high memory density, low power consumption, and compatibility with the backend line of standard complementary metal oxide semiconductor processes.
[0003] In large-scale memristor chip and other chip tests, due to the need to perform read / write operations and measurements of various weights, various ADC and DAC circuit modules are often used in weight read / write and measurement. The traditional design scheme is to mount ADC, DAC, and the test chip on the same PCBA according to specific test requirements. However, it is inconvenient to replace ADC, DAC, and the chip under test, and the scalability of the test scheme is relatively low. For new test requirements, a new test PCBA board needs to be designed, increasing the cost of chip testing. Summary of the Utility Model
[0004] Based on this, it is necessary to provide a memristor chip testing device for the above technical problems.
[0005] A memristor chip testing device includes: an ADC board, a DAC board, a logic calculation board, and a PXIe chassis.
[0006] The ADC board, the DAC board, and the logic calculation board are installed inside the PXIe chassis and are directly connected to the PXIe chassis backplane through PCIe2.0 X4; the ADC board, the DAC board, and the logic calculation board are connected by cables.
[0007] A connector for connecting the socket board of the chip under test is provided on the logic calculation board; the socket board of the chip under test is installed on the logic calculation board through the connector, and the chip under test is inserted into the socket board of the chip under test; the logic calculation board communicates with the host computer through a communication interface.
[0008] In one embodiment, the socket board of the chip under test is stacked and installed with the logic calculation board through the connector.
[0009] In one embodiment, the ADC board, the DAC board, and the logic calculation board are connected via SMA cables.
[0010] In one embodiment, the PXIe chassis is a PXIe 3U chassis.
[0011] In one embodiment, the ADC board includes an FPGA module, several ADC modules, several current acquisition circuits, and several single-ended to differential amplification circuits; the current acquisition circuits and the single-ended to differential amplification circuits are connected one-to-one.
[0012] The input end of each current acquisition circuit is used to receive the calculation result signal output by the input logic calculation board in the form of analog current. The output end of the current acquisition circuit is connected to the input section of a single-ended to differential amplification circuit. The output end of the single-ended to differential amplification circuit is connected to one input end of the ADC module; the output section of the ADC module is connected to the input end of the FPGA module; the FPGA module is connected to the PXIe chassis backplane via the PCIE bus.
[0013] In one embodiment, the DAC board includes: a first FPGA module, several DAC modules, several filtering modules, and several comparators; the filtering modules and the comparators are connected one-to-one; one DAC module is connected to two filtering modules.
[0014] The first FPGA module is connected to the PXIe chassis backplane via the PCIE bus. The output end of the first FPGA module is connected to the input end of the DAC module. The output end of the DAC module is connected to the input end of the filtering module. The output end of the filtering module is connected to the input end of the comparator. The output end of the comparator is used to output the logic calculation excitation signal for chip testing.
[0015] In one embodiment, the logic calculation board further includes: a second FPGA module, a strobe switch array, a write weight circuit, a read weight circuit, a clock circuit, a power supply, a bias circuit, and a communication interface module.
[0016] The strobe switch array, the write weight, and the read weight circuits are all connected to the second FPGA module. The bias circuit, the write weight, and the read weight circuits are all connected to the strobe switch array. The input end of the strobe switch array is connected to the input logic calculation excitation signal. The output end of the strobe switch array outputs the calculation result signal in the form of analog current to the ADC board; the strobe switch array is connected to the chip under test via a connector;
[0017] The second FPGA module is connected to the communication interface module; the logic calculation board is connected to the PXIe chassis backplane via the PCIE bus, and the logic calculation board is connected to the host computer via the communication interface module.
[0018] The power supply module is used to supply power to the second FPGA module, the gating switch array, the weight writing circuit, the weight reading circuit, the bias circuit, the clock circuit, and the communication interface module.
[0019] The clock circuit is used to provide clock signals to the weight writing circuit and the weight reading circuit.
[0020] The above-mentioned memristor chip testing device, the testing device includes: an ADC board, a DAC board, a logic calculation board, and a PXIe chassis. The ADC board, the DAC board, and the logic calculation board are installed inside the PXIe chassis and are directly connected to the backplane of the PXIe chassis through PCIe2.0 X4; the ADC board, the DAC board, and the logic calculation board are connected by cables. A connector for connecting the socket board of the chip under test is provided on the logic calculation board; the socket board of the chip under test is installed on the logic calculation board through the connector, and the chip under test is inserted into the socket board of the chip under test; the logic calculation board communicates with the host computer through a communication interface. The device adopts a modular design, and the DAC board, the ADC board, and the chip under test can be conveniently replaced, facilitating expansion. Different test schemes can be combined for different chips under test. In addition, a certain module can be conveniently upgraded and expanded, reducing the chip testing cost. Description of the Drawings
[0021] Figure 1 Schematic diagram of the board connection mode of the memristor chip testing device in one embodiment;
[0022] Figure 2 Three-dimensional structure diagram of the memristor chip testing device in another embodiment;
[0023] Figure 3 Block diagram of the ADC board in another embodiment;
[0024] Figure 4 Block diagram of the DAC board in another embodiment. Detailed Embodiment
[0025] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0026] Considering the diversity of the chip under test and the scalability of each functional module, in this application, the ADC, DAC, logic calculation gating switch, and the chip under test are modularly designed, changing a set of measurement circuits that require 6U and 3 slots into a 3U 3-slot measurement circuit. Each module is connected through a high-speed connector. At the same time, the DAC, ADC, and the chip under test can be easily replaced for easy expansion. Different test schemes are combined for different chips under test.
[0027] In one embodiment, as Figure 1 shown, a memristor chip test device is provided. The memristor chip test device includes: an ADC board 10, a DAC board 20, a logic calculation board 30, and a PXIe chassis 40.
[0028] The ADC board 10, the DAC board 20, and the logic calculation board 30 are installed on the slots of the PXIe chassis 40 and are directly connected to the PXIe chassis backplane through PCIe2.0 X4; the ADC board 10, the DAC board 20, and the logic calculation board 30 are connected by cables.
[0029] A connector for connecting the socket board of the chip under test is provided on the logic calculation board 30; the socket board of the chip under test is installed on the logic calculation board 30 through the connector, and the chip under test is inserted on the socket board of the chip under test; the logic calculation board 30 communicates with the host computer through a communication interface.
[0030] Among them, the logic calculation board 30 includes a carrier board and a daughter board. The socket board of the chip under test is pluggably installed on the connector of the socket board of the chip under test on the carrier board, and the carrier board is connected to the daughter board through the connector. The carrier board, the daughter board, and the chip under test are in a stacked form. Specifically, the carrier board and the daughter board of the logic calculation board 30 are stacked together through three Panasonic AXK connectors, and the main function is to gate and calculate 32X32-channel memristor measurement signals.
[0031] The ADC board 10, the DAC board 20, and the logic calculation board 30 are installed in the PXIe chassis 40, and the ADC board 10, the DAC board 20, and the logic calculation board 30 are directly connected to the backplane through PCIe2.0 X4. The ADC board 10, the DAC board 20, and the logic calculation board 30 are connected by SMA cables. This structure can facilitate the upgrade and expansion of one of the boards.
[0032] The DAC board 10 is mainly used to generate pulse signals. Pulse signals with different amplitudes flow through the memristor and generate different currents to be measured. The ADC board is mainly used to measure the weight value of the memristor, and the ADC board 20 is used to measure the current of the DAC pulse signal flowing through the memristor.
[0033] The three-dimensional structure diagram of the memristor chip test device is as follows Figure 2 shown.
[0034] The test functions of the memristor chip test device include read operation test and write operation test. The process of the read operation test is as follows: The DAC board sends a pulse signal of 0.2V and about 2ms, and at the same time, the logic calculation board performs row and column selection on the memristor, so that this pulse signal will be sent to the specified row and column of the memristor. The logic calculation board then sends the calculated analog signal to the ADC board, and the ADC board performs analog-to-digital conversion, and then outputs the read operation test of the memristor chip. The write operation speed measurement process is similar to the read operation speed measurement process. According to the different resistance values of the memristor device, the pulse signal of the DAC is adjusted.
[0035] In the above-mentioned memristor chip test device, the test device includes: an ADC board, a DAC board, a logic calculation board, and a PXIe chassis. The ADC board, the DAC board, and the logic calculation board are installed in the PXIe chassis and are directly connected to the backplane of the PXIe chassis through PCIe2.0 X4; the ADC board, the DAC board, and the logic calculation board are connected by cables. A connector for connecting the socket board of the chip to be tested is provided on the logic calculation board; the socket board of the chip to be tested is installed on the logic calculation board through the connector, and the chip to be tested is inserted into the socket board of the chip to be tested; the logic calculation board communicates with the upper computer through a communication interface. The device adopts a modular design, and the DAC board, the ADC board, and the chip under test can be easily replaced, which is convenient for expansion. Different test schemes can be combined for different chips under test. In addition, a certain module can be easily upgraded and expanded, reducing the chip test cost.
[0036] In one embodiment, the socket board of the chip to be tested is stacked and installed with the logic calculation board through a connector.
[0037] In one embodiment, the ADC board, the DAC board, and the logic calculation board are connected by SMA cables.
[0038] In one embodiment, the PXIe chassis is a PXIe 3U chassis.
[0039] In one embodiment, the ADC board includes an FPGA module, a plurality of ADC modules, a plurality of current acquisition circuits, and a plurality of single-ended to differential amplification circuits; the current acquisition circuits and the single-ended to differential amplification circuits are connected one-to-one. The input end of each current acquisition circuit is used to receive the calculation result signal output in the form of analog current by the input logic calculation board. The output end of the current acquisition circuit is connected to the input section of a single-ended to differential amplification circuit, and the output end of the single-ended to differential amplification circuit is connected to one input end of the ADC module; the output section of the ADC module is connected to the input end of the FPGA module; the FPGA module is connected to the PXIe chassis backplane through the PCIE bus.
[0040] Specifically, the block diagram of the ADC board is as Figure 3 shown. The ADC board includes two ADC modules, four current acquisition circuits, and four single-ended to differential amplification circuits. Each ADC module includes two acquisition channels, and each acquisition channel is connected to a current acquisition circuit and a single-ended to differential amplification circuit. The signal acquisition process of the ADC board is as follows: the input current signals (such as ADC_IN1 to ADC_IN4) are first sampled by the sampling resistors in the current acquisition circuits to be converted into voltage signals, and then amplified by the existing single-ended to differential amplification circuits at their rear ends, and then sent to the ADC modules of the ADC board for acquisition.
[0041] The ADC board uses a current acquisition method with sampling resistors.
[0042] In one embodiment, the DAC board includes: a first FPGA module, a plurality of DAC modules, a plurality of filtering modules, and a plurality of comparators; the filtering modules and the comparators are connected one-to-one; one DAC module is connected to two filtering modules; the first FPGA module is connected to the PXIe chassis backplane through the PCIE bus. The output end of the first FPGA module is connected to the input end of the DAC module, the output end of the DAC module is connected to the input end of the filtering module, the output end of the filtering module is connected to the input end of the comparator, and the output end of the comparator is used to output a logic calculation excitation signal for chip testing.
[0043] Specifically, the block diagram of the DAC board is as Figure 4 shown. The DAC board can use the existing (DAC) driver high-power op-amp pulse card, which has a filtering circuit and a comparator. One DAC driver high-power op-amp pulse card includes two-way pulse outputs. 4 DAC driver high-power op-amp pulse cards can be set on the DAC board, which can drive 8-way pulse outputs simultaneously. The 8-way pulse outputs are divided into 4 pairs, and each pair is responsible for programming pulses (i.e., pulse DAC_SET) and grid voltage control pulses (DAC_GATE) for the output devices of one array card 14.
[0044] In one of the embodiments, the logic computing board further includes: a second FPGA module, a strobe switch array, a write weight circuit, a read weight circuit, a clock circuit, a power supply, a bias circuit, and a communication interface module; the strobe switch array, the write weight circuit, and the read weight circuit are all connected to the second FPGA module, the bias circuit, the write weight circuit, and the read weight circuit are all connected to the strobe switch array, the input end of the strobe switch array is connected to the input logic computing excitation signal, and the output end of the strobe switch array outputs a computing result signal output in the form of an analog current to the ADC board; the strobe switch array is connected to the chip under test through a connector; the second FPGA module is connected to the communication interface module; the logic computing board is connected to the PXIe chassis backplane through a PCIE bus, and the logic computing board is connected to the host computer through the communication interface module; the power supply module is used to supply power to the second FPGA module, the strobe switch array, the write weight circuit, the read weight circuit, the bias circuit, the clock circuit, and the communication interface module; the clock circuit is used to provide a clock signal to the write weight circuit and the read weight circuit.
[0045] Specifically, the logic computing board is mainly responsible for switching the external DAC_SET and DAC_GATE to the selected rows, columns, and gates of the array, and at the same time outputting the current flowing through the selected memristors to the external ADC_IN for acquisition. In addition to the above functions, it also needs to be responsible for performing parallel computing operations. One logic computing card supports carrying a maximum of 4K (64 rows and 64 columns) of memristor arrays at most. One parallel computing can access 1K arrays (32 rows and 32 columns) to participate in the operation at the same time. 32 excitation signals are generated by 32 parallel high-speed DACs, and can send pulse waveforms, PWM waves, stepped waveforms, triangular waves, and custom waveforms. The output converging current signal flowing through the memristors is amplified by an instrumentation amplifier and then sent to a 32-channel high-speed ADC for acquisition, and the acquired current signal is sent back to the host computer through a PCIE interface.
[0046] The on-board strobe switch, excitation signal generation circuit, computing result measurement circuit, write weight circuit, and read weight circuit are all controlled by the FPGA control core. In order to enable the logic computing board to communicate with the host computer, a PCIe communication interface is provided on the board. The clocks of the on-board measurement circuit, excitation generation circuit, write weight circuit, and read weight circuit are provided by the clock circuit.
[0047] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0048] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims
1. A memristor chip testing device, characterized in that, The memristor chip test device includes: an ADC board, a DAC board, a logic calculation board, and a PXIe chassis; The ADC board, the DAC board, and the logic calculation board are installed inside the PXIe chassis and are directly connected to the PXIe chassis backplane through PCIe2.0 X4; the ADC board, the DAC board, and the logic calculation board are connected by cables; A connector for connecting to the socket board of the chip under test is provided on the logic calculation board; the socket board of the chip under test is installed on the logic calculation board through the connector, and the chip under test is inserted into the socket board of the chip under test; the logic calculation board communicates with the host computer through a communication interface.
2. The memristor chip testing device according to claim 1, characterized in that The socket board of the chip under test is stacked and installed with the logic calculation board through the connector.
3. The memristor chip testing device according to claim 1, wherein, The ADC board, the DAC board, and the logic calculation board are connected by SMA cables.
4. The memristor chip testing device according to claim 1, wherein The PXIe chassis is a PXIe 3U chassis.
5. The memristor chip testing device according to claim 1, wherein The ADC board includes an FPGA module, a plurality of ADC modules, a plurality of current acquisition circuits, and a plurality of single-ended to differential amplification circuits; the current acquisition circuits and the single-ended to differential amplification circuits are connected one-to-one; The input end of each current acquisition circuit is used to receive the calculation result signal output in the form of analog current from the input logic calculation board. The output end of the current acquisition circuit is connected to the input section of a single-ended to differential amplification circuit. The output end of the single-ended to differential amplification circuit is connected to an input end of the ADC module; the output section of the ADC module is connected to the input end of the FPGA module; the FPGA module is connected to the PXIe chassis backplane through the PCIE bus.
6. The memristor chip testing device according to claim 1, characterized in that, The DAC board includes: a first FPGA module, a plurality of DAC modules, a plurality of filtering modules, and a plurality of comparators; the filtering modules and the comparators are connected one-to-one; one DAC module is connected to two filtering modules; The first FPGA module is connected to the PXIe chassis backplane through the PCIE bus. The output end of the first FPGA module is connected to the input end of the DAC module. The output end of the DAC module is connected to the input end of the filtering module. The output end of the filtering module is connected to the input end of the comparator. The output end of the comparator is used to output a logic calculation excitation signal for chip testing.
7. The memristor chip testing device according to claim 6, characterized in that, The logic calculation board further includes: a second FPGA module, a strobe switch array, a write weight circuit, a read weight circuit, a clock circuit, a power supply, a bias circuit, and a communication interface module; The strobe switch array, the write weight, and the read weight circuits are all connected to the second FPGA module. The bias circuit, the write weight, and the read weight circuits are all connected to the strobe switch array. The input end of the strobe switch array is connected to the input logic calculation excitation signal. The output end of the strobe switch array outputs a calculation result signal in the form of analog current to the ADC board; The gating switch array is connected to the chip under test through the connector; The second FPGA module is connected to the communication interface module; the logic computing board is connected to the PXIe chassis backplane through the PCIE bus, and the logic computing board is connected to the host computer through the communication interface module; The power supply is used to supply power to the second FPGA module, the gating switch array, the write weight circuit, the read weight circuit, the bias circuit, the clock circuit, and the communication interface module; The clock circuit is used to provide clock signals to the write weight circuit and the read weight circuit.