Passive device of semiconductor substrate and semiconductor device

Abstract

The utility model provides a passive device or semiconductor substrate and a manufacturing method thereof. The passive device includes first and second upper metal elements on a substrate core having an insulator substrate, a passivation layer formed on the metal elements and the insulator substrate, a first conductive element formed on the passivation layer and in electrical contact with the first upper metal element; and a second conductive element formed on the passivation layer and in electrical contact with the second upper metal element. In addition, the device includes an insulating material formed over the first conductive element and the second conductive element. The insulating material between the first conductive element and the second conductive element defines a recess. The device further includes an asin build-up film plug element formed in a recess between the first conductive element and the second conductive element.

Description

Technical Field

[0001] The present disclosure relates to a method for forming an Ajinomoto build-up film (ABF) plug element in a semiconductor device, a passive device of a semiconductor substrate, and a semiconductor device. Background Art

[0002] The packaging of integrated circuits has become increasingly complex, with more device dies being packaged in the same package to achieve more functions. For example, a system-integrated on-chip (SoIC) has been developed to include multiple device dies (such as processors) and memory cubes in the same package. The SoIC may include device dies with different functions formed using different technologies, bonded to the same device die, interconnected vias, different bonding contacts, and mounted on a substrate to form a system. The substrate may be multi-layered and include one or more active or passive components. This can save manufacturing costs and optimize device performance. Summary of the Utility Model

[0003] According to some embodiments of the present disclosure, a method for forming an Ajinomoto build-up film (ABF) plug element in a semiconductor device. At least one upper metal element is formed on a substrate core including an insulating substrate. A passivation layer is formed on the at least one upper metal element and the insulating substrate. At least one conductive element of a passive device is formed on the passivation layer, and the at least one conductive element is in electrical contact with the at least one upper metal element. An insulating material is deposited on the substrate core, where the insulating material is deposited on a part of the at least one conductive element and the passivation layer. The insulating material is patterned to define a groove adjacent to the at least one conductive element. An Ajinomoto build-up film (ABF) material is deposited on the insulating material to form an ABF plug element.

[0004] According to some embodiments of the present disclosure, a passive device of a semiconductor substrate. The passive device includes first and second upper metal elements located on a substrate core including an insulator substrate, and a passivation layer formed on the first upper metal element, the second upper metal element, and the insulating substrate. The device further includes a first conductive element formed on the passivation layer and in electrical contact with the first upper metal element, and a second conductive element formed on the passivation layer and in electrical contact with the second upper metal element. Additionally, the device includes an insulating material formed on the first conductive element and the second conductive element. The insulating material between the first conductive element and the second conductive element defines a groove. The device further includes an ABF plug element formed in the groove between the first conductive element and the second conductive element.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a substrate having at least one passive device element, wherein the at least one passive device element includes a first conductive element and a second conductive element. Additionally, the at least one passive device element further includes an ABF plug element located between the first and second conductive elements. The semiconductor device further includes a system-on-chip (SoC), components, a first dynamic random access memory element, and a second dynamic random access memory element. The system-on-chip (SoC), components, the first dynamic random access memory element, and the second dynamic random access memory element are electrically coupled to the substrate.

[0006] To make the above features and advantages of the present disclosure more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased. [[ID=�]]

[0008] Figure 1 is an exemplary semiconductor device in accordance with some embodiments.

[0009] Figure 2 is a cross-sectional view of a passive element in accordance with some embodiments.

[0010] Figure 3 is in accordance with some embodiments Figure 3 top view of the passive element of

[0011] Figure 4 is a top view of an array of passive elements in accordance with some embodiments.

[0012] Figures 5A - 5B is Figure 4 top view and cross-sectional view of a portion of the array of

[0013] Figures 6A - 6M is a series of simplified cross-sectional views of an intermediate manufacturing stage of a conductive element and a passive device element in accordance with some embodiments.

[0014] Figures 7A - 7E is a series of cross-sectional views of an intermediate manufacturing stage of an array of passive elements in accordance with some embodiments.

[0015] Figures 8A - 8D is a cross-sectional view of manufacturing a substrate including a passive element using an ABF plug element in accordance with an exemplary embodiment.

[0016] Figures 9A - 9B is a top view and cross-sectional view of a second embodiment of an ABF plug element in accordance with an embodiment.

[0017] Figures 10A - 10B It is a top view and a sectional view of a third embodiment of an ABF plug element according to an embodiment.

[0018] Figures 11A - 11B It is a top view and a sectional view of a fourth embodiment of an ABF plug element according to an embodiment.

[0019] Figures 12A - 12B It is a top view and a sectional view of a fifth embodiment of an ABF plug element according to an embodiment.

[0020] Figures 13A - 13B It is a top view and a sectional view of a sixth embodiment of an ABF plug element according to an embodiment.

[0021] Figure 14 It is a flowchart showing a method of manufacturing a semiconductor device according to some embodiments.

[0022] Description of Reference Numerals

[0023] 100: Semiconductor device

[0024] 102: Substrate

[0025] 104: System-on-chip element, SoC element

[0026] 106: First dynamic random access memory element, first DRAM element

[0027] 108: Second dynamic random access memory element, second DRAM element

[0028] 110: Ball grid array, BGA

[0029] 112: Top surface

[0030] 114: Bottom surface

[0031] 116: Insulating core, substrate core

[0032] 118: Upper ABF layer, ABF layer, ABF material

[0033] 120: Lower ABF layer

[0034] 122: Passive device element, passive element

[0035] 124: SoC underfill

[0036] 126: SoC post or contact

[0037] 128: SoC solder element

[0038] 130: DRAM substrate

[0039] 132: DRAM bump

[0040] 136: Ajinomoto build-up film plug element, ABF plug element

[0041] 138: First passive device conductive element, first conductive element, conductive element

[0042] 140: Second passive device conductive element, second conductive element, conductive element

[0043] 138, 184, 190, 196, 202, 208: First conductive element

[0044] 140, 186, 192, 198, 204, 210: Second conductive element

[0045] 142: Passivation layer

[0046] 143: Insulating substrate

[0047] 144: Through hole

[0048] 146: Upper metal element

[0049] 148: Insulating material

[0050] 149: Groove

[0051] 158: Connection pin

[0052] 168: Array

[0053] 170: Seed layer

[0054] 172: Photoresist

[0055] 174: Metal layer

[0056] 176: Second metal layer

[0057] 178: Through hole

[0058] 180: Solder mask layer

[0059] 194, 200, 206: ABF plug element

[0060] 1400: Method

[0061] 1402 - 1422: Steps

[0062] d, 156: Thickness

[0063] D1, D1’: Length

[0064] D2, D2’: Width

[0065] T1, 150: Lower insulation opening

[0066] T2, 152: Upper insulation opening, distance

[0067] θ, 154: Angle Detailed implementation manners

[0068] The following disclosure provides a plurality of different embodiments or examples for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course, these elements and arrangements are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and more particularly may include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0069] In addition, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Except for the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive words used herein may be interpreted accordingly.

[0070] The numerical values in the specification and claims of this application should be understood to include the same values when reduced to the same significant digits and values that differ from the said value by less than the experimental error of the conventional measurement techniques used to determine the value of the type described in this application.

[0071] The term "about" may be used to include any numerical value that can vary without changing the basic function of the value. When used with a range, "about" more particularly discloses the range defined by the absolute values of the two endpoints. For example, "about 2 to about 4" also discloses the range "from 2 to 4". The term "about" may mean plus or minus 10% of the specified number.

[0072] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure or can have a scope less than that of the underlying or overlying structure. Additionally, a layer can be a region of a uniform or non-uniform continuous structure, the thickness of which is less than that of the continuous structure. For example, a layer can be located between any pair of horizontal planes at or between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and contact layers (in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0073] A substrate for semiconductor manufacturing can be made of multiple layers, such as a passivation layer, a polyimide layer, a conductive layer, other dielectric layers, etc., and can further include various passive components formed within the layers. In some embodiments, electrodes of one or more passive components are formed on the passivation layer of the substrate. Generally, a polyimide material is deposited or formed between these electrodes of the passive components. During the process of manufacturing a semiconductor substrate, various materials are used to form the substrate, and each material may require different processes, temperatures, and environments. In some cases, a change in temperature may cause the polyimide material to delaminate from the electrode material or the passivation layer. In other cases, due to the stress imposed by temperature or material changes, dendrites of the electrode material may form under the polyimide material. Covering this combination of the polyimide material and the passive component electrodes is a build-up layer, such as an Ajinomoto Build-up Film ("ABF"), which is a material commonly used in substrate manufacturing. This ABF material is an insulating layer that generally includes a combined organic epoxy resin, a hardener, and inorganic particulate fillers. As will be understood, this curing of the ABF material is more likely to have a negative impact on the interface between the polyimide material and the electrode material and / or the passivation layer. In some embodiments proposed herein, ABF plug elements are used to improve the formation of dendrites and / or the delamination of the polyimide.

[0074] Now referring to Figure 1 , there is shown a semiconductor device 100 that includes a substrate 102, a system on chip (SoC) element 104, a first dynamic random access memory (DRAM) element 106, a second dynamic random access memory element 108, and a ball grid array (BGA) 110. It should be understood that Figure 1 the illustration in Figures 2 to 3(discussed in more detail below). That is, the exemplary semiconductor device 100 represents any semiconductor device that uses the substrate 102 incorporating the ABF plug element 136 of the present disclosure.

[0075] As Figure 1 shown, the substrate 102 includes a top surface 112 and a bottom surface 114. As described below, the system-on-chip element 104, the first dynamic random access memory element 106, and the second dynamic random access memory element 108 are coupled to the top surface 112 of the substrate 102. As Figure 1 shown, the bottom surface 114 of the substrate 102 may include one or more bumps / balls of the BGA 110. The substrate 102 may be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon carbide germanium, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, etc. may also be used. In other embodiments, the substrate 102 may be a Silicon On Insulator (SOI) substrate. As will be appreciated, the SOI substrate includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon germanium, SOI, Silicon Germanium On Insulator (SGOI), or a combination thereof. In Figure 1 the illustrated embodiment, the substrate 102 is based on an insulating core 116, which is, for example but not limited to, a glass fiber reinforced resin core (such as glass fiber resin like FR4, bismaleimide-triazine (BT) resin, or other printed circuit board (PCB) materials or films.

[0076] In some embodiments, the substrate 102 includes an upper ABF layer 118 and a lower ABF layer 120. It should be understood that other build-up films or laminate materials may also be used for the substrate 102. The substrate 102 may include active and passive devices, which are generally designated as passive device elements 122 in Figure 1 . In some embodiments, the substrate 102 includes an array of passive device elements 122 deployed throughout the substrate 102. It should be understood that various devices such as transistors, capacitors, resistors, combinations thereof, etc. may be used to generate the structural and functional requirements of the semiconductor device 100 design. As discussed in more detail below, Figure 1 the passive device elements 122 shown in Figures 2 to 3 may be formed using any suitable method. According to some embodiments, as

[0077] The substrate 102 may further include a metallization layer, vias, and bonding pads (not shown). It should be understood that such a metallization layer may be formed over the active and passive devices 122 and is designed to connect the various devices to form a functional circuit. The metallization layer may be formed of alternating layers of a dielectric layer (e.g., a low-k dielectric material) and a conductive material (e.g., copper), where the vias interconnect the conductive material layers and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.).

[0078] As Figure 1 shown, the SoC element 104 of the semiconductor device 100 is suitably mounted to the substrate 102. It should be understood that any SoC element 104 (i.e., any integrated circuit design that combines many or all of the high-level functional elements of an electronic device onto a single chip) may be used according to the described embodiments. Additionally, those of ordinary skill in the art will understand that although Figure 1 the SoC element 104 is shown, any SoC, SoIC, Application Specific Integrated Circuit (ASIC), memory, logic, etc. elements may be considered. As Figure 1 shown, the semiconductor device 100 includes an SoC underfill 124 disposed between the bottom of the SoC element 104 and the top surface 112 of the substrate 102. The semiconductor device 100 further includes one or more SoC pillars or contacts 126 dispersed within the SoC underfill 124 located between the bottom of the SoC element 104 and the bottom of the top surface 112 of the substrate 102. As will be understood by those of ordinary skill in the art, the SoC solder element 128 secures the SoC element 104 to the substrate 102, enabling the SoC pillars or contacts 126 to be electrically coupled to the metal contacts of the substrate 102.

[0079] According to some embodiments, the SoC underfill 124 may suitably include (e.g., but not limited to) a liquid epoxy resin, a deformable gel, a silicone rubber, etc. coated between the SoC element 104 and the top surface 112 of the substrate 102, which is then cured to harden. In some embodiments, the SoC underfill 124 may be used to reduce cracks in the SoC pillars or contacts 126 and protect the SoC pillars or contacts 126, etc.

[0080] Figure 1 The semiconductor device 100 further includes a first DRAM element 106 and a second DRAM element 108. In some embodiments, each DRAM element 106 and 108 may include a DRAM substrate 130, DRAM bumps 132, and a DRAM underfill 134, as Figure 1As shown. According to some embodiments, the DRAM underfill 134 may include (by way of example and not limitation) liquid epoxy resin, deformable gel, silicone rubber, etc., which is placed between the DRAM element 106 or 108 and the top surface 112 of the substrate 102. As Figure 1 shown, DRAM bumps 132 are formed on the lower side of the DRAM substrate 130, where the DRAM bumps 132 are configured to contact metal elements disposed above or within the upper ABF layer 118 of the substrate 102.

[0081] As briefly mentioned above, as Figure 1 shown, the bottom surface 114 of the substrate 102 may include a ball grid array (BGA) 110. It should be understood that the solder balls of the ball grid array 110 may be appropriately arranged in various different configurations and numbers according to the design considerations of the semiconductor device 100, and the present disclosure is not limited to Figure 1 the configuration shown in the exemplary embodiments. In addition, as will be appreciated, the type of balls used in the ball grid array 110, its material, etc. may be selected according to the design considerations of the semiconductor device 100.

[0082] Now referring to Figure 2 , a cross-sectional view of a passive device element 122 using an ABF plug element 136 according to an exemplary embodiment is shown. As referred to above with reference to Figure 1 indicated, the exemplary passive device element 122 may be formed within or on the substrate core 116. As Figure 2 shown, the passive device element 122 includes a first passive device conductive element 138 and a second passive device conductive element 140. It should be understood that the first and second passive device conductive elements 138-140 may be made of any suitable conductive material, including (by way of example and not limitation) copper, gold, aluminum, metal, alloy, etc. In some embodiments, the first passive device conductive element 138 (e.g., VDD or voltage, device) may be implemented as the positive electrode of the corresponding passive device element 122, and the second passive device conductive element 140 (e.g., VSS or voltage, series) may be implemented as the ground of the corresponding passive device element 122. In some embodiments, each passive device element 122 may include more than two electrodes, and as will be appreciated, the electrodes are used to generate a voltage change of the passive device element 122.

[0083] As Figure 2As shown, a first passive device conductive element 138 and a second passive device conductive element 140 are formed on a passivation layer 142. The passivation layer 142 may include (e.g., but not limited to) an insulating material that can be implemented as a suitable dielectric, i.e., including (e.g., but not limited to) a silicon dioxide (SiO2) material, a silicon nitride (SiNx) material, etc. According to one embodiment, the passivation layer 142 is formed over at least one upper metal element 146, wherein the first passive device conductive element 138 and the second passive device conductive element 140 are in electrical contact with the at least one upper metal element 146 through vias 144. In some embodiments, the vias 144 include a conductive material that is the same as or different from the conductive material used in the conductive elements 138 - 140, such as copper, gold, aluminum, their alloys, metals, metal alloys, etc. The upper metal element 146 and the passivation layer 142 may be formed on an insulating substrate 143, such as, for example, a ceramic material, a fiberglass material, etc. As Figure 2 shown, the passive device element 122 further includes one or more connection pins 158 extending from the upper metal element 146 through the passivation layer 142 to provide an electrical connection to the upper metal element 146.

[0084] As Figure 2 shown, an insulating material 148 is formed on the first passive device conductive element 138 and the second passive device conductive element 140, respectively. According to some embodiments, the insulating material 148 is a polyimide material. It should be understood that other suitable insulating materials may be used, including (e.g., but not limited to) polyimide materials or other suitable materials having equivalent thermal stability, chemical resistance, and electrical properties. As Figure 2 shown, the insulating material 148 is formed on the sides of the conductive elements 138 - 140, extending upward from the passivation layer 142 and extending over a portion of the tops of the conductive elements 138 - 140.

[0085] As Figure 2 shown, the insulating material 148 includes a lower insulating opening ("T1") 150 located at the bottom of the conductive elements 138 - 140 and adjacent to the passivation layer 142 and an upper insulating opening ("T2") 152 located at the top of the insulating material 148 on the tops of the conductive elements 138 - 140. According to one embodiment, the lower insulating opening T1 150 corresponds to the width of the ABF plug element 136 adjacent to the passivation layer 142, and the upper insulating opening T2 152 corresponds to the width of the ABF plug element 136 at the top of the insulating material 148. In some embodiments, the distance T1 150 can be implemented as the distance between the interface of the first conductive element 138 / insulating material 148 and the interface of the insulating material 148 / second conductive element 140. In other embodiments, the distance T2 152 can be implemented as the distance between the cutting edges of two separate insulating materials 148. AsFigure 2 As shown in the exemplary embodiment of, the insulating material 148 is configured to have a thickness ("d") 156 at the lower insulating opening T1 150 and an angle ("θ") 154 of the insulating material 148 at the lower insulating opening T1 150. In Figure 2 In the embodiment shown, the ABF plug element 136 including the ABF material is located between the insulating materials 148 on each of the conductive elements 138 - 140. It should be understood that Figure 2 The similar wedge - like formation of the ABF plug element 136 shown provides tensile strength for the bonding of the insulating material 148 and the conductive elements 138 - 140, because the ABF material 118 exerts a tensile force on the insulating material 148. According to an exemplary embodiment, when using ABF as the filling material, the main component of the ABF can be a polymer, which expands when the assembly temperature of the substrate core 116 exceeds the Tg (glass transition temperature) of the ABF, thereby generating a tensile stress (i.e., force) to prevent delamination between the insulating material 148 and the conductive elements 138 - 140 and between the insulating material 148 and the passivation layer 142. That is, the structural shape (e.g., wedge - like shape) of the ABF material 118 formed as the ABF plug element 136 provides a force (tensile force) against the insulating material 148, providing protection against its delamination and dendrite formation of the conductive elements 138 - 140. Depending on the formation of the insulating material 148 between the conductive elements 138 - 140, the ABF plug element 136 (formed by the ABF layer 118) can adopt other shapes as discussed below, including conical, rectangular (i.e., straight - edged), polygonal, ridged, etc., and the diagrams provided herein are only illustrative examples thereof.

[0086] Figure 3 A top view of the passive device element 122 of Figure 2 is provided, which includes a first conductive element 138 and a second conductive element 140. It should be understood that although Figure 2 and Figure 3 the shapes shown in are substantially rectangular, other shapes of the conductive elements 138 - 140 can also be considered herein, such as polygonal, circular, cylindrical, etc., and Figures 2 to 3 the depiction of the conductive elements 138 - 140 in is only for illustrative purposes.

[0087] As Figure 3 shown, the insulating material 148 surrounds the conductive elements 138 - 140, advancing a predetermined distance from their edges towards the center. That is, in Figure 3 the embodiment shown, the insulating material 148 not only covers the sides of the conductive elements 138 - 140 but also partially covers the top surfaces of the conductive elements 138 - 140. In addition to the foregoing, Figure 3Illustrations of various dimensions related to the insulating material 148, the conductive elements 138 - 140, and the ABF material 118 are provided. Thus, the length (D1) 160 of the conductive element 138 corresponds to the length of the conductive element 138 that is not covered by the insulating material 148 when viewed from its top. Figure 3 Also shown in Figure 3 is the corner - to - corner length (D1’) 162 of the insulating material 148 in the X - direction along with the width (D2) 164 of the conductive element 140 and the corner - to - corner width (D2’) 166 of the insulating material in the Y - direction. According to some embodiments, the following relationships for the aforementioned lengths, widths, and angles can be used: 0 < D1 / D1’ < 1μm; 0 < D2 / D2’ < 1μm; 0 < d / T2 < T1 / T2 < 1μm; and 0° < θ < 90°. In some embodiments, an array 168 of passive device elements 122 can be formed on or within the substrate core 116.

[0088] Figure 4 An illustrative top - view of such an array 168 of passive device elements 122 according to one embodiment is provided. It should be understood that, as Figure 4 shown, the ABF plug elements 136 are appropriately formed between adjacent conductive elements 138 - 140 in the X and Y directions. Thus, Figure 5A a top - view of a portion of the array 168 along the Y - direction is provided, while Figure 5B a cross - sectional view of a portion of the array from Figure 5A is provided. Thus, as Figure 5A and 5B shown, two passive - device conductive elements 138 include an ABF plug element 136 located therebetween.

[0089] Now referring to Figures 6A to 6M , a series of simplified cross - sectional views of an intermediate manufacturing stage of the conductive elements 138 - 140 and the passive device elements 122 according to some embodiments are shown. Next, various layers or films are deposited and patterned. The patterning of the layers can employ any suitable patterning technique, such as deposition of a photoresist layer and lithographic patterning of a photomask selectively exposing vias to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), etc., followed by development of the exposed photoresist and subsequent etching, deposition, or other process steps laterally delineated by the developed photoresist. In other embodiments, patterning of an electron - sensitive resist layer can be performed by means of electron - beam exposure (electron - beam lithography, i.e., e - beam lithography). Those of ordinary skill in the art will understand that the foregoing are merely illustrative examples.

[0090] Now referring to Figure 6A, shows a top metal layer element 146 or a passive device element 122 according to an exemplary embodiment. Then, a seed layer 170 is deposited and / or formed on the upper metal element 146, as Figure 6B shown. It should be understood that the seed layer 170 can be a thin layer of sputtered or evaporated metal deposited for conductivity. As Figure 6C shown, a photoresist 172 is then deposited on the seed layer 170.

[0091] As Figure 6D shown, the photoresist 172 is then patterned, for example, by exposing it to a suitable light source to activate portions thereof by illumination through a corresponding mask. The photoresist 172 is then lithographed, and the un-lithographed portions (i.e., unexposed portions) of the photoresist 172 are removed and a groove as Figure 6E shown is formed. In Figure 6F , descum is performed in preparation for metal deposition of the conductive elements 138 - 140 to remove any contaminants from the seed layer 170. Metal electroplating is then performed as Figure 6G shown. That is, the metal material of the conductive elements 138 - 140 is formed on the seed layer 170. According to some embodiments, the conductive elements 138 - 140 can include, for example, a suitable conductive metal, including, for example, but not limited to copper, aluminum, gold, iron, metal, metal alloy, and / or alloys thereof, etc. The conductive elements 138 - 140 can be deposited by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroless plating, electroplating, sputtering, ion metal plasma, another deposition process, or any suitable combination thereof.

[0092] Figure 6H shows a manufacturing stage in which the photoresist 172 has been removed, leaving the exposed conductive elements 138 - 140. Then, as Figure 6I shown, a seed layer etch is performed to remove those portions of the seed layer 170 that are not covered by the conductive elements 138 - 140.

[0093] As Figure 6J shown, an insulating material 148 is then formed on the conductive elements 138 - 140. The insulating material 148 is then exposed, i.e., patterned as Figure 6K shown. The insulating material 148 is then lithographed according to the exposure pattern, resulting in the conductive elements 138 - 140 being partially covered as Figure 6L shown. Thereafter, as Figure 6M shown, as will be understood, the insulating material 148 is cured so as to enable further processing as discussed below with respect to Figures 7A - 7E .

[0094] Now refer to Figures 7A - 7E, showing a series of cross - sectional views of an intermediate manufacturing stage of an array 168 of passive elements 122 according to some embodiments. As Figure 7A shown, a portion of the passive device element 122 including the aforementioned passivation layer 142, insulating substrate 143, upper metal element 146, and connection plug 158 is shown as being formed in the substrate core 116. It should be understood that Figures 7A - 7E the images presented are simplified in nature and are only intended to show the manufacturing on the array 168 or substrate core 116 according to some embodiments. Figure 7B An illustration of the array 168 after forming the passive device conductive elements 138 - 140 is provided. Figures 6A to 6I An illustration of a series of manufacturing steps related to forming the passive device conductive elements 138 - 140 is provided. As Figure 7B shown, vias 144 have been formed in the passivation layer 142 to enable electrical contact between the conductive elements 138 - 140 and the upper metal element 146.

[0095] In Figure 7C a layer of insulating material 148 is formed on the array 168 of passive elements 122. A more detailed description of a series of manufacturing steps for applying the insulating material 148 to individual conductive elements 138 - 140 is given above with reference to Figures 6J - 6K . Figure 7D An illustration of the array 168 of passive elements 122 formed in or on the substrate core 116 after patterning of the insulating material 148 and before the application of the ABF layer 118 is provided. As Figure 7D shown, a plurality of grooves 149 are formed between adjacent conductive elements 138 - 140. It should be understood that the shape of the ABF plug element 136 can be defined by the corresponding shape of the grooves 149, i.e., the ABF layer 118 fills the grooves 149 to form the ABF plug element 136. Figures 6L - 6M A more detailed view of this manufacturing stage is provided. Figure 7E A simplified cross - sectional view of the array 168 after applying the ABF layer 118 is provided, where the ABF plug element 136 is formed between each adjacent conductive element 138 - 140.

[0096] Now referring to Figures 8A - 8D , a cross - sectional view of manufacturing a substrate 102 including passive elements 122 using the ABF plug element 136 according to an exemplary embodiment is shown. As Figure 8A shown, the substrate 102 shown therein includes a plurality of passive elements 122 disposed on or in the substrate core 116. One or more metal layers 174 are formed on the substrate core 116, as Figure 8AAs shown, the ABF layer 118 has been formed on the substrate core 116, the metal layer 174, and the passive components 122. According to one embodiment, as described above, the application of the ABF layer 118 includes forming the ABF plug elements 136 between the conductive elements and the passive device elements 122.

[0097] Figure 8B A subsequent stage of the manufacture of the substrate 102 is provided, and then a second metal layer 176 is formed on the ABF layer 118 and a plurality of grooves exposing the first and second conductive elements 138 - 140 are formed. Thereafter, as Figure 8C shown, additional metal material is deposited on the substrate 102 to form vias 178 connecting the second metal layer 176 to the first and second conductive elements 138 - 140. As Figure 8D shown, additional ABF material is then formed along with the metal layer to complete the manufacture of the upper ABF layer 118 of the substrate 102. As Figure 8D shown, a solder mask layer 180 is then formed on the ABF layer 118.

[0098] Now referring to Figures 9A - 9B , a top view and a cross - sectional view of a second embodiment of the ABF plug element 182 are shown, wherein the first conductive element 184 and the second conductive element 186 are wedge - shaped, tapering from a wider top down to a narrower bottom. As Figure 9B shown, it should be understood that the application of the insulating material 148 maintains the angled structure described above with respect to Figure 2 . It should be understood that the dimensions described above with reference to Figure 2 and Figure 3 also apply to the embodiment shown in Figures 9A to 9B .

[0099] Now referring to Figures 10A to 10B , a top view and a cross - sectional view of a third embodiment of the ABF plug element 188 are shown, wherein the first conductive element 190 and the second conductive element 192 are wedge - shaped, tapering from a narrow top down to a wider bottom. As Figure 10B shown, it should be understood that the application of the insulating material 148 maintains the angled structure described above with respect to Figure 2 . It should be understood that the dimensions described above with reference to Figures 2 to 3 also apply to the embodiment shown in Figures 10A to 10B .

[0100] Now referring to Figures 11A to 11B , a top view and a cross - sectional view of a fourth embodiment of the ABF plug element 194 are shown, wherein the first conductive element 196 and the second conductive element 198 are conformal / wedge - shaped, tapering from a wider top down to a narrower bottom. As Figure 11BAs shown, it should be understood that the application of the insulating material 148 maintains the angled structure and conforms to the conductive elements 196 - 198, similar to that described above with respect to Figure 2 It should be understood that the dimensions described above with reference to Figures 2 to 3 also apply to Figures 11A to 11B the embodiment shown.

[0101] Figures 12A to 12B A top view and a cross-sectional view of a fifth embodiment of the ABF plug element 200 are shown respectively. As Figures 12A to 12B shown, the first conductive element 202 and the second conductive element 204 are of a conformal / wedge shape, tapering from a narrower top to a wider bottom. As Figure 12B shown, it should be understood that the application of the insulating material 148 maintains the angled structure and conforms to the conductive elements 202 - 204, similar to that described above with respect to Figure 2 It should be understood that the dimensions described above with reference to Figures 2 to 3 also apply to Figures 12A to 12B the embodiment shown.

[0102] Now referring to Figures 13A to 13B , a top view and a cross-sectional view of a sixth embodiment of the ABF plug element 206 are shown, where the first conductive element 208 and the second conductive element 210 are shaped as described above in Figure 2 and Figure 3 . However, the shape of the insulating material 148 results in a stepped ABF plug element 206. As Figure 13B shown, it should be understood that the application of the insulating material 148 maintains the angled structure described above with respect to Figure 2 . It should be understood that the dimensions described above with respect to Figures 2 to 3 also apply to Figures 13A to 13B the embodiment shown

[0103] Now referring to Figure 14 , a flowchart illustrating a method 1400 for manufacturing an ABF plug element 136 according to some embodiments is shown. As Figure 14 shown, the method 1400 begins at step 1402, followed by forming an insulating substrate 143 on the substrate core 116. In step 1404, one or more upper metal elements 146 are formed on the insulating substrate 143. Then in step 1406, a passivation layer 142 is formed on the upper metal elements 146 and the insulating substrate 143. As Figure 7AAs shown, the substrate core 116 includes an upper metal element 146 located on an insulating substrate 143, and a passivation layer 142 is deposited on the upper metal element 146 and the insulating substrate 143. In step 1408, a photoresist is deposited on the passivation layer 142 and patterned. Thereafter, in step 1410, one or more conductive elements 138-140 are formed on the passivation layer 142 and are electrically contacted with the upper metal element 146 through vias 144. According to some embodiments, as Figures 9A to 13B shown, one or more conductive elements 138-140 can be formed in a variety of shapes. That is, the formation of the conductive elements 138-140 can include, for example but not limited to, wedge shapes, conical shapes, stepped shapes, conformal shapes, etc. It should be understood that such formation can include patterning the above-mentioned photoresist using different masks before depositing the conductive elements 138-140.

[0104] In step 1412, the photoresist is removed. Thereafter, in step 1414, as Figure 7C shown, an insulating material 148 is deposited on the substrate core 116, covering the conductive elements 138-140 and a portion of the passivation layer 142. As described above, the insulating material 148 can include (for example but not limited to) polyimide or other insulating materials. In step 1416, a photoresist is applied to the insulating material 148 and patterned. Patterning the photoresist in step 1416 can combine a variety of different patterns to establish the sides of the ABF plug element 136. For example but not limited to, Figures 9A to 13B shows various different shapes related to the application of the insulating material 148. It should be understood that the insulating material 148 is suitable for forming on the conductive elements 138-140, and the shape of the groove 149 into which the ABF material 118 is deposited can be defined via the patterned insulating material 148, as Figures 9A to 13B shown in various embodiments of the ABF plug element 136.

[0105] Thereafter, in step 1418, the insulating material 148 is etched to remove the portion of the insulating material 148 removed according to the patterned photoresist. Suitable etching forms can include (for example but not limited to) dry etching processes, reactive ion etching (RIE) processes, wet etching processes, some other etching processes, or combinations of the foregoing. In some embodiments, as Figure 7D shown, the insulating material 148 is removed from between adjacent conductive elements 138-140, thereby forming the aforementioned groove 149 therebetween and removing a portion of the insulating material 148 from the top of the conductive elements 138-140. Then the photoresist is removed in step 1420. Thereafter, in step 1422, as Figure 7EAs shown, the ABF material 118 is deposited on the substrate core 116. It should be understood that the deposition of the ABF material 118 on the substrate core 116 fills the grooves between the conductive elements 138-140, thereby forming the ABF plug element 136.

[0106] Due to the interfacial delamination of the conductive element / insulating material (copper / polyimide) and the passivation layer / insulating material (passivation material / polyimide), serious power short-circuit problems occur in the passive components after the biased high-acceleration stress test (bHAST). Due to the low Tg of the ABF, serious strain of the ABF during the substrate assembly process may trigger delamination. In the ABF plug structure, the thermal strain of the ABF can prevent the delamination of copper / polyimide and passivation material / polyimide due to thermal expansion, thereby further reducing the formation of copper dendrites.

[0107] According to a first embodiment, a method of forming a monosodium glutamate build-up film (ABF) plug element in a semiconductor device is provided. At least one upper metal element is formed on a substrate core including an insulating substrate. A passivation layer is formed on the at least one upper metal element and the insulating substrate. At least one conductive element of a passive element is formed on the passivation layer, and the at least one conductive element is in electrical contact with the at least one upper metal element. An insulating material is deposited on the substrate core, wherein the insulating material is deposited on the at least one conductive element and a portion of the passivation layer. The insulating material is patterned to define a groove adjacent to the at least one conductive element. An ABF material is deposited on the insulating material to form an ABF plug element. In one embodiment, forming the at least one conductive element further includes: depositing a photoresist on the passivation layer; patterning the photoresist on the passivation layer to define the shape of the at least one conductive element; and depositing a conductive element material according to the patterned photoresist. In one embodiment, the shape is selected from the group consisting of a wedge having a wider base, a wedge having a wider top, a wedge having a conformal top and a wider base, and a wedge having a conformal top and a wider top. In one embodiment, the ABF plug element includes: a lower insulating opening T1, an upper insulating opening T2, and the thickness d of the insulating material at the lower insulating opening T1; and wherein 0 μm < d / T2 < T1 / T2 < 1 μm. In one embodiment, the insulating material has an angle (θ) at the lower insulating opening T1, and wherein 0° ≤ θ ≤ 90°. In one embodiment, the ABF plug element is wedge-shaped or stepped. In one embodiment, the at least one conductive element includes a length D1 and a length D1' corresponding to the corner-to-corner of the insulating material on the top of the conductive element in the X direction, and wherein 0 μm < D1 / D1' < 1 μm. In one embodiment, the at least one conductive element includes a width D2 and a width D2' corresponding to the corner-to-corner of the insulating material on the top of the conductive element in the Y direction, and wherein 0 μm < D2 / D2' < 1 μm. In one embodiment, the insulating material is a polyimide material.

[0108] According to a second embodiment, a passive device for a semiconductor substrate. The passive device includes first and second upper metal elements located on a substrate core including an insulator substrate, and a passivation layer formed on the first upper metal element, the second upper metal element, and the insulating substrate. The device further includes a first conductive element formed on the passivation layer and in electrical contact with the first upper metal element, and a second conductive element formed on the passivation layer and in electrical contact with the second upper metal element. Additionally, the device includes an insulating material formed on the first conductive element and the second conductive element. The insulating material between the first conductive element and the second conductive element defines a groove. The device further includes an ABF plug element formed in the groove between the first conductive element and the second conductive element. In one embodiment, the cross-sectional shapes of the first conductive element and the second conductive element are selected from the group consisting of a wedge having a wider base, a wedge having a wider top, a wedge having a conformal top and a wider base, and a wedge having a conformal top and a wider top. In one embodiment, the ABF plug element includes: a lower insulating opening T1, an upper insulating opening T2, and the thickness d of the insulating material at the lower insulating opening T1; and where 0 μm < d / T2 < T1 / T2 < 1 μm. In one embodiment, the insulating material has an angle (θ) at the lower insulating opening T1, and where 0° ≤ θ ≤ 90°. In one embodiment, the ABF plug element is wedge-shaped or stepped. In one embodiment, the at least one conductive element includes a length D1 and a length D1' corresponding to the corner-to-corner of the insulating material on the top of the conductive element in the X direction, and where 0 μm < D1 / D1' < 1 μm. In one embodiment, the at least one conductive element includes a width D2 and a width D2' corresponding to the corner-to-corner of the insulating material on the top of the conductive element in the Y direction, and where 0 μm < D2 / D2' < 1 μm. In one embodiment, the insulating material is a polyimide material.

[0109] According to a third embodiment, a semiconductor device is provided that includes a substrate having at least one passive device element, wherein the at least one passive device element includes a first conductive element and a second conductive element. Additionally, the at least one passive device element further includes an ABF plug element located between the first and second conductive elements. The semiconductor device further includes a system-on-chip (SoC), components, a first dynamic random access memory element, and a second dynamic random access memory element. The system-on-chip (SoC), components, first dynamic random access memory element, and second dynamic random access memory element are electrically coupled to the substrate. In one embodiment, the ABF plug element is wedge-shaped or stepped. In one embodiment, the at least one passive device further includes an insulating material formed on the first conductive element and the second conductive element, wherein the insulating material between the first conductive element and the second conductive element defines a groove, and wherein the ABF plug element is formed in the groove between the first conductive element and the second conductive element.

[0110] The foregoing has outlined features of several embodiments so that the detailed description that follows may be better understood and in order that the present contributions to the art may be better appreciated. Those of ordinary skill in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A passive device for a semiconductor substrate, characterized in that Comprising: A first upper metal element and a second upper metal element, located on a substrate core including an insulating substrate; A passivation layer, formed on the first upper metal element, the second upper metal element, and the insulating substrate; A first conductive element, formed on the passivation layer and in electrical contact with the first upper metal element; A second conductive element, formed on the passivation layer and in electrical contact with the second upper metal element; An insulating material, formed on the first conductive element and the second conductive element, wherein the insulating material between the first conductive element and the second conductive element defines a groove; And A Ajinomoto etch stop layer plug element, formed in the groove between the first conductive element and the second conductive element.

2. The passive device according to claim 1, wherein The cross-sectional shapes of the first conductive element and the second conductive element are selected from the group consisting of a wedge having a wider base, a wedge having a wider top, a wedge having a conformal top and a wider base, and a wedge having a conformal top and a wider top.

3. The passive device according to claim 1, characterized in that The Ajinomoto etch stop layer plug element comprises: A lower insulating opening T1, an upper insulating opening T2, and the thickness d of the insulating material at the lower insulating opening T1; and Where 0μm < d / T2 < T1 / T2 < 1μm.

4. The passive device according to claim 3, wherein The insulating material has an angle θ at the lower insulating opening T1, and wherein 0° ≤ θ ≤ 90°.

5. The passive device according to claim 4, characterized in that, The Ajinomoto etch stop layer plug element is wedge-shaped or stepped.

6. The passive device according to claim 4, wherein The first conductive element includes a length D1 and a length D1' corresponding to the corner-to-corner of the insulating material on the top of the first conductive element in the X direction, and wherein 0μm < D1 / D1' < 1μm.

7. The passive device according to claim 6, wherein The second conductive element includes a width D2 and a width D2' corresponding to the corner-to-corner of the insulating material on the top of the second conductive element in the Y direction, and wherein 0μm < D2 / D2' < 1μm.

8. A semiconductor device, characterized in that, Comprising: A substrate, including at least one passive device element, the at least one passive device element including a first conductive element and a second conductive element, and wherein the at least one passive device element further includes an Ajinomoto etch stop layer plug element located between the first conductive element and the second conductive element; A system-on-chip element; A first dynamic random access memory element; And A second dynamic random access memory element, wherein the system-on-chip element, the first dynamic random access memory element, and the second dynamic random access memory element are electrically coupled to the substrate.

9. The semiconductor device according to claim 8, wherein, The Ajinomoto etch stop layer plug element is wedge-shaped or stepped.

10. The semiconductor device according to claim 9, wherein The at least one passive device further includes an insulating material formed on the first conductive element and the second conductive element, wherein the insulating material between the first conductive element and the second conductive element defines a groove, and wherein the Ajinomoto etch stop layer plug element is formed in the groove between the first conductive element and the second conductive element.

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