Carrier plate
By setting a buffer layer on the glass core plate, the damage caused by thermal stress and thermal expansion and contraction of the dielectric layer during the manufacturing process is solved, and the high mechanical properties and crack resistance of the carrier plate are achieved, which extends the service life.
Patent Information
- Application Number
- CN202421556928.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-03
- Publication Date
- 2025-08-01
- Estimated Expiration
- 2034-07-03
AI Technical Summary
In the manufacturing process and in actual applications, glass core plates are easily damaged due to local microcracks, via-hole thermal stress and thermal expansion and contraction of the dielectric layer, which affects the reliability and service life of the chip and circuit board.
A buffer layer is provided on the glass core plate to cover the surface and the inner peripheral wall of the via holes to relieve the thermal stress during processing and the stress caused by thermal expansion and contraction of the dielectric layer, and enhance crack resistance.
It improves the mechanical properties and warpage resistance of the carrier plate, extends the service life, enhances the buffering capacity of the external structure, and improves the reliability of the carrier plate.
Smart Images
Figure CN223182379U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electrical components, in particular to a carrier board. Background Art
[0002] Because of its excellent mechanical properties, electrical properties and warpage resistance, the glass core board is an important part of the chip carrier board and the circuit carrier board. However, there is strong stress at the opening position on the glass core board, and local microcracks are likely to occur during the manufacturing process and actual application. After a long time, the local microcracks will cause the glass core board to crack, thus damaging the chip or circuit board. At the same time, during the manufacturing process of the chip and the circuit board, metals such as copper are usually filled in the vias on the glass core board. The metal filled in the vias is relatively hard, so it is easy to cause damage to the glass core board due to the via thermal stress generated during the processing process and in the thermal shock environment. In addition, during the manufacturing process of the chip and the circuit board, multiple dielectric layers are usually formed on the glass core board. Filling holes are provided on the dielectric layers, and metals are usually filled in the filling holes. When there are overlapping holes in the filling holes of the multiple dielectric layers, the stress on the glass core board generated by the thermal expansion and contraction of the dielectric layers is also likely to cause damage to the glass core board. Summary of the Utility Model
[0003] The purpose of the utility model is to provide a carrier board, which has good mechanical properties, electrical properties and warpage resistance, and also has good crack resistance, better reliability and longer service life.
[0004] To achieve the above purpose, the utility model adopts the following technical solutions:
[0005] The utility model discloses a carrier board, comprising: a glass core board, which has a first surface and a second surface arranged oppositely and vias penetrating therethrough; a buffer layer, which is arranged on the glass core board, and covers the first surface, the second surface and the inner peripheral wall of the vias.
[0006] In some embodiments, the thickness of the buffer layer is 10μm - 20μm.
[0007] In some embodiments, the buffer layer is a PI layer or an epoxy resin layer.
[0008] In some embodiments, the inner side wall of the via is a frosted surface.
[0009] In some embodiments, the carrier board further comprises a seed layer, which is arranged to cover the buffer layer.
[0010] In some specific embodiments, the thickness of the seed layer is less than that of the buffer layer, and the thickness of the seed layer is 5μm - 10μm.
[0011] In some embodiments, there are a plurality of vias, and the buffer layer is formed on the inner wall of each via.
[0012] In some embodiments, the buffer layer includes an adhesive layer and an elastic layer, and two relatively arranged surfaces of the adhesive layer are respectively bonded to the glass core board and the elastic layer.
[0013] In some embodiments, the buffer layer includes a first part and a second part. The first part covers the first surface and the second surface, and the second part covers the inner peripheral wall of the via. The thickness of the first part is less than the thickness of the second part.
[0014] In some embodiments, the cross-section of the via is circular or polygonal.
[0015] Beneficial effects of the carrier board of the present utility model: Since the carrier board of this embodiment includes a glass core board and a buffer layer, with the glass core board as the main structure of the carrier board, it ensures that the carrier board has good mechanical properties, electrical properties, and warpage resistance; since the buffer layer is formed on the inner peripheral wall of the via of the glass core board, the existence of the buffer layer can alleviate the damage to the glass core board caused by the via thermal stress generated during the processing process and in the thermal shock environment; since the buffer layer is provided on the first surface of the glass core board, the existence of the buffer layer can alleviate the damage to the glass core board caused by the stress generated by the thermal expansion and contraction of the dielectric layer to the stress of the glass core board. Since there is also a buffer layer on the second surface of the glass core board, and the second surface is the bottom surface of the glass core board, setting the buffer layer on the bottom surface can better buffer the acting force of the external structure on the glass core board; thus, by setting the buffer layer, the crack resistance of the carrier board can be better improved, which is beneficial to extending the service life of the carrier board.
[0016] Additional aspects and advantages of the present utility model will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present utility model. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is a cross-sectional schematic view of the carrier board according to an embodiment of the present utility model;
[0018] Figure 2 is a cross-sectional schematic view of the combination of the carrier board according to an embodiment of the present utility model and metal;
[0019] Figure 3 is a cross-sectional schematic view of the carrier board provided with a dielectric layer according to an embodiment of the present utility model;
[0020] Figure 4 is Figure 1 a schematic diagram of a manufacturing method of the carrier board shown;
[0021] Figure 5Yes Figure 1 Schematic diagram of another manufacturing method of the carrier board shown;
[0022] Figure 6 It is a cross-sectional schematic diagram of another carrier board according to an embodiment of the present invention.
[0023] Reference numerals:
[0024] 100, glass core board; 110, first surface; 120, second surface; 130, via hole;
[0025] 200, buffer layer; 300, seed layer; 400, dielectric layer. Detailed implementation manners
[0026] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only the parts related to the present invention are shown in the drawings, rather than all the structures.
[0027] In the description of the present invention, unless otherwise clearly defined and limited, the terms "connected", "connected to", and "fixed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.
[0028] In the present invention, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features between them. Moreover, the first feature being "above", "above", and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is at a higher horizontal height than the second feature. The first feature being "below", "below", and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that the first feature is at a lower horizontal height than the second feature.
[0029] In the description of this embodiment, the orientation or positional relationships such as "upper", "lower", "right", etc. are based on the orientation or positional relationships shown in the drawings. They are only for the convenience of description and simplifying operations, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present utility model. In addition, the terms "first" and "second" are only used for distinction in description and have no special meaning.
[0030] The present utility model discloses a carrier board. Referring to Figure 1 and Figure 6 as shown, the carrier board of this embodiment includes a glass core board 100 and a buffer layer 200. The glass core board 100 has a first surface 110 and a second surface 120 arranged oppositely and a via hole 130 penetrating therethrough. The buffer layer 200 is provided on the glass core board 100, and the buffer layer 200 covers the first surface 110, the second surface 120, and the inner peripheral wall of the via hole 130. It can be understood that since the carrier board of this embodiment includes a glass core board 100 and a buffer layer 200, with the glass core board 100 as the main structure of the carrier board, it ensures that the carrier board has good mechanical properties, electrical properties, and warpage resistance. Since the inner peripheral wall of the via hole 130 of the glass core board 100 is formed with a buffer layer 200, during the actual process, the presence of the buffer layer 200 can relieve Figure 2 the damage caused to the glass core board 100 by the thermal stress of the via hole 130 generated at location A during the processing and in the thermal shock environment shown in Figure 3 and improve the crack resistance of the carrier board. At the same time, since the buffer layer 200 is provided on the first surface 110 of the glass core board 100, during the actual process, the presence of the buffer layer 200 can relieve Figure 3 the damage to the glass core board 100 caused by the stress on the glass core board 100 generated by the thermal expansion and contraction of the dielectric layer 400 at location B shown in Figure 3 and improve the crack resistance of the carrier board. In addition, since there is also a buffer layer 200 on the second surface 120 of the glass core board 100, and the second surface 120 is the bottom surface of the glass core board 100, setting the buffer layer 200 on the bottom surface can better buffer the acting force of the external structure on the glass core board 100, thereby improving the crack resistance of the carrier board.
[0031] The carrier board of this embodiment can be manufactured in two ways during the actual processing. The first is as Figure 4 shown, forming the buffer layer 200 on the first surface 110, the second surface 120 of the glass core board 100 provided with the via hole 130, and the inner peripheral wall of the via hole 130 through a deposition process; the second is as Figure 5As shown, a buffer layer 200 is formed on the first surface 110 and the second surface 120 of the glass core board 100 provided with vias 130 through a coating process, and a filling portion is formed in the vias 130 to fill the entire via 130. Then, a via 130 is opened in the filling portion by means of laser drilling for filling metal in subsequent processes. In the actual production and manufacturing process, the carrier board of the present utility model can be processed by any one of the above two methods. Among them, the deposition process, the coating process, and the drilling process are all existing technologies, and specific descriptions of the deposition process, the coating process, and the drilling process are not required here. In addition, the present utility model provides a carrier board with a new structure, rather than an improvement in the manufacturing process of the carrier board. The above manufacturing process is only an exemplary illustration.
[0032] In some embodiments, the thickness of the buffer layer 200 is 10μm - 20μm. It can be understood that during the actual process, if the thickness of the buffer layer 200 is too large, the thickness of the entire carrier board will be relatively thick, which is not conducive to realizing the thin and light design of the chip or the circuit board. If the thickness of the buffer layer 200 is too small, the buffering capacity will be insufficient, thereby reducing the protective effect on the glass core board 100. In this embodiment, the thickness of the buffer layer 200 is set at 10μm - 20μm, ensuring a moderate thickness of the buffer layer 200 on the premise of ensuring the buffering effect, which is convenient for realizing the thin and light design of the chip or the circuit board.
[0033] Optionally, the thickness of the buffer layer 200 can be 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm. Of course, the thickness of the buffer layer 200 can also be any other number within the range of 10μm - 20μm, not limited to the above examples. In other embodiments of the present utility model, the thickness of the buffer layer 200 can also be selected as other thicknesses according to actual needs, not limited to the range of 10μm - 20μm in this embodiment.
[0034] In some embodiments, the buffer layer 200 is a PI layer (Polyimide) or an epoxy resin layer. It can be understood that both the PI layer and the epoxy resin layer have good buffering performance, good insulation, and wear resistance. Using the PI layer and the epoxy resin layer as the buffer layer 200 can better extend the service life of the entire carrier board. Of course, in other embodiments of the present utility model, the buffer layer 200 can also be selected as other materials according to actual needs, not limited to polyimide and epoxy resin.
[0035] In some embodiments, the inner wall of the via 130 is a frosted surface. It can be understood that the frosted inner wall of the via 130 can increase the roughness of the inner wall of the via 130, ensure a more reliable bonding between the via 130 and the buffer layer 200, and prevent the buffer layer 200 from peeling off the inner wall of the via 130.
[0036] In some embodiments, the first surface 110 and the second surface 120 are frosted surfaces. It can be understood that the frosted first surface 110 and second surface 120 can increase the roughness of the first surface 110 and the second surface 120, ensure a more reliable bonding between the first surface 110 and the second surface 120 and the buffer layer 200, and prevent the buffer layer 200 from peeling off the inner walls of the first surface 110 and the second surface 120.
[0037] It should be noted that in the embodiments of the present invention, the roughness of the inner wall of the via 130, the first surface 110, and the second surface 120 can be selected according to actual needs, and the roughness parameters of the inner wall of the via 130, the first surface 110, and the second surface 120 are not specifically limited herein.
[0038] In some embodiments, referring to Figure 6 As shown, the carrier plate further includes a seed layer 300, and the seed layer 300 covers the buffer layer 200. It can be understood that the added seed layer 300 can facilitate subsequent processes and is beneficial to improving the bonding strength between the carrier plate and the metal, thereby extending the service life of electrical components such as chips and circuit boards that use the carrier plate.
[0039] In some specific embodiments, the thickness of the seed layer 300 is less than the thickness of the buffer layer 200, and the thickness of the seed layer 300 is 5 μm - 10 μm. During the actual process, too large a thickness of the seed layer 300 will result in a relatively thick overall thickness of the carrier plate, which is not conducive to the thin and light design of the chip or circuit board. Too small a thickness of the buffer layer 200 will result in an insignificant effect of improving the bonding strength between the carrier plate and the metal. In this embodiment, the thickness of the seed layer 300 is set within 5 μm - 10 μm to ensure a moderate thickness of the seed layer 300 on the premise of ensuring the bonding strength between the carrier plate and the metal, facilitating the thin and light design of the chip or circuit board.
[0040] Optionally, the thickness of the seed layer 300 can be 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm. Of course, the thickness of the seed layer 300 can also be any other number within the range of 5μm - 10μm, not limited to the above examples. In other embodiments of the present utility model, the thickness of the seed layer 300 can also be selected according to actual needs, not limited to the range of 5μm - 10μm in this embodiment.
[0041] In some embodiments, there are multiple vias 130, and a buffer layer 200 is formed on the inner wall of each via 130. The multiple vias 130 can better meet the needs of chips and circuit boards of different models and specifications. In the embodiments of the present utility model, the specific number of vias 130 can be adjusted according to actual needs, and the arrangement pattern of the multiple vias 130 can also be designed according to actual needs.
[0042] In some embodiments, the buffer layer 200 includes an adhesive layer and an elastic layer. The two relatively arranged surfaces of the adhesive layer are respectively bonded to the glass core board 100 and the elastic layer. It can be understood that the adhesive layer can ensure the connection strength between the glass core board 100 and the buffer layer 200, avoiding the phenomenon that the buffer layer 200 falls off from the glass core board 100, and the elastic layer can ensure the buffering effect of the buffer layer 200, thereby better protecting the glass core board 100.
[0043] In some embodiments, the buffer layer 200 includes a first part and a second part. The first part covers the first surface 110 and the second surface 120, and the second part covers the inner peripheral wall of the via 130. The thickness of the first part is less than the thickness of the second part. It can be understood that compared with the first surface 110 and the second surface 120, the inner peripheral wall of the via 130 is more likely to be damaged. The thickness of the first part being less than the thickness of the second part can enhance the protection of the inner peripheral wall of the via 130, thereby being beneficial to extending the service life of the glass core board 100.
[0044] In some embodiments, the cross-section of the via 130 is circular or polygonal. The specific shape of the via 130 can be selected as circular, triangular, quadrilateral, etc. according to actual needs, and can be specifically adjusted according to actual needs.
[0045] In the description of this specification, the descriptions with reference to terms such as "some embodiments", "other embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.
[0046] Obviously, the above embodiments of the present utility model are merely examples for clearly illustrating the present utility model, rather than limitations on the implementation manners of the present utility model. For those of ordinary skill in the art, various obvious changes, re-adjustments and substitutions can be made without departing from the protection scope of the present utility model. It is not necessary and impossible to enumerate all implementation manners here. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present utility model shall be included within the protection scope of the claims of the present utility model.
Claims
1. A carrier board, characterized in that, Comprising: A glass core board (100), the glass core board (100) having a first surface (110) and a second surface (120) disposed opposite to each other and a via hole (130) penetrating therethrough; A buffer layer (200), the buffer layer (200) being provided on the glass core board (100), and the buffer layer (200) covering the first surface (110), the second surface (120) and the inner peripheral wall of the via hole (130); wherein, The buffer layer (200) includes a first part and a second part, the first part covering the first surface (110) and the second surface (120), and the second part covering the inner peripheral wall of the via hole (130), the thickness of the first part being less than the thickness of the second part.
2. The carrier board according to claim 1, wherein, The thickness of the buffer layer (200) is 10 μm - 20 μm.
3. The carrier board according to claim 1, wherein The buffer layer (200) is a PI layer or an epoxy resin layer.
4. The carrier board according to claim 1, wherein The inner side wall of the via hole (130) is a frosted surface.
5. The carrier board according to claim 1, characterized in that, The carrier board further includes a seed layer (300), the seed layer (300) being disposed to cover the buffer layer (200).
6. The carrier board according to claim 5, wherein The thickness of the seed layer (300) is less than the thickness of the buffer layer (200), and the thickness of the seed layer (300) is 5 μm - 10 μm.
7. The carrier plate according to claim 1, characterized in that, The via holes (130) are multiple, and the buffer layer (200) is formed on the inner wall of each of the via holes (130).
8. The carrier board according to claim 1, wherein The buffer layer (200) includes an adhesive layer and an elastic layer, and two opposite surfaces of the adhesive layer are respectively bonded to the glass core board (100) and the elastic layer.
9. The carrier board according to claim 1, wherein The cross-section of the via hole (130) is circular or polygonal.