Timer circuit structure

Abstract

The utility model relates to the technical field of electronic circuits, and particularly discloses a timer circuit structure, which comprises a timing chip, a power supply circuit and a driving circuit, the power supply circuit comprises a live wire end and a null line end, the live wire end comprises a series resistor, the other end of the series resistor serves as a voltage output end VCC, the null line end comprises at least two series resistors, one end of the at least two series resistors is divided into two paths, one path is connected with the timing chip through the resistor to serve as a zero-crossing detection point, and the other path is connected with the timing chip through the resistor to serve as a zero-crossing detection point. The anode of the diode is used as a grounding end, and the grounding end is connected with a voltage output end VCC through a voltage stabilizing diode; a power pin VDD of the timing chip is connected with a voltage output end VCC; the driving circuit is connected with an output pin of the timing chip, and switching of on-off states is achieved according to received pulse signals of the timing chip. By improving the power supply circuit and the driving circuit, the situation that the driving circuit works in the quadrant IV is avoided, and the timer has the effect of keeping the timer to work stably.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, in particular to a timer circuit structure. Background Art

[0002] The power supply circuits of existing timers are mostly complex, and such complex power supply circuits occupy a large space on the circuit board, which cannot meet the design requirements of small-volume timers.

[0003] Chinese patent CN 220323742 U discloses a timer whose power supply circuit utilizes a step-down circuit composed of two chip resistors to reduce the power supply from 220V to the required low voltage. A half-wave rectifier circuit is then used to output the voltage VCC. This power supply circuit can be implemented using relatively small or fewer components, meeting the design requirements of a compact timer. The timer is equipped with a drive circuit that includes a thyristor (SCR). The power supply voltage output by the timer's power supply circuit is a positive voltage output. When the timer drives the SCR, the SCR only operates in quadrants one and four. In quadrant four, the SCR cannot conduct normally. Therefore, the ability of the SCR to trigger and maintain conduction is limited, affecting the normal operation and performance of the entire timer circuit. Furthermore, the timer's drive circuit can only use standard bidirectional thyristors or SCRs, and cannot use non-standard bidirectional thyristors or ACS and ACST series AC power solid-state switches. This also restricts the manufacture and use of the timer. Utility Model Content

[0004] The technical problem to be solved by the utility model is: by improving the power supply circuit and driving circuit of the timer, the occurrence of the situation that the driving circuit connected to the timer works in quadrant four is avoided, and the timer is kept working stably. Moreover, its driving circuit can use standard bidirectional thyristors and thyristor rectifiers, non-standard bidirectional thyristors and thyristor rectifiers, ACS series and ACST series AC power solid-state switches.

[0005] In order to solve the above technical problems, a technical solution adopted by the present invention is: a timer circuit structure, including: a timing chip, a power supply circuit and a driving circuit;

[0006] The power supply circuit includes a live terminal electrically connected to the live wire and a neutral terminal electrically connected to the neutral wire. The live terminal includes a series resistor R4, the other end of which serves as a voltage output terminal VCC. The neutral terminal includes at least two series resistors R2 and R3, one end of which is divided into two paths. One path is connected to the timing chip through resistor R1 as a zero-crossing detection point, and the other path is connected to the cathode of diode D1. The anode of diode D1 serves as a ground terminal. The ground terminal is also connected to the voltage output terminal VCC through a voltage regulator diode DW1.

[0007] The power pin VCC of the timing chip is connected to the voltage output terminal VCC;

[0008] The driving circuit is connected to the output pin of the timing chip and switches the on-off state according to the pulse signal received from the timing chip;

[0009] Among them, the driving circuit includes a thyristor, the control electrode series resistor R5 of the thyristor is connected to the output pin of the timing chip, one end of the thyristor is connected to the voltage output terminal VCC, and the other end is connected to the interface. The thyristor realizes the switching of the thyristor on and off state according to the received pulse signal.

[0010] As a preferred technical solution, the voltage output terminal VCC is connected to the ground terminal through a capacitor C1; a capacitor C2 is connected in parallel between the power pin VCC and the ground pin of the timing chip.

[0011] As a preferred technical solution, the timer circuit structure further includes: an operating circuit, which is connected to the timing chip and is used to turn on or off the timing function of the timing chip. When in the on state, the timing chip outputs a pulse signal.

[0012] As a preferred technical solution, the timer circuit structure further includes: an indicator circuit, which is a three-way LED indicator circuit that controls the three indicator lights in a time-sharing manner through three pins of the timing chip.

[0013] As a preferred technical solution, the resistors R1, R2, R3, R4 and R5 are all chip resistors, the diode D1 is a chip diode, the voltage regulator diode DW1 is a chip voltage regulator diode, and the thyristor is a bidirectional thyristor.

[0014] As a preferred technical solution, capacitors C1 and C2 are both chip capacitors.

[0015] The utility model is capable of preventing a driving circuit connected to a timer from operating in quadrant four by arranging a power circuit to generate a negative voltage for power supply and connecting one end of the thyristor to the voltage output end VCC, thereby having the effect of maintaining stable operation of the timer; and the driving circuit can use standard bidirectional thyristors and thyristor rectifiers, non-standard bidirectional thyristors and thyristor rectifiers, ACS series and ACST series AC power solid-state switches, so that the utility model has a wide range of manufacture and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a circuit diagram of the utility model.

[0017] Figure 2 Schematic diagram of the four quadrant triggering of thyristor. DETAILED DESCRIPTION

[0018] For example, certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different nouns to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criteria for distinction. For example, "including" and "comprising" mentioned throughout the specification and claims are open-ended terms, so they should be interpreted as "including but not limited to" and "including but not limited to". "Approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and basically achieve the technical effect. The subsequent description of the specification is a preferred embodiment of the present application, but the description is for the purpose of illustrating the general principles of the present application, and is not used to limit the scope of the present application. The scope of protection of the present application shall be determined by the definition of the attached claims.

[0019] The detailed description and technical contents of the present invention are described below with reference to the accompanying drawings. However, the drawings are provided for reference and illustration only and are not intended to limit the present invention.

[0020] like Figure 1 As shown, the utility model provides a timer circuit structure including: a timing chip U1, a power supply circuit and a drive circuit.

[0021] The power supply circuit includes a live wire end electrically connected to the live wire and a neutral wire end electrically connected to the neutral wire. The live wire end includes a series resistor R4 that acts as a fuse. The other end of the series-connected fuse resistor R4 serves as a voltage output end VCC. The neutral wire end includes at least two series-connected resistors R2 and R3. One end of the two series-connected resistors is divided into two paths. One path is connected to the timing chip U1 through the resistor R1 as a zero-crossing detection point, and the other path is connected to the cathode of the diode D1. The anode of the diode D1 serves as the ground end of the entire circuit. The ground end is also connected to the voltage output end VCC through the voltage regulator diode DW1.

[0022] The power pin VCC of the timing chip U1 is connected to the voltage output terminal VCC.

[0023] The driving circuit is connected to the output pin of the timing chip U1 and switches between on and off states according to the pulse signal received from the timing chip U1.

[0024] In this timer circuit structure, the driving circuit includes a thyristor Q1. The control electrode series resistor R5 of the thyristor Q1 is connected to the output pin of the timing chip U1. One end of the thyristor Q1 is connected to the voltage output terminal VCC, and the other end is connected to the interface. The thyristor Q1 switches the on-off state of the thyristor according to the received pulse signal.

[0025] In the timer circuit structure, the voltage output terminal VCC is connected to the ground terminal through the capacitor C1.

[0026] In the timer circuit structure, a capacitor C2 is connected in parallel between the power pin VCC and the ground pin of the timing chip U1.

[0027] The timer circuit structure further includes an operating circuit connected to the timing chip U1 for turning on or off the timing function of the timing chip. When in the on state, the timing chip U1 outputs a pulse signal.

[0028] The timer circuit structure also includes an indicator circuit, which is a three-way LED indicator circuit that controls the three-way LED indicator lights in a time-sharing manner through three pins of the timing chip.

[0029] Figure 1 In the power supply circuit, resistors R1, R2, R3 and R4 are all chip resistors. Preferably, the resistance of R1 is 1 megohm, the resistance of R2 is 43 kiloohms, the resistance of R3 is 43 kiloohms, and the resistance of R4 is 0.5 ohms; the diode D1 is a chip diode, and the preferred model is 1N4007; the voltage regulator diode DW1 is a chip voltage regulator diode, and the preferred model is a 5.1V voltage regulator tube; the capacitor C1 is a chip capacitor, and the preferred capacitance is 10 microfarads.

[0030] Figure 1In the driving circuit, the thyristor Q1 is a bidirectional thyristor, preferably a 97A6 or 97A8; the series resistor R5 is a chip resistor, preferably a resistance of 1 kilo-ohm.

[0031] Figure 1 The timing chip U1 is a timer chip, preferably XC8P9520 or HC18P015A0 or HC18P122A1 or NY8A051H; the parallel capacitor C2 is a chip capacitor, preferably 1 microfarad.

[0032] Figure 1 In the operation circuit, the button SW1 is used to turn on or off the timing function of the timing chip. The button SW1 is a patch button, and the preferred model is a 3*4 four-legged turtle.

[0033] Figure 1 In the indication circuit, the three LED indicator lights are light emitting diodes D2, D3, and D4, and the light emitting diodes D2, D3, and D4 are patch indicator lights.

[0034] Figure 1 In the figure, P1 is the terminal block, which is the AC input terminal block; P2 is the terminal block, which is the heating element terminal block.

[0035] In other embodiments, the drive circuit of the present invention can use standard bidirectional thyristors and thyristor rectifiers, non-standard bidirectional thyristors and thyristor rectifiers, ACS series and ACST series AC power solid-state switches.

[0036] The working principle of the utility model circuit:

[0037] Power semiconductor components can generally only be controlled via a power supply. When their drive reference is connected to the mains (line or neutral), a non-isolated power supply is often required. This is the case when triggering AC switches such as triacs, AC / DC converters (ACSs), ACSs, or silicon-controlled rectifiers (SCRs). These components are controlled by a gate current. This gate current can only be applied to the gate pin and circulates between the gate and the AC switch's reference terminal: the cathode (K) for SCRs, A1 for triacs, or COM for AC / DC converters and ACSs. Because the AC switch control circuitry and its power supply can only be connected to the component reference terminal (the back-to-line voltage), a non-isolated power supply is required.

[0038] For triacs, ACSs, and ACSTs, four trigger quadrants can be defined based on the polarity of the gate current and voltage across the device before turn-on. Gate current is considered positive when it originates from the gate. Voltage is considered positive when it is relative to the drive reference point.

[0039] like Figure 2As shown, taking thyristor as an example, the four trigger quadrants are:

[0040] 1. Quadrant 1: positive gate current and positive voltage;

[0041] 2. Quadrant 2: negative gate current and positive voltage;

[0042] 3. Quadrant 3: negative gate current and negative voltage;

[0043] 4. Quadrant 4: Positive gate current and negative voltage.

[0044] Each quadrant of a thyristor (SCR) triggers with different voltage and current conditions. When triggered in the fourth quadrant, due to the SCR's process structure, the trigger current flows farther between the chips within the device, resulting in the highest drive current of the four quadrants. This current requires a larger holding current, lasts the longest, and has the weakest di / dt (rate of change of current) capability. If the MCU's IO port is used to directly drive the SCR to operate in the fourth quadrant, the MCU's IO drive capability and drive time will affect the thyristor's ability to conduct properly.

[0045] In the prior art, Chinese patent CN 220323742 U discloses a timer, such as Figure 1 As shown, the drive reference point is connected to the non-isolated power supply by connecting the power supply circuit ground (GND) to the drive reference point, effectively grounding one end of the thyristor Q1. Because the power supply voltage (VCC) is actually higher than the mains terminal potential (line or neutral), and the mains terminal potential is connected to the drive reference point (GND), this topology is called a positive voltage topology. If the power supply is 5V, VCC is 5V higher than the mains reference point. This topology can only be used directly with standard triacs and thyristor rectifiers, not with non-standard triacs, ACS, and ACSTs. Using this topology to generate a positive voltage supply will cause the thyristor to operate only in quadrants 1 and 4, causing the thyristor to not conduct properly in quadrant 4.

[0046] In the present utility model, Figure 1 As shown, the drive reference point is connected to the non-isolated power supply by connecting the power circuit supply voltage (VCC) to the drive reference point, effectively connecting one terminal of thyristor Q1 to the voltage output terminal VCC. The supply voltage reference point (GND) is actually lower than VCC, which is connected to the mains reference point. If the power supply is 5V, GND is 5V lower than the line reference point, or –5V relative to the line. This topology can be used with all triacs, ACSs, and ACSTs. This topology generates a negative voltage to supply power, allowing the thyristor to operate only in quadrants 2 and 3, completely avoiding all issues associated with quadrant 4.

[0047] The above embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Any equivalent substitution or modification made by those skilled in the art based on the present invention shall fall within the protection scope of the present invention.

Claims

1. A timer circuit structure, characterized in that: It includes: Timing chip, power supply circuit and drive circuit; The power supply circuit includes a live wire terminal electrically connected to the live wire and a neutral wire terminal electrically connected to the neutral wire, the live wire terminal includes a series resistor R4, the other end of the series resistor R4 serves as a voltage output terminal VCC, and the neutral wire terminal includes at least two series resistors R2 and R3, one end of the at least two series resistors R2 and R3 is divided into two paths, one path is connected to the timing chip through the resistor R1 as a zero-crossing detection point, and the other path is connected to the cathode of the diode D1, the anode of the diode D1 serves as a ground terminal, and the ground terminal is further connected to the voltage output terminal VCC through the voltage regulator diode DW1; The power pin VCC of the timing chip is connected to the voltage output terminal VCC; The driving circuit is connected to the output pin of the timing chip and switches the on-off state according to the pulse signal received from the timing chip; The driving circuit includes a thyristor, the control electrode series resistor R5 of the thyristor is connected to the output pin of the timing chip, one end of the thyristor is connected to the voltage output terminal VCC, and the other end is connected to the interface. The thyristor realizes the switching of the thyristor on and off state according to the received pulse signal.

2. A timer circuit structure as claimed in claim 1, characterized in that: The voltage output terminal VCC is connected to the ground terminal through a capacitor C1; a capacitor C2 is connected in parallel between the power pin VCC and the ground pin of the timing chip.

3. A timer circuit structure as claimed in claim 1 or 2, characterized in that: It also includes: an operating circuit, which is connected to the timing chip and is used to turn on or off the timing function of the timing chip. When in the on state, the timing chip outputs a pulse signal.

4. A timer circuit structure as claimed in claim 3, characterized in that: It also includes: an indication circuit, which is a three-way LED indication circuit, and controls the three-way indicator lights in a time-sharing manner through three pins of a timing chip.

5. A timer circuit structure as claimed in claim 1, characterized in that: The resistors R1, R2, R3, R4 and R5 are all chip resistors, the diode D1 is a chip diode, the voltage regulator diode DW1 is a chip voltage regulator diode, and the thyristor is a bidirectional thyristor.

6. A timer circuit structure as claimed in claim 2, characterized in that: The capacitors C1 and C2 are both chip capacitors.

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