Driving circuit and voltage converter

Abstract

The utility model relates to a driving circuit and a voltage converter. The driving circuit generates a first control signal and a second control signal and outputs the first control signal and the second control signal to respective control electrodes of the first power semiconductor element and the second power semiconductor element which are connected in parallel. The range of the safe operation area of the first power semiconductor element is larger than the range of the safe operation area of the second power semiconductor element. The driving circuit comprises a time delay circuit, a control logic circuit and a buffer. The time delay circuit compares a voltage level of the second control signal with a first reference voltage or compares a drain-source voltage of the first power semiconductor element with a second reference voltage, and generates a first voltage according to a comparison result. The first and second reference voltages are associated with temperatures of the first and second power semiconductor elements. The control logic circuit generates a logic signal according to the first voltage. The buffer generates a first or second control signal according to a logic signal. According to the utility model, the range of a relatively large safe working area can be realized.

Description

Technical Field

[0001] The utility model relates to a voltage converter, and in particular to a driving circuit and a voltage converter. Background Art

[0002] To achieve a higher voltage converter, a conventional method is to connect the two power semiconductor devices in the upper and lower bridge sections using a cascode connection. However, the cascode connection increases the on-resistance, resulting in poor switching efficiency. Utility Model Content

[0003] The present invention provides a driver circuit for generating a first control signal and a second control signal, and providing the first and second control signals to control electrodes of a first power semiconductor element and a second power semiconductor element connected in parallel in a voltage converter. The safe operating area of the first power semiconductor element is greater than the safe operating area of the second power semiconductor element. The driver circuit includes a first time delay circuit, a control logic circuit, and a first buffer. The first time delay circuit performs a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or compares the drain-source voltage of the first power semiconductor element with a second reference voltage and generate a corresponding second comparison result, and generates a first voltage based on the first or second comparison result. The first and second reference voltages are associated with the temperatures of the first and second power semiconductor elements. The control logic circuit is coupled to the first time delay circuit and generates a first logic signal based on the first voltage. The first buffer is coupled to the control logic circuit and generates one of a first and a second control signal based on the first logic signal.

[0004] The present invention further provides a voltage converter comprising a first power semiconductor element, a second power semiconductor element, a first time delay circuit, a control logic circuit, and a first buffer. The first power semiconductor element has a control electrode that receives a first control signal. The second power semiconductor element is connected in parallel to the first power semiconductor element and has a control electrode that receives a second control signal. The safe operating area of the first power semiconductor element is greater than the safe operating area of the second power semiconductor element. The first time delay circuit performs a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or compares a first drain-source voltage of the first power semiconductor element with a second reference voltage and generates a corresponding second comparison result, and generates a first voltage based on the first or second comparison result. The first and second reference voltages are associated with first temperatures of the first and second power semiconductor elements. The control logic circuit is coupled to the first time delay circuit and is configured to generate a first logic signal based on the first voltage and a pulse width modulation signal. The first buffer is coupled to the control logic circuit and is configured to generate one of a first and a second control signal based on the first logic signal.

[0005] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following detailed description, taken in conjunction with the accompanying drawings, will provide a better understanding of the present invention. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a circuit diagram of a voltage converter according to an embodiment of the present utility model;

[0008] Figure 2 is a signal timing diagram of a voltage converter according to an embodiment of the present utility model;

[0009] Figure 3 is an exemplary circuit diagram of a control logic circuit according to an embodiment of the present utility model;

[0010] Figure 4A is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention;

[0011] Figure 4B is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present utility model;

[0012] Figure 5is a signal timing diagram of the upper bridge portion of the voltage converter in the conduction phase according to an embodiment of the present invention;

[0013] Figure 6A is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention;

[0014] Figure 6B is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present utility model;

[0015] Figure 7 is a signal timing diagram of the upper bridge portion of the voltage converter in the shutdown phase according to an embodiment of the present invention;

[0016] Figure 8 is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present utility model;

[0017] Figure 9 is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present utility model;

[0018] Figure 10A is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention;

[0019] Figure 10B is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present utility model;

[0020] Figure 11A is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention;

[0021] Figure 11B is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present utility model;

[0022] Figure 12 is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present utility model;

[0023] Figure 13 is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present utility model;

[0024] Figure 14 is a circuit diagram of a voltage converter according to an embodiment of the present utility model. DETAILED DESCRIPTION

[0025] The following detailed discussion includes embodiments of the present invention. However, it should be understood that the embodiments provide numerous applicable concepts that can be implemented in a wide variety of specific contexts. The embodiments discussed and disclosed are for illustrative purposes only and are not intended to limit the scope of the present invention. The terms "first," "second," etc., as used herein, do not specifically denote order or precedence; they are used solely to distinguish between elements or operations described using the same technical terminology.

[0026] Figure 1 FIG. 1 is a circuit diagram of a voltage converter 1 according to an embodiment of the present invention. Figure 1 In this embodiment, voltage converter 1 is a buck converter. Voltage converter 1 includes temperature sensors 122 and 162, time delay circuits 120, 140, 160, and 180, a control logic circuit 220, a buffer BF, power semiconductor devices NM1-NM4, an inductor L, and an output capacitor Cout. Power semiconductor devices NM1 and NM2 form the upper bridge portion of voltage converter 1, while power semiconductor devices NM3 and NM4 form the lower bridge portion of voltage converter 1.

[0027] The temperature sensor 122 is positioned adjacent to the power semiconductor elements NM1 and NM2 to sense the temperature of the power semiconductor elements NM1 and NM2 (i.e., the temperature of the upper bridge portion) and output a sense voltage Vtemp1 corresponding to the temperature (i.e., the sense voltage Vtemp1 indicates the temperature of the power semiconductor elements NM1 and NM2). In this embodiment, as the temperature of the power semiconductor elements NM1 and NM2 increases, the sense voltage Vtemp1 increases accordingly. For example, different voltage values of the sense voltage Vtemp1 correspond to different temperature values or different temperature ranges of the power semiconductor elements NM1 and NM2. The temperature sensor 162 is positioned adjacent to the power semiconductor elements NM3 and NM4 to sense the temperature of the power semiconductor elements NM3 and NM4 (i.e., the temperature of the lower bridge portion) and output a sense voltage Vtemp2 corresponding to the temperature (i.e., the sense voltage Vtemp2 indicates the temperature of the power semiconductor elements NM3 and NM4). In this embodiment, as the temperature of the power semiconductor elements NM3 and NM4 increases, the sense voltage Vtemp2 increases accordingly. For example, different voltage values of the sensed voltage Vtemp2 correspond to different temperature values or different temperature ranges of the power semiconductor devices NM3 and NM4 .

[0028] Time delay circuits 140 and 120 are coupled to temperature sensor 122 to receive a sense voltage Vtemp1 from temperature sensor 122 and provide or generate voltages VG1 and VG2, respectively, based on sense voltage Vtemp1. Time delay circuits 180 and 160 are coupled to temperature sensor 162 to receive a sense voltage Vtemp2 from temperature sensor 162 and provide voltages VG3 and VG4, respectively, based on sense voltage Vtemp2. As can be seen from the above description, time delay circuits 140, 120, 180, and 160 are used to provide voltages VG1, VG2, VG3, and VG4, respectively.

[0029] The control logic circuit 220 receives a pulse width modulation (PWM) signal SPWM and is coupled to the time delay circuits 120, 140, 160, and 180 to receive voltages VG1, VG2, VG3, and VG4, respectively. Figure 1 As shown, the control logic circuit 220 provides or generates logic signals SG1-SG4 based on the PWM signal SPWM and voltages VG1-VG4. Buffers BF buffer the logic signals SG1-SG4, respectively. Specifically, the logic signals SG1-SG4 are each enhanced in signal strength (enhanced in driving capability) by the buffers BF. The enhanced logic signals SG1, SG2, SG3, and SG4 serve as control signals SG10, SG20, SG30, and SG40, respectively. In other words, the control signals SG10, SG20, SG30, and SG40 are derived from the logic signals SG1, SG2, SG3, and SG4, respectively, by the buffers BF (i.e., the control signals SG10, SG20, SG30, and SG40 are derived from the logic signals SG1, SG2, SG3, and SG4, respectively). The buffer BF provides control signals SG10, SG20, SG30 and SG40 to the gates (also called control electrodes) G1, G2, G3 and G4 of the power semiconductor elements NM1, NM2, NM3 and NM4, respectively, to control or determine the on / off (on-off) states of the power semiconductor elements NM1, NM2, NM3 and NM4, respectively. Figure 1 In the embodiment, temperature sensors 122 and 162, time delay circuits 120, 140, 160, and 180, a buffer BF, and a control logic circuit 220 constitute a driver circuit 100 for providing or generating control signals SG10, SG20, SG30, and SG40 to drive power semiconductor devices NM1, NM2, NM3, and NM4, respectively. In other embodiments, the driver circuit 100 is constituted by the time delay circuits 120, 140, 160, and 180, a buffer BF, and a control logic circuit 220, and the temperature sensors 122 and 162 are disposed externally to the driver circuit 100.

[0030] The PWM signal SPWM is generated by the front stage circuit ( Figure 1 (not shown). The PWM signal SPWM can be switched or converted between a high voltage level and a low voltage level. When the PWM signal SPWM is switched or converted to a high voltage level, it instructs the voltage converter 1 to turn on its upper bridge portion (i.e., power semiconductor elements NM1 and NM2). At this time, the upper bridge portion charges the output capacitor Cout via the inductor L. When the PWM signal SPWM is switched or converted to a low voltage level, it instructs the voltage converter 1 to turn on its lower bridge portion (i.e., power semiconductor elements NM3 and NM4). At this time, the lower bridge portion discharges the output capacitor Cout via the inductor L. Through the charging and discharging operations on the output capacitor Cout, the voltage converter 1 generates the output voltage VOUT.

[0031] In voltage converter 1, power semiconductor element NM1 is connected in parallel with power semiconductor element NM2. Therefore, power semiconductor elements NM1 and NM2 share a common drain D1 and a common source S1. In an embodiment of the present invention, the safe operating area (SOA) of power semiconductor element NM1 is greater than that of power semiconductor element NM2. Therefore, power semiconductor element NM1 has a higher withstand voltage than power semiconductor element NM2. In an embodiment of the present invention, power semiconductor elements NM1 and NM2 are metal oxide semiconductor field effect transistors (MOSFETs), but the present invention is not limited thereto.

[0032] In the voltage converter 1, the power semiconductor element NM3 is connected in parallel with the power semiconductor element NM4. Therefore, the power semiconductor elements NM3 and NM4 have a common drain D3 and a common source S3. In the embodiment of the present invention, the safe operating area (SOA) of the power semiconductor element NM3 is greater than the safe operating area of the power semiconductor element NM4. Therefore, the power semiconductor element NM3 has a higher withstand voltage than the power semiconductor element NM4. In the embodiment of the present invention, the power semiconductor elements NM3 and NM4 are metal oxide semiconductor field effect transistors, but the present invention is not limited to this. Figure 1 , the source S1 and the drain D3 are the same electrode point, and the source S3 is coupled to the ground GND.

[0033] In an existing voltage converter, to increase the withstand voltage, the two power semiconductor elements of the upper bridge portion (the same applies to the lower bridge portion, which will not be described in detail here) are connected in a cascode manner. However, the cascode connection method increases the on-resistance of the upper bridge portion, resulting in poor switching efficiency of the upper bridge portion. In contrast, the present invention connects the two power semiconductor elements of the upper bridge portion (the same applies to the lower bridge portion, which will not be described in detail here) in parallel, significantly reducing the resistance during conduction. Therefore, compared to the above-mentioned existing voltage converter, the voltage converter of the present invention can use the same chip area to obtain a smaller on-resistance and can also achieve a higher withstand voltage voltage converter, so it can be used in higher voltage voltage conversion applications. Because of the smaller on-resistance, the loss during conduction is smaller and the switching efficiency is higher. On the other hand, it should be understood that if the on-resistance of the above-mentioned existing voltage converter and the voltage converter of the present invention is the same, the voltage converter of the present invention can use less chip area to achieve a higher cost-effectiveness.

[0034] Specifically, the voltage converter of the present invention connects two power semiconductor elements with different safe operating areas in parallel in the upper bridge part and the lower bridge part, respectively, to achieve a larger safe operating area (SOA) range, reduce on-resistance, reduce power loss during switching and chip area used, thereby increasing overall performance and using lower costs.

[0035] It is worth noting that in order for the voltage converter 1 to operate normally, the power semiconductor elements NM1 and NM2 of the upper bridge portion and the power semiconductor elements NM3 and NM4 of the lower bridge portion must be turned on and off in a specific order, as will be explained below.

[0036] Figure 2 1 is a signal timing diagram of the voltage converter 1 according to an embodiment of the present utility model. Figure 2As shown, time periods t1, t2, and t3 illustrate the process of turning on the high-side portion of voltage converter 1 (i.e., power semiconductor devices NM1 and NM2). At the start of time period t1, PWM signal SPWM switches or transitions from a low voltage level to a high voltage level, indicating that the high-side portion of voltage converter 1 is to be turned on. Simultaneously, logic signal SG4 transitions from a high voltage level to a low voltage level, thereby turning off power semiconductor device NM4 via the corresponding buffer BF. Next, at the start of time period t2, logic signal SG3 transitions from a high voltage level to a low voltage level, thereby turning off power semiconductor device NM4 via the corresponding buffer BF. Next, at the start of time period t3 (i.e., time T1), logic signal SG1 transitions from a low voltage level to a high voltage level, thereby turning on power semiconductor device NM1 via the corresponding buffer BF. Finally, at the end of time period t3 (i.e., time T2), logic signal SG2 transitions from a low voltage level to a high voltage level, thereby turning on power semiconductor device NM2 via the corresponding buffer BF.

[0037] Specifically, before turning on the upper bridge portion of the voltage converter 1, the lower bridge portion of the voltage converter 1 must be turned off first. In an embodiment of the present invention, because the range of the safe operating area of the power semiconductor element NM3 is larger than the range of the safe operating area of the power semiconductor element NM4, the turn-off time point of the power semiconductor element NM3 needs to be later than the turn-off time point of the power semiconductor element NM4, which can reduce the avalanche multiplication effect of the MOSFET. Specifically, the turn-off time point of the power semiconductor element NM3 needs to be later than the turn-off time point of the power semiconductor element NM4 to achieve the optimal timing for turning off the lower bridge portion, and ensure that the power semiconductor elements NM3 and NM4 are in the nominal operation area and will not be damaged. Therefore, if Figure 2 As shown, the power semiconductor element NM4 is turned off before the starting point of the time period t1 , and then the power semiconductor element NM3 is turned off after the starting point of the time period t2 .

[0038] In addition, to ensure that the voltage converter 1 can operate normally, there must be a time delay (i.e., time period t2) after the lower bridge portion of the voltage converter 1 is turned off before the upper bridge portion of the voltage converter 1 is turned on. This can avoid turning on the upper bridge portion before the lower bridge portion is turned off. Therefore, if Figure 2 As shown, after the power semiconductor element NM3 is turned off at the starting point of the time period t2, there is a time delay (ie, the time period t2), and then the power semiconductor element NM1 is turned on at the starting point of the time period t3 (ie, the time point T1).

[0039] After the lower bridge portion of the voltage converter 1 is turned off, the upper bridge portion of the voltage converter 1 is turned on. In the embodiment of the present invention, because the safe operating area (SOA) of the power semiconductor element NM1 is larger than the safe operating area of the power semiconductor element NM2, the turn-on time of the power semiconductor element NM1 must be earlier than the turn-on time of the power semiconductor element NM2 to achieve the optimal timing for turning on the upper bridge portion and ensure that the power semiconductor elements NM1 and NM2 are in a normal operating range without being damaged. Therefore, if Figure 2 As shown, the power semiconductor element NM1 is turned on before the starting point of the time period t3 , and then the power semiconductor element NM2 is turned on at the end point of the time period t3 .

[0040] Such as Figure 2 As shown, time periods t4, t5, and t6 illustrate the process of turning on the lower bridge portion of voltage converter 1 (i.e., power semiconductor devices NM3 and NM4). At the start of time period t4 (i.e., time T3), PWM signal SPWM transitions from a high voltage level to a low voltage level, indicating that the lower bridge portion of voltage converter 1 is to be turned on at this point. Simultaneously, logic signal SG2 transitions from a high voltage level to a low voltage level, thereby turning off power semiconductor device NM2 via the corresponding buffer BF. Next, at the start of time period t5 (i.e., time T4), logic signal SG1 transitions from a high voltage level to a low voltage level, thereby turning off power semiconductor device NM1 via the corresponding buffer BF. Next, at the start of time period t6, logic signal SG3 transitions from a low voltage level to a high voltage level, thereby turning on power semiconductor device NM3 via the corresponding buffer BF. Then, at the end of the time period t6 , the logic signal SG4 changes from a low voltage level to a high voltage level to turn on the power semiconductor device NM4 through the corresponding buffer BF.

[0041] Specifically, before turning on the lower bridge portion of the voltage converter 1, the upper bridge portion of the voltage converter 1 must be turned off first. In an embodiment of the present invention, because the range of the safe operating area of the power semiconductor element NM1 is larger than the range of the safe operating area of the power semiconductor element NM2, the turn-off time point of the power semiconductor element NM1 needs to be later than the turn-off time point of the power semiconductor element NM2, which can reduce the avalanche multiplication effect of the MOSFET. Specifically, the turn-off time point of the power semiconductor element NM1 needs to be later than the turn-off time point of the power semiconductor element NM2 to achieve the optimal timing for turning off the upper bridge portion and ensure that the power semiconductor elements NM1 and NM2 are in a normal operating range. Therefore, if Figure 2 As shown, the power semiconductor element NM2 is turned off before the starting point of the time period t4 , and then the power semiconductor element NM1 is turned off after the starting point of the time period t5 .

[0042] In addition, to ensure that the voltage converter 1 can operate normally, there must be a time delay (i.e., time period t5) after the upper bridge portion of the voltage converter 1 is turned off before the lower bridge portion of the voltage converter 1 is turned on. This can avoid turning on the lower bridge portion before the upper bridge portion is turned off. Figure 2 As shown, after the power semiconductor element NM1 is turned off at the starting point of the time period t5 (ie, time point T4), there is a time delay (ie, time period t5), and then the power semiconductor element NM3 is turned on at the starting point of the time period t6.

[0043] After the upper bridge portion of the voltage converter 1 is turned off, the lower bridge portion of the voltage converter 1 is turned on. In the embodiment of the present invention, because the safe operating area of the power semiconductor element NM3 is larger than the safe operating area of the power semiconductor element NM4, the turn-on time of the power semiconductor element NM3 needs to be earlier than the turn-on time of the power semiconductor element NM4. This ensures that the power semiconductor element NM4 is within the normal operating range when it is turned on, reaches the optimal timing for turning on the lower bridge portion, and ensures that the power semiconductor elements NM3 and NM4 are within the normal operating range. Therefore, if Figure 2 As shown, the power semiconductor element NM3 is turned on before the starting point of the time period t6 , and then the power semiconductor element NM4 is turned on at the end point of the time period t6 .

[0044] Figure 3 1 is an exemplary circuit diagram of a control logic circuit 220 according to an embodiment of the present invention. The control logic circuit 220 includes AND gates AND1 to AND4, OR gates OR1 and OR2, and delays DL1 and DL2. AND gate AND1 receives the PWM signal SPWM and the inverse of the logic signal SG3 (e.g. Figure 3 As shown, the logic signal SG3 passes through the inverter and is then received by the AND gate AND1) and the inverse of the logic signal SG4, one input end of the OR gate OR1 is coupled to the output end of the AND gate AND1 via the delay device DL1 (that is, the input end of the OR gate OR1 is coupled to the output end of the AND gate AND1), and the other input end thereof receives the voltage VG1, so that the OR gate OR1 outputs the logic signal SG1 accordingly. In other words, the control logic circuit 220 provides the logic signal SG1 according to the voltage VG1, the logic signals SG3 and SG4, and the PWM signal SPWM. The delay device DL1 provides a delay time. In one embodiment, the length of the delay time provided by the delay device DL1 is equal to Figure 2The length of the time period t2, therefore, the time period t2 can also be called the delay time. The AND gate AND2 receives the inverse of the PWM signal SPWM, the inverse of the logic signal SG1 and the inverse of the logic signal SG2. One input end of the OR gate OR2 is coupled to the output end of the AND gate AND2 via the delay device DL2 (that is, the input end of the OR gate OR2 is coupled to the output end of the AND gate AND2), and its other input end receives the voltage VG3, so that the OR gate OR2 outputs the logic signal SG3 accordingly. In other words, the control logic circuit 220 provides the logic signal SG3 according to the voltage VG3, the logic signals SG1 and SG2, and the PWM signal SPWM. The delay device DL2 provides a delay time. In one embodiment, the length of the delay time provided by the delay device DL2 is equal to Figure 2 The length of time period t5 is the same as that of time period t5. Therefore, time period t5 can also be referred to as a delay time. AND gate AND3 receives the PWM signal SPWM and voltage VG2 and outputs logic signal SG2 accordingly (in other words, control logic circuit 220 provides logic signal SG2 based on PWM signal SPWM and voltage VG2). AND gate AND4 receives the inverse of PWM signal SPWM and voltage VG4 and outputs logic signal SG4 accordingly (in other words, control logic circuit 220 provides logic signal SG4 based on PWM signal SPWM and voltage VG4).

[0045] Figure 4A FIG. 1 is an exemplary circuit diagram of the temperature sensor 122 and the time delay circuit 120 according to an embodiment of the present invention. Figure 4A As shown, the time delay circuit 120 receives the sensing voltage Vtemp1 from the temperature sensor 122. The time delay circuit 120 generates a reference voltage Vds1_adj according to the sensing voltage Vtemp1 and compares the reference voltage Vds1_adj with the drain-source voltage VDS1 (i.e., Figure 1 The voltage difference between the drain D1 and the source S1 of the transistor is used to generate a comparison result, and a voltage VG2 is output according to the comparison result.

[0046] In detail, Figure 4AAs shown, the time delay circuit 120 includes a current source ITH1, a resistor Rds1_adj, and a comparator CMP1. The current source ITH1 is coupled in series with the resistor Rds1_adj between the system voltage VDD and the ground GND. The positive input terminal (+) of the comparator CMP1 is coupled to the node between the current source ITH1 and the resistor Rds1_adj to receive a reference voltage Vds1_adj, and the negative input terminal (-) of the comparator CMP1 receives the drain-source voltage VDS1. The comparator CMP1 compares the reference voltage Vds1_adj with the drain-source voltage VDS1. When the reference voltage Vds1_adj is greater than the drain-source voltage VDS1, the comparator CMP1 outputs or generates a voltage VG2 at a high voltage level based on the comparison result. When the reference voltage Vds1_adj is less than the drain-source voltage VDS1, the comparator CMP1 outputs or generates a voltage VG2 at a low voltage level based on the comparison result.

[0047] like Figure 4A As shown, the resistor Rds1_adj receives the sensing voltage Vtemp1. Figure 4A In the embodiment, resistor Rds1_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) responsive to a sense voltage Vtemp1. As the sense voltage Vtemp1 increases, the resistance of resistor Rds1_adj increases accordingly. The current output by current source ITH1 does not change with temperature. In other words, because the sense voltage Vtemp1 increases with the temperature of power semiconductor components NM1 and NM2, the resistance of resistor Rds1_adj also increases with the temperature of power semiconductor components NM1 and NM2. Consequently, the reference voltage Vds1_adj increases with the temperature of power semiconductor components NM1 and NM2.

[0048] Figure 5 This is a signal timing diagram of the upper bridge portion of the voltage converter 1 in the conduction phase according to an embodiment of the present invention. Figures 1 to 4A 、 Figure 5 To further explain the detailed process of the upper bridge portion of the voltage converter 1 during the conduction phase. First, before time point T1, the logic signals SG1 and SG2 are both at a low voltage level (eg Figure 2 As shown), and the control signals SG10 and SG20 generated by the buffer BF are correspondingly at a low voltage level (as shown Figure 5 As shown). Figure 1 As shown, since the control signals SG10 and SG20 are respectively supplied to the gate G1 of the power semiconductor element NM1 and the gate G2 of the power semiconductor element NM2 , the power semiconductor elements NM1 and NM2 are turned off.

[0049] Then, at time point T1, the logic signal SG1 changes from a low voltage level to a high voltage level (eg Figure 2 As shown), this causes the control signal SG10 to change from a low voltage level to a high voltage level (as shown Figure 5 As shown in FIG, the control signal SG10 at a high voltage level turns on the power semiconductor element NM1.

[0050] Then, after the time point T1, since the power semiconductor element NM1 is turned on, the drain-source voltage VDS1 of the power semiconductor element NM1 gradually decreases (e.g. Figure 5 In addition, Figure 4A As shown, the temperature of the power semiconductor elements NM1 and NM2 will gradually increase due to the conduction of the power semiconductor element NM1, which will cause the reference voltage Vds1_adj to gradually increase. Until time point T2, the drain-source voltage VDS1 of the power semiconductor element NM1 is lower than the reference voltage Vds1_adj (as shown in FIG. Figure 5 As shown in FIG, the voltage VG2 output by the comparator CMP1 will change from a low voltage level to a high voltage level. Figure 2 It can be seen that at time point T2, the PWM signal SPWM is at a high voltage level. Figure 3 Due to the operation of the AND gate AND3, the logic signal SG2 is switched to a high voltage level at time point T2, which causes the control signal SG20 to also be a high voltage level. Therefore, the high voltage level control signal SG20 turns on the power semiconductor element NM2.

[0051] Specifically, the time delay circuit 120 controls the reference voltage Vds1_adj to be within the safe operating area of the power semiconductor element NM2 to ensure that the drain-source voltage VDS1 of the power semiconductor element NM2 when the power semiconductor element NM2 is turned on is also within the safe operating area of the power semiconductor element NM2. This ensures that the power semiconductor elements NM1 and NM2 are in a normal operating range.

[0052] The present invention uses a time delay circuit 120 to dynamically adjust the time delay (i.e., time period t3) between the turn-on time of power semiconductor element NM2 (i.e., time point T2) and the turn-on time of power semiconductor element NM1 (i.e., time point T1) based on the temperatures of power semiconductor elements NM1 and NM2. In other words, the aforementioned time delay is not a fixed length of time. Specifically, the high-bridge portion of the voltage converter 1 of the present invention has a mechanism for automatically adjusting its turn-on delay. This mechanism dynamically adjusts the turn-on delay based on varying temperatures to achieve the optimal turn-on timing for the high-bridge portion.

[0053] As described above, reference voltage Vds1_adj is associated with the temperature of power semiconductor devices NM1 and NM2. Specifically, reference voltage Vds1_adj increases with the temperature of power semiconductor devices NM1 and NM2, while being controlled within the safe operating area (SAA) of power semiconductor device NM2. Generally speaking, the SAA of a power semiconductor device varies with its operating temperature and / or process variations.

[0054] Therefore, in other embodiments of the present invention (such as Figure 4B In an embodiment), the voltage converter 1 may be coupled to or include a memory that stores a lookup table. The aforementioned memory may be provided in the drive circuit 100, for example, in the control logic circuit 220. This lookup table includes a plurality of different preset sensing voltage values as indexes, and includes a plurality of different preset reference voltage values as output values. The aforementioned plurality of different preset sensing voltages correspond to different temperature values or different temperature ranges of the power semiconductor element, and the aforementioned plurality of different preset reference voltages correspond to the ranges of different safe operating zones of the aforementioned power semiconductor element. In the lookup table, the aforementioned plurality of different preset sensing voltage values may respectively correspond to the aforementioned plurality of different preset reference voltage values, that is, respectively correspond to the ranges of different safe operating zones; or at least two of the aforementioned different preset sensing voltage values may correspond to the same preset reference voltage value, that is, correspond to the range of the same safe operating zone.

[0055] See Figure 4B In some embodiments, the time delay circuit 120 only includes the comparator CMP1 and does not include Figure 4A The current source ITH1 of the embodiment is a resistor Rds1_adj. The positive input terminal (+) of the comparator CMP1 receives the reference voltage Vds1_adj, and the negative input terminal (-) thereof receives the drain-source voltage VDS1. The voltage converter 1 (or the driver circuit 100 or the control logic circuit 220) searches the lookup table in the aforementioned memory according to the value of the sensing voltage Vtemp1 generated by the temperature sensor 122 (corresponding to a preset sensing voltage value in the aforementioned lookup table) to obtain the corresponding preset reference voltage value as the reference voltage Vds1_adj. As can be seen from the above, Figure 4B The reference voltage Vds1_adj increases as the temperature of the power semiconductor elements NM1 and NM2 increases, and corresponds to the range of the safe operating area of the power semiconductor element NM2 under the temperatures of the power semiconductor elements NM1 and NM2.

[0056] See Figure 1 、 Figure 2 、 Figure 4B and Figure 5 At time point T1, the logic signal SG1 changes from a low voltage level to a high voltage level (eg Figure 2 ), and the control signal SG10 changes from a low voltage level to a high voltage level (as shown Figure 5 In response to the conduction of the power semiconductor element NM1, the drain-source voltage VDS1 of the power semiconductor element NM1 gradually decreases (as shown in FIG. Figure 5 In addition, Figure 4B As shown, the temperature of the power semiconductor elements NM1 and NM2 gradually rises due to the conduction of the power semiconductor element NM1, which causes the reference voltage Vds1_adj to gradually increase. Until time point T2, the drain-source voltage VDS1 is lower than the reference voltage Vds1_adj (as shown in FIG. Figure 5 As shown in FIG, the voltage VG2 output by the comparator CMP1 will change from a low voltage level to a high voltage level. Figure 2 It can be seen that at time point T2, the PWM signal SPWM is at a high voltage level. Figure 3 Due to the operation of AND gate AND3, logic signal SG2 switches to a high voltage level at time point T2, which causes control signal SG20 to also be at a high voltage level. Therefore, the high voltage level of control signal SG20 turns on power semiconductor device NM2. In this way, time delay circuit 120 can dynamically adjust the time delay (i.e., time period t3) between the turn-on time point of power semiconductor device NM2 (i.e., time point T2) and the turn-on time point of power semiconductor device NM1 (i.e., time point T1) based on the temperatures of power semiconductor devices NM1 and NM2.

[0057] Figure 6A FIG. 1 is an exemplary circuit diagram of the temperature sensor 122 and the time delay circuit 140 according to an embodiment of the present invention. Figure 6A As shown, the time delay circuit 140 receives the sensing voltage Vtemp1 from the temperature sensor 122 and the control signal SG20. The time delay circuit 140 generates a reference voltage Vgs2_adj based on the sensing voltage Vtemp1, compares the reference voltage Vgs2_adj with the voltage level of the control signal SG20 to generate a comparison result, and outputs a voltage VG1 based on the comparison result.

[0058] In detail, Figure 6AAs shown, the time delay circuit 140 includes a current source ITH2, a resistor Rgs2_adj, and a comparator CMP2. The current source ITH2 is coupled in series with the resistor Rgs2_adj between the system voltage VDD and the ground GND. The negative input terminal (-) of the comparator CMP2 is coupled to the node between the current source ITH2 and the resistor Rgs2_adj to receive the reference voltage Vgs2_adj, and the positive input terminal (+) of the comparator CMP2 receives the control signal SG20. The comparator CMP2 compares the voltage level of the control signal SG20 with the reference voltage Vgs2_adj. When the voltage level of the control signal SG20 is greater than the reference voltage Vgs2_adj, the comparator CMP2 outputs or generates a voltage VG1 at a high voltage level at its output terminal based on the comparison result. When the voltage level of the control signal SG20 is less than the reference voltage Vgs2_adj, the comparator CMP2 outputs or generates a voltage VG1 at a low voltage level at its output terminal based on the comparison result.

[0059] like Figure 6A As shown, the resistor Rgs2_adj receives the sensing voltage Vtemp1. Figure 6A In the embodiment, resistor Rgs2_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) responsive to sense voltage Vtemp1. As sense voltage Vtemp1 decreases, the resistance of resistor Rgs2_adj increases. The current output by current source ITH2 does not change with temperature. In other words, because sense voltage Vtemp1 decreases as the temperature of power semiconductor components NM1 and NM2 decreases, the resistance of resistor Rgs2_adj also increases as the temperature of power semiconductor components NM1 and NM2 decreases. Consequently, reference voltage Vgs2_adj increases as the temperature of power semiconductor components NM1 and NM2 decreases.

[0060] Figure 7 This is a signal timing diagram of the upper bridge portion of the voltage converter 1 in the shutdown phase according to an embodiment of the present invention. Figures 1 to 3 、 Figure 6A and Figure 7 To further explain the detailed process of the upper bridge portion of the voltage converter 1 during the shutdown phase. First, before time point T3, the logic signals SG1 and SG2 are both at a high voltage level (eg Figure 2 As shown), and the control signals SG10 and SG20 generated by the buffer BF are correspondingly at a high voltage level (as shown Figure 7 As shown). Figure 1 As shown, since the control signals SG10 and SG20 are respectively supplied to the gate G1 of the power semiconductor element NM1 and the gate G2 of the power semiconductor element NM2 , the power semiconductor elements NM1 and NM2 are turned on.

[0061] Then, at time point T3, the logic signal SG2 changes from a high voltage level to a low voltage level (eg Figure 2 As shown), this will cause the control signal SG20 to gradually decrease from a high voltage level to a low voltage level (as shown Figure 7 As shown), the control signal SG20 gradually turns off the power semiconductor element NM2.

[0062] Furthermore, after time point T3, since the power semiconductor element NM2 is gradually turned off, the temperatures of the power semiconductor elements NM1 and NM2 gradually decrease due to the gradual turn-off of the power semiconductor element NM2, which causes the reference voltage Vgs2_adj to gradually increase. Until time point T4, the voltage level of the control signal SG20 is lower than the reference voltage Vgs2_adj (e.g. Figure 7 As shown in FIG, the voltage VG1 output by the comparator CMP2 will change from a high voltage level to a low voltage level. Figure 2 It can be seen that at time point T4, the PWM signal SPWM is at a low voltage level. Figure 3 By the operation of AND gate AND1 and OR gate OR1, logic signal SG1 switches from high voltage level to low voltage level at time point T4, which causes control signal SG10 to gradually decrease from high voltage level to low voltage level (e.g. Figure 7 As shown), the control signal SG10 gradually turns off the power semiconductor element NM1.

[0063] Specifically, the time delay circuit 140 controls the reference voltage Vgs2_adj to be within the shutdown operating range of the power semiconductor device NM2. Furthermore, the time delay circuit 140 dynamically adjusts the shutdown delay of the power semiconductor device NM1 to ensure that the power semiconductor device NM2 is fully shut down before shutting down the power semiconductor device NM1. This ensures that the power semiconductor devices NM1 and NM2 remain within the normal operating range and are not damaged.

[0064] The present invention uses a time delay circuit 140 to dynamically adjust the time delay (i.e., time period t4) between the turn-off time of power semiconductor element NM1 (i.e., time point T4) and the turn-off time of power semiconductor element NM2 (i.e., time point T3) based on the temperatures of power semiconductor elements NM1 and NM2. In other words, the aforementioned time delay is not a fixed time length. Specifically, the high-bridge portion of the voltage converter 1 of the present invention has a mechanism for automatically adjusting its turn-off delay. This mechanism dynamically adjusts the turn-off delay based on different temperatures to achieve the optimal turn-off timing of the high-bridge portion.

[0065] As described above, reference voltage Vgs2_adj is generated by current source ITH2 and resistor Rgs2_adj based on sense voltage Vtemp1 and is correlated to the temperature of power semiconductor devices NM1 and NM2. Specifically, reference voltage Vgs2_adj increases as the temperature of power semiconductor devices NM1 and NM2 decreases. In other embodiments, reference voltage Vgs2_adj represents the threshold voltage (Vth) of power semiconductor device NM2. Generally, the threshold voltage of a power semiconductor device varies with operating temperature and / or process variations.

[0066] In other embodiments of the present invention, the voltage converter 1 may be coupled to or include a memory that stores a lookup table. The aforementioned memory may be provided in the drive circuit 100, for example, in the control logic circuit 220. This lookup table includes a plurality of different preset sensing voltage values as indexes, and includes a plurality of different preset reference voltage values as output values. The aforementioned plurality of different preset sensing voltages correspond to different temperature values or different temperature ranges of the power semiconductor element, and the aforementioned plurality of different preset reference voltages correspond to different threshold voltages of the aforementioned power semiconductor element. In the lookup table, the aforementioned plurality of different preset sensing voltage values may respectively correspond to the aforementioned plurality of different preset reference voltage values, that is, respectively correspond to different threshold voltages; or at least two of the aforementioned different preset sensing voltage values may correspond to the same preset reference voltage value, that is, correspond to the same threshold voltage.

[0067] See Figure 6B In some embodiments, the time delay circuit 140 includes only the comparator CMP2 and does not include Figure 6A The current source ITH2 of the embodiment is a resistor Rgs2_adj. The positive input terminal (+) of the comparator CMP1 receives the control signal SG20, and the negative input terminal (-) thereof receives the reference voltage Vgs2_adj. The voltage converter 1 (or the driver circuit 100 or the control logic circuit 220) searches the lookup table in the aforementioned memory according to the value of the sensing voltage Vtemp1 generated by the temperature sensor 122 (corresponding to a preset sensing voltage value in the aforementioned lookup table) to obtain the corresponding preset reference voltage value as the reference voltage Vgs2_adj. As can be seen from the above, Figure 6B The reference voltage Vgs2_adj increases as the temperature of the power semiconductor elements NM1 and NM2 decreases, and corresponds to the threshold voltage of the power semiconductor element NM2 at the temperature of the power semiconductor elements NM1 and NM2.

[0068] See Figure 1 、 Figure 2 、 Figure 6B and Figure 7At time point T1, at time point T3, the logic signal SG2 changes from a high voltage level to a low voltage level (eg Figure 2 As shown), the control signal SG20 also gradually decreases from a high voltage level to a low voltage level (as shown Figure 7 As shown in FIG4 , the control signal SG20 is gradually turned off to gradually turn off the power semiconductor element NM2. In response to the gradual turn-off of the power semiconductor element NM2, the temperatures of the power semiconductor elements NM1 and NM2 gradually decrease due to the gradual turn-off of the power semiconductor element NM2, which causes the reference voltage Vgs2_adj to gradually increase. Until time point T4, the control signal SG20 is already less than the reference voltage Vgs2_adj (as shown in FIG4 ). Figure 7 As shown in FIG, the voltage VG1 output by the comparator CMP2 will change from a high voltage level to a low voltage level. Figure 2 It can be seen that at time point T4, the PWM signal SPWM is at a low voltage level. Figure 3 By the operation of AND gate AND1 and OR gate OR1, logic signal SG1 switches from high voltage level to low voltage level at time point T4, which causes control signal SG10 to gradually decrease from high voltage level to low voltage level (e.g. Figure 7 As shown in FIG. 1 , control signal SG10 gradually turns off power semiconductor device NM1. In this way, time delay circuit 140 dynamically adjusts the time delay (i.e., time period t4) between the turn-off point of power semiconductor device NM1 (i.e., time point T4) and the turn-off point of power semiconductor device NM2 (i.e., time point T3) according to the temperatures of power semiconductor devices NM1 and NM2.

[0069] Figure 8 is another exemplary circuit diagram of the time delay circuit 120 according to an embodiment of the present invention. Figure 8 The time delay circuit 120 and Figure 4A The time delay circuit 120 is similar to the time delay circuit 120, the difference is Figure 4A The current source ITH1 of the time delay circuit 120 and the resistor Rds1_adj are Figure 8 The time delay circuit 120 is replaced by a current source ITH1_adj and a resistor Rds1. Specifically, Figure 8 The time delay circuit 120 has the Figure 4A The time delay circuit 120 has a similar function, so the Figure 1 The time delay circuit 120 of the illustrated embodiment may also be used Figure 8 This is achieved by the time delay circuit 120.

[0070] In detail, Figure 8As shown, the current source ITH1_adj is coupled in series with the resistor Rds1 between the system voltage VDD and the ground GND, and the current source ITH1_adj receives the sensing voltage Vtemp1. Figure 8 In this embodiment, current source ITH1_adj is a voltage-controlled element (i.e., a voltage-controlled current source) responsive to a sense voltage Vtemp1. As sense voltage Vtemp1 increases, the current of current source ITH1_adj increases accordingly. The resistance of resistor Rds1 does not change with temperature. In other words, because sense voltage Vtemp1 increases with the temperature of power semiconductor components NM1 and NM2, the current output by current source ITH1_adj also increases with the temperature of power semiconductor components NM1 and NM2. Consequently, reference voltage Vds1_adj increases with the temperature of power semiconductor components NM1 and NM2.

[0071] Figure 9 is another exemplary circuit diagram of the time delay circuit 140 according to an embodiment of the present invention. Figure 9 The time delay circuit 140 and Figure 6A The time delay circuit 140 is similar to the time delay circuit 140, the difference is Figure 6A The current source ITH2 of the time delay circuit 140 and the resistor Rgs2_adj are Figure 9 The time delay circuit 140 is replaced by a current source ITH2_adj and a resistor Rgs2. Specifically, Figure 9 The time delay circuit 140 has the Figure 6A The time delay circuit 140 has a similar function, so the Figure 1 The time delay circuit 140 of the illustrated embodiment may also be used Figure 9 This is achieved by the time delay circuit 140.

[0072] In detail, Figure 9 As shown, the current source ITH2_adj is coupled in series with the resistor Rgs2 between the system voltage VDD and the ground GND, and the current source ITH2_adj receives the sensing voltage Vtemp1. Figure 9In this embodiment, current source ITH2_adj is a voltage-controlled element (i.e., a voltage-controlled current source) responsive to sense voltage Vtemp1. As sense voltage Vtemp1 decreases, the current of current source ITH2_adj increases accordingly. The resistance of resistor Rgs2 does not change with temperature. In other words, because sense voltage Vtemp1 decreases as the temperature of power semiconductor components NM1 and NM2 decreases, the current output by current source ITH2_adj also increases as the temperature of power semiconductor components NM1 and NM2 decreases. Consequently, reference voltage Vgs2_adj increases as the temperature of power semiconductor components NM1 and NM2 decreases.

[0073] Figure 10A FIG is an exemplary circuit diagram of the temperature sensor 162 and the time delay circuit 160 according to an embodiment of the present invention. Figure 10A As shown, the time delay circuit 160 receives the sensing voltage Vtemp2 from the temperature sensor 162. The time delay circuit 160 generates a reference voltage Vds3_adj according to the sensing voltage Vtemp2 and compares the reference voltage Vds3_adj with the drain-source voltage VDS3 (i.e., Figure 1 The voltage difference between the drain D3 and the source S3 is used to generate a comparison result, and a voltage VG4 is output according to the comparison result.

[0074] In detail, Figure 10A As shown, time delay circuit 160 includes a current source ITH3, a resistor Rds3_adj, and a comparator CMP3. Current source ITH3 is coupled in series with resistor Rds3_adj between system voltage VDD and ground GND. A positive input terminal (+) of comparator CMP3 is coupled to a node between current source ITH3 and resistor Rds3_adj to receive a reference voltage Vds3_adj, and a negative input terminal (-) of comparator CMP3 receives a drain-source voltage VDS3 of power semiconductor device NM3. Comparator CMP3 compares reference voltage Vds3_adj with drain-source voltage VDS3. When reference voltage Vds3_adj is greater than drain-source voltage VDS3, comparator CMP3 generates or outputs a voltage VG4 at its output terminal at a high voltage level based on the comparison result. When the reference voltage Vds3_adj is lower than the drain-source voltage VDS3 , the voltage VG4 output or generated at the output terminal of the comparator CMP3 according to the comparison result is a low voltage level.

[0075] like Figure 10A As shown, the resistor Rds3_adj receives the sensing voltage Vtemp2. Figure 10AIn the embodiment of the present invention, the resistor Rds3_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) that responds to the sensing voltage Vtemp2. When the sensing voltage Vtemp2 increases, the resistance value of the resistor Rds3_adj will increase accordingly. The current output by the current source ITH3 does not change with temperature. In other words, since the sensing voltage Vtemp2 increases with the increase in the temperature of the power semiconductor elements NM3 and NM4, the resistance value of the resistor Rds3_adj will also increase with the increase in the temperature of the power semiconductor elements NM3 and NM4. In this way, the reference voltage Vds3_adj will increase with the increase in the temperature of the power semiconductor elements NM3 and NM4. The operation of the time delay circuit 160 is similar in operation logic to Figure 4A The operation of the time delay circuit 120 is omitted here for detailed operation description.

[0076] As described above, reference voltage Vds3_adj is associated with the temperature of power semiconductor devices NM3 and NM4. Specifically, reference voltage Vds3_adj increases with the temperature of power semiconductor devices NM3 and NM4, while remaining within the safe operating area (SAA) of power semiconductor device NM2. Generally speaking, the SAA of a power semiconductor device varies with its operating temperature and / or process variations.

[0077] Therefore, in other embodiments of the present invention (such as Figure 10B In an embodiment of the present invention, the voltage converter 1 may be coupled to or include a memory that stores a lookup table. The memory may be disposed within the driver circuit 100, for example, within the control logic circuit 220. The lookup table includes a plurality of different preset sensing voltage values as indexes and a plurality of different preset reference voltage values as output values. The plurality of different preset sensing voltages correspond to different temperature values or temperature ranges of the power semiconductor device, while the plurality of different preset reference voltages correspond to different safe operating area ranges of the power semiconductor device.

[0078] See Figure 10B In some embodiments, the time delay circuit 160 includes only the comparator CMP3 and does not include Figure 10A The current source ITH3 of the embodiment is connected to the resistor Rds3_adj. The positive input terminal (+) of the comparator CMP3 receives the reference voltage Vds3_adj, and the negative input terminal (-) of the comparator CMP3 receives the drain-source voltage VDS3. The voltage converter 1 (or the driver circuit 100 or the control logic circuit 220) searches the memory lookup table based on the value of the sensed voltage Vtemp2 generated by the temperature sensor 162 (corresponding to a preset sensed voltage value in the lookup table) to obtain the corresponding preset reference voltage value as the reference voltage Vds3_adj. Figure 10B The reference voltage Vds3_adj increases as the temperature of the power semiconductor elements NM3 and NM4 increases, and corresponds to the range of the safe operating area of the power semiconductor element NM4 under the temperatures of the power semiconductor elements NM3 and NM4. Figure 10B The operation of the time delay circuit 160 is similar in operation logic to Figure 4B The operation of the time delay circuit 120 is omitted here for detailed operation description. Figure 10B In the embodiment, the time delay circuit 160 can dynamically adjust the time delay (ie, time period t6 ) between the turn-on timings of the power semiconductor elements NM4 and NM3 according to the temperatures of the power semiconductor elements NM3 and NM4 .

[0079] In some embodiments, when using Figure 4B and Figure 10B In the embodiment of the present invention, the voltage converter 1 may be coupled to or include a memory storing a lookup table for obtaining the reference voltages Vds1_adj and Vds3_adj.

[0080] Figure 11A FIG is an exemplary circuit diagram of the temperature sensor 162 and the time delay circuit 180 according to an embodiment of the present invention. Figure 11A As shown, the time delay circuit 180 receives the sensing voltage Vtemp2 from the temperature sensor 162. The time delay circuit 180 generates a reference voltage Vgs4_adj according to the sensing voltage Vtemp2, and compares the reference voltage Vgs4_adj with the voltage level of the control signal SG40 to generate a comparison result, and outputs a voltage VG3 according to the comparison result.

[0081] In detail, Figure 11A As shown, time delay circuit 180 includes a current source ITH4, a resistor Rgs4_adj, and a comparator CMP4. Current source ITH4 is coupled in series with resistor Rgs4_adj between system voltage VDD and ground GND. A negative input terminal (-) of comparator CMP4 is coupled to a node between current source ITH4 and resistor Rgs4_adj to receive a reference voltage Vgs4_adj, and a positive input terminal (+) of comparator CMP4 receives the reference voltage Vgs4_adj. Comparator CMP4 compares the voltage level of control signal SG40 with the reference voltage Vgs4_adj. When the voltage level of control signal SG40 is greater than the reference voltage Vgs4_adj, comparator CMP4 outputs or generates a voltage VG3 at its output terminal at a high voltage level based on the comparison result. When the voltage level of control signal SG40 is less than the reference voltage Vgs4_adj, comparator CMP4 outputs or generates a voltage VG3 at its output terminal at a low voltage level based on the comparison result.

[0082] like Figure 11A As shown, the resistor Rgs4_adj receives the sensing voltage Vtemp2. Figure 11A In the embodiment of the present invention, the resistor Rgs4_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) that responds to the sensing voltage Vtemp2. When the sensing voltage Vtemp2 decreases, the resistance value of the resistor Rgs4_adj will increase accordingly. In addition, the current output by the current source ITH4 does not change with temperature changes. In other words, since the sensing voltage Vtemp2 decreases as the temperature of the power semiconductor elements NM3 and NM4 decreases, the resistance value of the resistor Rgs4_adj will also increase as the temperature of the power semiconductor elements NM3 and NM4 decreases. In this way, the reference voltage Vgs4_adj will increase as the temperature of the power semiconductor elements NM3 and NM4 decreases. The operation of the time delay circuit 180 is similar in operation logic to Figure 6A The operation of the time delay circuit 140 is omitted here for detailed operation description.

[0083] As described above, reference voltage Vgs4_adj is generated by current source ITH4 and resistor Rgs4_adj based on sense voltage Vtemp2 and is correlated to the temperature of power semiconductor devices NM3 and NM4. Specifically, reference voltage Vgs4_adj increases as the temperature of power semiconductor devices NM3 and NM4 decreases. In other embodiments, reference voltage Vgs4_adj represents the threshold voltage of power semiconductor device NM4. Generally, the threshold voltage of a power semiconductor device varies with operating temperature and / or process variations.

[0084] In other embodiments of the present invention, the voltage converter 1 may be coupled to or include a memory that stores a lookup table. The memory may be disposed within the driver circuit 100, for example, within the control logic circuit 220. The lookup table includes a plurality of different preset sensing voltage values as indexes and a plurality of different preset reference voltage values as output values. The plurality of different preset sensing voltages correspond to different temperature values or temperature ranges of the power semiconductor device, while the plurality of different preset reference voltages correspond to different threshold voltages of the power semiconductor device.

[0085] See Figure 11B In some embodiments, the time delay circuit 180 includes only the comparator CMP4 and does not include Figure 11AThe current source ITH4 resistor Rgs4_adj of the embodiment. The positive input terminal (+) of the comparator CMP4 receives the control signal SG40, and the negative input terminal (-) thereof receives the reference voltage Vgs4_adj. The voltage converter 1 (or the driver circuit 100 or the control logic circuit 220) searches the lookup table in the aforementioned memory according to the value of the sensing voltage Vtemp2 generated by the temperature sensor 162 (corresponding to a preset sensing voltage value in the aforementioned lookup table) to obtain the corresponding preset reference voltage value as the reference voltage Vgs4_adj. As can be seen from the above, Figure 11B The reference voltage Vgs4_adj increases as the temperature of the power semiconductor elements NM3 and NM4 decreases, and corresponds to the threshold voltage of the power semiconductor element NM4 at the temperature of the power semiconductor elements NM3 and NM4. Figure 11B The operation of the time delay circuit 180 is similar in operation logic to Figure 6B The operation of the time delay circuit 140 is omitted here for detailed operation description. Figure 11B In the embodiment, the time delay circuit 180 can dynamically adjust the time delay (ie, time period t1) between the turn-off timings of the power semiconductor elements NM3 and NM4 according to the temperatures of the power semiconductor elements NM3 and NM4.

[0086] In some embodiments, when using Figure 6B and Figure 11B In the embodiment of the present invention, the voltage converter 1 may be coupled to or include a memory storing a lookup table for obtaining the reference voltages Vgs2_adj and Vgs4_adj.

[0087] In other embodiments, when using Figure 4B 、 Figure 6B 、 Figure 10B and Figure 11B In the embodiment of the present invention, the voltage converter 1 may be coupled to or include a memory that stores two lookup tables, one of which is used to obtain the reference voltages Vds1_adj and Vds3_adj, and the other is used to obtain the reference voltages Vgs2_adj and Vgs4_adj. Figure 4B 、 Figure 6B 、 Figure 10B and Figure 11B In the case of the embodiment, the time periods t1, t3, t4, and t6 can be shortened and the Figure 3 The delay devices DL1 and DL2 are omitted to improve the operating efficiency of the voltage converter 1. Figure 3 In the case of the delay devices DL1 and DL2, the input terminal of the OR gate OR1 is directly coupled to the output terminal of the AND gate AND1, and the input terminal of the OR gate OR2 is directly coupled to the output terminal of the AND gate AND2.

[0088] Figure 12 is another exemplary circuit diagram of the time delay circuit 160 according to an embodiment of the present invention. Figure 12 The time delay circuit 160 and Figure 10A The time delay circuit 160 is similar to the time delay circuit 160, the difference is Figure 10A The current source ITH3 of the time delay circuit 160 and the resistor Rds3_adj are Figure 12 The time delay circuit 160 is replaced by a current source ITH3_adj and a resistor Rds3. Specifically, Figure 12 The time delay circuit 160 has the Figure 10A The time delay circuit 160 has a similar function, so the Figure 1 The time delay circuit 160 of the illustrated embodiment may also be used Figure 12 This is achieved by the time delay circuit 160.

[0089] In detail, Figure 12 As shown, the current source ITH3_adj is coupled in series with the resistor Rds3 between the system voltage VDD and the ground GND, and the current source ITH3_adj receives the sensing voltage Vtemp2. Figure 12 In the embodiment, current source ITH3_adj is a voltage-controlled element (i.e., a voltage-controlled current source) responsive to a sense voltage Vtemp2. As the sense voltage Vtemp2 increases, the current of current source ITH3_adj increases accordingly. The resistance of resistor Rds3 does not change with temperature. In other words, because the sense voltage Vtemp2 increases with the temperature of power semiconductor components NM3 and NM4, the current output by current source ITH3_adj also increases with the temperature of power semiconductor components NM3 and NM4. Consequently, reference voltage Vds3_adj increases with the temperature of power semiconductor components NM3 and NM4.

[0090] Figure 13 is another exemplary circuit diagram of the time delay circuit 180 according to an embodiment of the present invention. Figure 13 The time delay circuit 180 and Figure 11A The time delay circuit 180 is similar to the time delay circuit 180, the difference is Figure 11A The current source ITH4 and the resistor Rgs4_adj of the time delay circuit 180 are connected in a Figure 13 The time delay circuit 180 is replaced by a current source ITH4_adj and a resistor Rgs4. Specifically, Figure 13 The time delay circuit 180 has the Figure 11A The time delay circuit 180 has similar functions, so the Figure 1The time delay circuit 180 of the illustrated embodiment may also be used Figure 13 This is achieved by the time delay circuit 180.

[0091] In detail, Figure 13 As shown, the current source ITH4_adj is coupled in series with the resistor Rgs4 between the system voltage VDD and the ground GND, and the current source ITH4_adj receives the sensing voltage Vtemp2. Figure 13 In the embodiment, current source ITH4_adj is a voltage-controlled element (i.e., a voltage-controlled current source) responsive to a sense voltage Vtemp2. As the sense voltage Vtemp2 decreases, the current of current source ITH4_adj increases accordingly. The resistance of resistor Rgs4 does not change with temperature. In other words, because the sense voltage Vtemp2 decreases as the temperature of power semiconductor components NM3 and NM4 decreases, the current output by current source ITH4_adj also increases as the temperature of power semiconductor components NM3 and NM4 decreases. Consequently, reference voltage Vgs4_adj increases as the temperature of power semiconductor components NM3 and NM4 decreases.

[0092] The following will cooperate Figures 1 to 4A 、 Figure 6A 、 Figure 10A 、 Figure 11A To explain in detail the detailed process of the voltage converter 1 in various stages. Before the starting point of the time period t1, the logic signals SG1 and SG2 are at a low voltage level. At the starting point of the time period t1, the PWM signal SPWM changes from a low voltage level to a high voltage level, indicating that the upper bridge part of the voltage converter 1 (i.e., the power semiconductor elements NM1 and NM2) is intended to be turned on. Therefore, the lower bridge part of the voltage converter 1 (i.e., the power semiconductor elements NM3 and NM4) must be turned off first. In addition, because the range of the safe operating area of the power semiconductor element NM3 is larger than the range of the safe operating area of the power semiconductor element NM4, the turn-off time of the power semiconductor element NM3 must be later than the turn-off time of the power semiconductor element NM4. By Figure 3 It can be seen that at this time, the inverse of the PWM signal SPWM received by the AND gate AND4 changes from a high voltage level to a low voltage level, so the logic signal SG4 output by the AND gate AND4 changes from a high voltage level to a low voltage level.

[0093] As described above, at the start of time period t1, logic signal SG4 transitions from a high voltage level to a low voltage level, causing control signal SG40 to gradually decrease from a high voltage level to a low voltage level during time period t1. Therefore, control signal SG40 gradually turns off power semiconductor element NM4. As power semiconductor element NM4 gradually turns off, the temperatures of power semiconductor elements NM3 and NM4 gradually decrease, causing reference voltage Vgs4_adj to gradually increase. By the end of time period t1, control signal SG40 is already less than reference voltage Vgs4_adj. Figure 11A The voltage VG3 output by the comparator CMP4 of the time delay circuit 180 will then change from a high voltage level to a low voltage level. Figure 2 It can be seen that at the end of the time period t1, the PWM signal SPWM is at a high voltage level. Figure 3 Due to the operation of the AND gate AND2, the delay device DL2, and the OR gate OR2, the logic signal SG3 changes from a high voltage level to a low voltage level, which causes the control signal SG30 to gradually decrease from a high voltage level to a low voltage level. Therefore, the control signal SG30 gradually turns off the power semiconductor element NM3.

[0094] As described above, at the start point of time period t2 (i.e., the end point of time period t1), logic signal SG3 changes from a high voltage level to a low voltage level. During time period t2, based on the operation of time delay circuit 140, output voltage VG1 is at a low voltage level, which makes OR gate OR1 depend on the output signal of AND gate AND1. Figure 3 The AND gate AND1 and the OR gate OR1 operate as the logic signal SG3 transitions to a low voltage level. At the end of time period t2, the logic signal SG1 transitions from a low voltage level to a high voltage level, thereby turning on the power semiconductor device NM1. It is worth noting that the delay device DL1 is coupled between the AND gate AND1 and the OR gate OR1 (i.e., the input terminal of the OR gate OR1 is coupled to the output terminal of the AND gate AND1 via the delay device DL1). Therefore, after the output signal of the AND gate AND1 transitions from a low voltage level to a high voltage level in response to the transition of the logic signal SG3 from a high voltage level, a further time period t2 (i.e., the delay time of the delay device DL1) must elapse before the logic signal SG1 transitions from a low voltage level to a high voltage level.

[0095] Next, during time period t3, since the power semiconductor element NM1 is turned on, the drain-source voltage VDS1 of the power semiconductor element NM1 gradually decreases, and the temperatures of the power semiconductor elements NM1 and NM2 rise, which causes the reference voltage Vds1_adj to gradually increase. At the end of time period t3 (time point T2), the drain-source voltage VDS1 of the power semiconductor element NM1 is lower than the reference voltage Vds1_adj. Figure 4A The voltage VG2 output by the comparator CMP1 of the time delay circuit 120 will then change from a low voltage level to a high voltage level. Figure 3 With the operation of the AND gate AND3, at the end of the time period t3, the logic signal SG2 changes from a low voltage level to a high voltage level, thereby turning on the power semiconductor device NM2.

[0096] Then, at the start of time period t4, the PWM signal SPWM changes from a high voltage level to a low voltage level, indicating that the lower bridge portion of the voltage converter 1 (i.e., power semiconductor elements NM3 and NM4) is to be turned on. Therefore, the upper bridge portion of the voltage converter 1 (i.e., power semiconductor elements NM1 and NM2) must be turned off first. In addition, because the safe operating area of the power semiconductor element NM1 is larger than the safe operating area of the power semiconductor element NM2, the turn-off time of the power semiconductor element NM1 must be later than the turn-off time of the power semiconductor element NM2. Figure 3 It can be seen that at this time, the PWM signal SPWM received by the AND gate AND3 changes from a high voltage level to a low voltage level, so the logic signal SG2 output by the AND gate AND3 changes from a high voltage level to a low voltage level.

[0097] As described above, at the start point of time period t4 (i.e., time point T3), logic signal SG2 changes from a high voltage level to a low voltage level, which causes control signal SG20 to gradually decrease from a high voltage level to a low voltage level during time period t4. Therefore, control signal SG20 gradually turns off power semiconductor element NM2. As power semiconductor element NM2 is gradually turned off, the temperature of power semiconductor elements NM1 and NM2 gradually decreases, which causes reference voltage Vgs2_adj to gradually increase. By the end point of time period t4 (i.e., time point T4), control signal SG20 is already less than reference voltage Vgs2_adj. Figure 6A The voltage VG1 output by the comparator CMP2 of the time delay circuit 140 will then change from a high voltage level to a low voltage level. Figure 2 It can be seen that at the end of the time period t4, the PWM signal SPWM is at a low voltage level. Figure 3With the operation of the AND gate AND1 and the OR gate OR1, the logic signal SG1 changes from a high voltage level to a low voltage level, which causes the control signal SG10 to gradually decrease from a high voltage level to a low voltage level. Therefore, the control signal SG10 gradually turns off the power semiconductor element NM1.

[0098] As described above, at the start point of time period t5 (i.e., time point T4), logic signal SG1 changes from a high voltage level to a low voltage level. During time period t5, due to the operation of time delay circuit 180, output voltage VG3 is at a low voltage level, which makes OR gate OR2 depend on the output signal of AND gate AND2. Figure 3 In the operation of AND gate AND2 and OR gate OR2, as logic signal SG1 transitions to a low voltage level, logic signal SG3 transitions from a low voltage level to a high voltage level at the end of time period t5, thereby turning on power semiconductor device NM3. It is worth noting that delay element DL2 is coupled between AND gate AND2 and OR gate OR2 (i.e., the input of OR gate OR2 is coupled to the output of AND gate AND2 via delay element DL2). Therefore, after AND gate AND2 transitions its output signal from a low voltage level to a high voltage level in response to the transition of logic signal SG1 from a high voltage level to a low voltage level, time period t5 (i.e., the delay time of delay element DL2) must elapse before logic signal SG3 transitions from a low voltage level to a high voltage level.

[0099] Next, during time period t6, since the power semiconductor element NM3 is turned on, the drain-source voltage VDS3 of the power semiconductor element NM3 gradually decreases, and the temperatures of the power semiconductor elements NM3 and NM4 rise, which causes the reference voltage Vds3_adj to gradually increase. At the end of time period t6, the drain-source voltage VDS3 of the power semiconductor element NM3 is lower than the reference voltage Vds3_adj. Figure 10A The voltage VG4 output by the comparator CMP3 of the time delay circuit 160 will then change from a low voltage level to a high voltage level. Figure 3 Due to the operation of the AND gate AND4, at the end of the time period t6, the logic signal SG4 changes from a low voltage level to a high voltage level, thereby turning on the power semiconductor device NM4.

[0100] Figure 14 1 is a circuit diagram of a voltage converter 14 according to an embodiment of the present invention. Figure 1 The voltage converter 1 shown is similar, except that the voltage converter 14 is a boost converter.

[0101] See Figure 14When the PWM signal SPWM is at a low voltage level, the voltage converter 14 turns on its lower bridge portion (i.e., power semiconductor devices NM3 and NM4), and current from the system voltage VDD flows through the inductor L to store energy. When the PWM signal SPWM is at a high voltage level, the voltage converter 14 turns on its upper bridge portion (i.e., power semiconductor devices NM1 and NM2), and the current flowing through the inductor L charges the output capacitor Cout via the upper bridge portion, thereby causing the voltage converter 14 to output the voltage VOUT.

[0102] The signal timing diagram of the voltage converter 14 is also the same as Figure 2 As shown, the exemplary circuit diagram of the control logic circuit 220 of the voltage converter 14 is also as shown in FIG. Figure 3 As shown, the operation process will not be described here in detail.

[0103] According to the above embodiments, in the voltage converter control method of the present invention, the control logic circuit 220 receives the PWM signal SPWM and uses the PWM signal SPWM as a base signal to control the operation of the upper and lower bridge components of the voltage converter 1. The control method of this embodiment will be described below using the control of the upper bridge component as an example.

[0104] According to the control method of the present invention, the time delay circuit 140 performs a comparison operation to compare the voltage level of the control signal SG20 with the reference voltage Vgs2_adj and generates a corresponding comparison result. The time delay circuit 140 generates the voltage VG1 based on this comparison result. Furthermore, the time delay circuit 120 performs another comparison operation to compare the drain-source voltage VDS1 of the power semiconductor device NM1 with the reference voltage Vds1_adj and generates a corresponding comparison result. The time delay circuit 120 generates the voltage VG2 based on this comparison result. In an embodiment of the present invention, both the reference voltages Vgs2_adj and Vds1_adj are related to the temperatures of the power semiconductor devices NM1 and NM2. The control logic circuit 220 generates the logic signal SG1 based on the voltage VG1 and the PWM signal SPWM, and generates the logic signal SG2 based on the voltage VG2 and the PWM signal SPWM. The logic signals SG1 and SG2 are buffered by two buffers to generate the control signals SG10 and SG20, respectively. Control signals SG10 and SG20 are respectively provided to the gates (control electrodes) of the power semiconductor elements NM1 and NM2 to control their on / off timings.

[0105] The above summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art will understand that they can easily use this invention as a basis to design or modify other processes and structures to achieve the same goals and / or obtain the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present invention.

[0106]

Explanation of symbols

[0107] 1,14: Voltage Converter

[0108] 100: driving circuit

[0109] 120,140,160,180: Time delay circuit

[0110] 122,162: Temperature sensor

[0111] 220: Control logic circuit

[0112] AND1, AND2, AND3, AND4: AND gate

[0113] BF: Buffer

[0114] CMP1, CMP2, CMP3, CMP4: Comparators

[0115] Cout: output capacitance

[0116] D1, D3: drain

[0117] DL1, DL2: Delay

[0118] G1, G2, G3, G4: Gate

[0119] GND: Ground

[0120] ITH1, ITH1_adj, ITH2, ITH2_adj, ITH3, ITH3_adj, ITH4, ITH4_adj: current source

[0121] L: Inductance

[0122] NM1, NM2, NM3, NM4: Power semiconductor components

[0123] OR1, OR2: OR gate

[0124] Rds1, Rds3, Rds1_adj, Rds3_adj, Rgs2, Rgs4, Rgs2_adj, Rgs4_adj: Resistance

[0125] S1, S3: Source

[0126] SG1, SG2, SG3, SG4: logic signals

[0127] SG10, SG20, SG30, SG40: control signal

[0128] SPWM: Pulse Width Modulation (PWM) signal

[0129] T1, T2, T3, T4: time points

[0130] t1, t2, t3, t4, t5, t6: time period

[0131] VDD: system voltage

[0132] VDS1, VDS3: drain-source voltage

[0133] Vds1_adj, Vds3_adj, Vgs2_adj, Vgs4_adj: reference voltage

[0134] VG1, VG2, VG3, VG4: voltage

[0135] VOUT: output voltage

[0136] Vtemp1, Vtemp2: sensing voltage.

Claims

1. A driving circuit, characterized in that: The drive circuit is configured to generate a first control signal and a second control signal and to provide the first and second control signals to a control electrode of a first power semiconductor element and a control electrode of a second power semiconductor element connected in parallel to each other in a voltage converter, wherein the safe operating area of the first power semiconductor element is greater than the safe operating area of the second power semiconductor element. The drive circuit comprises: a first time delay circuit that performs a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or compares the drain-source voltage of the first power semiconductor device with a second reference voltage and generate a corresponding second comparison result, and generates a first voltage according to the first comparison result or the second comparison result, wherein the first and second reference voltages are associated with temperatures of the first and second power semiconductor devices; and a control logic circuit coupled to the first time delay circuit and generating a first logic signal according to the first voltage; and The first buffer is coupled to the control logic circuit and generates one of the first and second control signals according to the first logic signal.

2. The driving circuit according to claim 1, wherein: The first reference voltage increases as the temperature of the first and second power semiconductor devices decreases, and the second reference voltage increases as the temperature of the first and second power semiconductor devices increases.

3. The driving circuit according to claim 1, wherein: The first time delay circuit performs the first comparison operation to generate the first comparison result and generates the first voltage according to the first comparison result, and the first buffer generates the first control signal according to the first logic signal; The driving circuit further includes: a second time delay circuit that performs a second comparison operation to compare the drain-source voltage with the second reference voltage and generates a second comparison result, and generates a second voltage according to the second comparison result, wherein the control logic circuit is coupled to the second time delay circuit and generates a second logic signal according to the second voltage; as well as The second buffer is coupled to the control logic circuit and generates the second control signal according to the second logic signal.

4. The driving circuit according to claim 3, wherein: The first time delay circuit includes a first current source, a first resistor and a first comparator. The first current source is coupled in series with the first resistor. The negative input of the first comparator is coupled to a node between the first current source and the first resistor to receive the first reference voltage. The positive input of the first comparator receives the second control signal. The first comparator generates the first voltage at its output according to the first comparison result.

5. The driving circuit according to claim 3, wherein: The second time delay circuit includes a second current source, a second resistor, and a second comparator. The second current source is coupled in series with the second resistor. A positive input of the second comparator is coupled to a node between the second current source and the second resistor to receive the second reference voltage. A negative input of the second comparator receives the drain-source voltage. The second comparator generates the second voltage at its output according to the second comparison result.

6. A voltage converter, characterized in that: include: A first power semiconductor element having a control electrode receiving a first control signal; a second power semiconductor element connected in parallel to the first power semiconductor element and having a control electrode for receiving a second control signal, wherein a safe operating area of the first power semiconductor element is greater than a safe operating area of the second power semiconductor element; a first time delay circuit that performs a first comparison operation to compare a voltage level of the second control signal with a first reference voltage and generates a corresponding first comparison result, or compares a first drain-source voltage of the first power semiconductor element with a second reference voltage and generates a corresponding second comparison result, and generates a first voltage according to the first comparison result or the second comparison result, wherein the first and second reference voltages are associated with first temperatures of the first and second power semiconductor elements; a control logic circuit coupled to the first time delay circuit and configured to generate a first logic signal according to the first voltage and a pulse width modulation signal; as well as The first buffer is coupled to the control logic circuit and generates one of the first and second control signals according to the first logic signal.

7. The voltage converter according to claim 6, wherein: The first time delay circuit performs the first comparison operation to generate the first comparison result and generates the first voltage according to the first comparison result, and the first buffer generates the first control signal according to the first logic signal; The voltage converter further includes: a second time delay circuit that performs a second comparison operation to compare the first drain-source voltage with the second reference voltage and generates a second comparison result, and generates a second voltage based on the second comparison result, wherein the control logic circuit is coupled to the second time delay circuit and generates a second logic signal based on the second voltage and the pulse width modulation signal; as well as The second buffer is coupled to the control logic circuit and generates the second control signal according to the second logic signal.

8. The voltage converter according to claim 7, wherein: The first time delay circuit includes a first comparator, a negative input terminal of the first comparator receiving the first reference voltage, a positive input terminal of the first comparator receiving the second control signal, the first comparator generating the first voltage at its output terminal according to the first comparison result, and the first reference voltage increasing as the first temperature of the first and second power semiconductor elements decreases.

9. The voltage converter according to claim 7, wherein: The second time delay circuit includes a second comparator, wherein a positive input terminal of the second comparator receives the second reference voltage, a negative input terminal of the second comparator receives the first drain-source voltage, and the second comparator generates the second voltage at its output terminal according to the second comparison result. The second reference voltage increases as the first temperature of the first and second power semiconductor elements increases.

10. The voltage converter according to claim 7, wherein: Also includes: a third power semiconductor element having a control electrode receiving a third control signal; a fourth power semiconductor element connected in parallel with the third power semiconductor element and having a control electrode for receiving a fourth control signal, wherein a safe operating area of the third power semiconductor element is greater than a safe operating area of the fourth power semiconductor element, the first and second power semiconductor elements constitute an upper bridge portion of the voltage converter, and the third and fourth power semiconductor elements constitute a lower bridge portion of the voltage converter; a third time delay circuit that performs a third comparison operation to compare the voltage level of the fourth control signal with a third reference voltage and generates a corresponding third comparison result, and generates a third voltage according to the third comparison result; a fourth time delay circuit that performs a fourth comparison operation to compare the second drain-source voltage of the third power semiconductor device with a fourth reference voltage and generates a corresponding fourth comparison result, and generates a fourth voltage based on the fourth comparison result, wherein the third and fourth reference voltages are associated with second temperatures of the third and fourth power semiconductor devices, and wherein the control logic circuit is coupled to the third and fourth time delay circuits and generates a third logic signal based on the third voltage and the pulse width modulation signal, and generates a fourth logic signal based on the fourth voltage and the pulse width modulation signal; a third buffer coupled to the control logic circuit and generating the third control signal according to the third logic signal; as well as The fourth buffer is coupled to the control logic circuit and generates the fourth control signal according to the fourth logic signal.

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