Multi-layer epitaxial super-junction MOSEFT device

Abstract

The utility model relates to a multi-layer epitaxial super junction MOSEFT device comprising a first conductive type substrate, a first conductive type epitaxial layer is arranged on the front surface of the first conductive type substrate, and the first conductive type epitaxial layer comprises a plurality of stacked sub epitaxial layers; the second conductive type body region is arranged on the front surface of the first conductive type epitaxial layer and is positioned in the first conductive type epitaxial layer; the number of the second conductive type columns is at least two, and the second conductive type columns extend into the second conductive type body region from the sub epitaxial layer close to the first conductive type substrate; the first conductive type source region is arranged on the front surface of the second conductive type body region and is located in the second conductive type body region; wherein the trench gate structure comprises a first trench arranged on the front surface of the first conductive type epitaxial layer, at least two gates are arranged in the first trench, and a shield gate is arranged between the two gates. The trench gate structure has the effects that the on-resistance is further reduced, the on-resistance of the whole structure is small, and the through-current capability is strong.

Description

Technical Field

[0001] The utility model relates to the technical field of microelectronics, in particular to a multi-layer epitaxial super-junction MOSFET device. Background Art

[0002] MOS is one of the basic components in integrated circuit technology. Its main advantages include high integrability, fast switching speed, low power consumption, good electrical isolation and stability, which make it widely used in various applications such as digital circuits, analog circuits, microprocessors, memories and power amplifiers. The key innovation of planar MOS lies in the application of metal, oxide and semiconductor structures to transistor design. By forming a layer of oxide (usually silicon dioxide) on the semiconductor surface and using metal as the gate above it, the gate voltage is used to control the resistance of the conductive channel on the semiconductor surface between the source and drain to control the conductivity of the channel, thereby realizing the switching and amplification functions of the device.

[0003] In modern electronic devices, especially in high-frequency and high-power applications, reducing on-resistance is one of the key factors in improving device performance and power efficiency. Trench gate structure is a commonly used technology. By etching trenches on the semiconductor substrate and forming a gate in the trench, the contact area is increased, and the gate's ability to control the channel current is improved. This not only enables the device to achieve a larger current at the same gate drive voltage, but also greatly reduces the on-resistance.

[0004] Although the traditional trench gate structure can reduce the on-resistance to a certain extent, with the continuous advancement of technology, the requirements for on-resistance are becoming increasingly higher. In application scenarios with higher performance requirements, such as high-frequency and high-power devices, the on-resistance of the traditional trench gate structure has not yet reached the ideal level, limiting the performance of the device under extreme conditions. Therefore, there is an urgent need to make further improvements based on the existing trench gate structure to further reduce the on-resistance. Utility Model Content

[0005] In view of this, the purpose of the present invention is to provide a multi-layer epitaxial super-junction MOSFET device to solve the technical problem in the prior art that the conductive resistance of the traditional trench gate structure has not reached an ideal level.

[0006] The utility model provides a multi-layer epitaxial superjunction MOSFET device, comprising:

[0007] a first conductive type substrate;

[0008] A first conductive type epitaxial layer is provided on the front surface of the first conductive type substrate, wherein the first conductive type epitaxial layer includes a plurality of stacked sub-epitaxial layers;

[0009] A second conductive type body region is provided on the front surface of the first conductive type epitaxial layer and is located within the first conductive type epitaxial layer;

[0010] At least two second conductive type columns are provided, and the second conductive type columns extend from the sub-epitaxial layer close to the first conductive type substrate to the second conductive type body region;

[0011] a trench gate structure, disposed between two adjacent second conductivity type pillars and extending from a front surface to a back surface of the first conductivity type epitaxial layer having a second conductivity type body region;

[0012] A first conductive type source region is disposed on the front side of the second conductive type body region and is located within the second conductive type body region;

[0013] In which, the trench gate structure includes a first trench opened on the front side of the first conductive type epitaxial layer, at least two gates are arranged in the first trench, a shielding gate is arranged between the two gates, and a gate oxide layer is arranged between the shielding gate and the gate, between the gate and the inner wall of the first trench, and between the shielding gate and the bottom wall of the first trench.

[0014] Optionally, multiple sub-epitaxial layers are stacked in sequence of n layers from the front side of the first conductive type substrate toward the second conductive type body region, wherein the thickness of the nth sub-epitaxial layer is not greater than the thickness of the n-1th sub-epitaxial layer, and the thickness of the nth sub-epitaxial layer is less than the thickness of the 1st sub-epitaxial layer.

[0015] Optionally, the sub-epitaxial layer is provided with 7-13 layers.

[0016] Optionally, a first conductive type buffer layer is provided between the first conductive type epitaxial layer and the first conductive type substrate.

[0017] Optionally, the first conductivity type ion concentration in the first conductivity type buffer layer is between the first conductivity type ion concentration in the first conductivity type substrate and the first conductivity type epitaxial layer.

[0018] Optionally, the first conductivity type ion concentration in the first conductivity type substrate is greater than the first conductivity type ion concentration in the first conductivity type epitaxial layer.

[0019] Optionally, an insulating dielectric layer is provided on the front side of the second conductive type body region, and a plurality of metal contact holes are opened in the insulating dielectric layer. A part of the metal contact holes are provided corresponding to the second conductive type columns and penetrate into the second conductive type body region to be connected with the second conductive type body region and the first conductive type source region, and another part of the metal contact holes are provided corresponding to the shielding gate and are connected with the shielding gate.

[0020] Optionally, it also includes:

[0021] a front metal layer, disposed on the front surface of the insulating dielectric layer, wherein a portion of the front metal layer located at the metal contact through-hole extends into the metal contact through-hole until the metal contact through-hole is completely filled;

[0022] The back metal layer is arranged on the back side of the first conductive type substrate.

[0023] Optionally, the depth of the first groove is set to 1.5 μm-3 μm.

[0024] Optionally, a depth of the shielding gate in the first trench is greater than a depth of the gate in the first trench.

[0025] The technical solution of the utility model has the following advantages:

[0026] The utility model provides a multi-layer epitaxial super-junction MOSFET device. A first conductive type epitaxial layer is provided, and the first conductive epitaxial layer includes a multi-layer stacked sub-epitaxial layer. Second conductive type columns are provided in the multi-layer sub-epitaxial layer. Based on the charge balance technology, under the same withstand voltage, the thickness of the first conductive type epitaxial layer is reduced, thereby reducing the on-resistance, and the ion concentration and thickness of the multiple sub-epitaxial layers can be accurately controlled; by adopting a shielding grid, the first conductive type epitaxial layer can be assisted to be depleted, thereby reducing the on-resistance and reducing the conduction loss. On this basis, the trench gate structure provided between two adjacent second conductive type columns includes two or more gates, which can increase the conductive current path when the super-junction MOSFET is turned on, further reducing the on-resistance, so that the on-resistance of the entire structure is small and the current flow capacity is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1It is a cross-sectional view of forming a sub-epitaxial layer in the present invention;

[0029] Figure 2 A cross-sectional view of a first conductive type column region formed in the present invention;

[0030] Figure 3 A cross-sectional view of forming a multi-layer sub-epitaxial layer in the present invention;

[0031] Figure 4 It is a cross-sectional view of forming a first conductive type column in the present invention;

[0032] Figure 5 A cross-sectional view showing the formation of a second conductive type body region in the present invention;

[0033] Figure 6 It is a cross-sectional view of forming the first groove in the present invention;

[0034] Figure 7 A cross-sectional view of a trench gate structure formed in the present invention;

[0035] Figure 8 A cross-sectional view of a first conductive type source region formed in the present invention;

[0036] Figure 9 It is a cross-sectional view of forming an insulating dielectric layer in the present invention;

[0037] Figure 10 It is a cross-sectional view of forming the front metal layer and the back metal layer in the present invention;

[0038] Figure 11 It is a cross-sectional view of the buffer layer with the first conductive type in the present invention.

[0039] Description of reference numerals:

[0040] 1. First conductive type substrate; 2. First conductive type epitaxial layer; 21. Sub-epitaxial layer; 3. Second conductive type body region; 4. First conductive type source region; 5. Second conductive type column; 51. Second conductive type column region; 6. Trench gate structure; 61. Gate; 62. Shielding gate; 63. First trench; 64. Gate oxide layer; 7. First conductive type buffer layer; 8. Insulating dielectric layer; 9. Metal contact via; 10. Front metal layer; 11. Back metal layer. DETAILED DESCRIPTION

[0041] Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, and not all of them. Based on the description of the present invention, all other embodiments derived by persons of ordinary skill in the art without inventive effort are also within the scope of protection of the present invention.

[0042] Unless otherwise specified or limited, the terms "disposed," "installed," and "connected" should be interpreted broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; and direct or indirect connections through an intermediary. Those skilled in the art will understand the specific meanings of these terms based on the specific circumstances.

[0043] The directions or positional relationships indicated by terms such as "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inside" and "outside" are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the utility model product is usually placed when in use. They are only for the convenience and simplification of description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on the utility model.

[0044] The terms "first," "second," "third," etc. are merely used to distinguish elements of similar nature and do not indicate or imply relative importance or a particular order.

[0045] The terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than the listed elements and may also include additional elements not specifically listed.

[0046] Example

[0047] For an N-type multi-layer epitaxial super-junction MOSFET device, the first conductivity type is N-type and the second conductivity type is P-type; for a P-type multi-layer epitaxial super-junction MOSFET device, the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, an N-type multi-layer epitaxial super-junction MOSFET device is taken as an example.

[0048] Reference Figure 1-11As shown, the utility model provides a multi-layer epitaxial superjunction MOSFET device, including a first conductive type substrate 1, a first conductive type epitaxial layer 2, a second conductive type body region 3, a second conductive type column 5, a trench gate structure 6 and a first conductive type source region 4. In this embodiment, the top surface is set as the front surface and the bottom surface is set as the back surface, wherein the first conductive type substrate 1 selects N-type silicon as the substrate, the first conductive type epitaxial layer 2 is arranged on the front surface of the first conductive type substrate 1, and the first conductive type epitaxial layer 2 includes a plurality of sub-epitaxial layers 21 stacked layer by layer, and the sub-epitaxial layers 21 are grown layer by layer through an epitaxial process; the second conductive type body region 3 is arranged on the front surface of the first conductive type epitaxial layer 2 and is located in the first conductive type epitaxial layer 2, specifically in the topmost sub-epitaxial layer 21; the second conductive type column At least two second conductive type pillars 5 are provided, extending from the sub-epitaxial layer 21 close to the first conductive type substrate 1 toward the second conductive type body region 3 until extending into the second conductive type body region 3. Specifically, after the sub-epitaxial layer 21 is epitaxially grown, second conductive type ions are implanted into a portion of the sub-epitaxial layer 21 to form second conductive type pillar regions 51. Several sub-epitaxial layers 21 are epitaxially grown continuously, and second conductive type ions are implanted into the same portion of each sub-epitaxial layer 21 to form second conductive type pillar regions 51. The second conductive type pillar regions 51 are arranged in a vertical direction to form multiple rows. After completion, another sub-epitaxial layer 21 is epitaxially grown and high-temperature advancement is performed. At this time, the second conductive type pillar regions 51 in the same row are diffused and connected, thereby forming second conductive type pillars 5.

[0049] At least one trench gate structure 6 is provided, and a trench gate structure 6 is provided between two adjacent second conductive type pillars 5. The trench gate structure 6 extends from the front side of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back side, until it extends from the second conductive type body region 3 to the sub-epitaxial layer 21 on the back side of the first conductive type body region; the first conductive type source region 4 is provided on the front side of the second conductive type body region 3 and is located within the second conductive type body region 3. In this embodiment, a plurality of first conductive type source regions 4 are provided, and two first conductive type source regions 4 are correspondingly provided at each trench gate structure 6, which are respectively located on both sides of the trench gate structure 6 in the direction toward the second conductive type pillar 5 and extend toward the second conductive type pillar 5;

[0050] The trench gate structure 6 includes a first trench 63 formed on the front surface of the first conductive type epitaxial layer 2. The first trench 63 extends from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back surface of the first conductive type epitaxial layer 2, until it extends from the second conductive type body region 3 to the sub-epitaxial layer 21 on the back surface of the first conductive type body region. Two gates 61 are provided in the first trench 63, and a shielding gate 62 is provided between the two gates 61. Both the gate 61 and the shielding gate 62 extend from the notch of the first trench 63 to the interior of the first trench 63. Gaps are left between the gate 61 and the inner wall of the first trench 63 and the shielding gate 62. A gate oxide layer 64 is provided between the shielding gate 62 and the gate 61, between the gate 61 and the inner wall of the first trench 63, and between the shielding gate 62 and the bottom wall of the first trench 63, and the gate oxide layer 64 is used to separate the gates. In other embodiments, the number of gates 61 is not limited to a single number and can also be set to multiple.

[0051] By setting a first conductive type epitaxial layer 2, and the first conductive epitaxial layer includes a multi-layer stacked sub-epitaxial layer 21, and a second conductive type column 5 is arranged in the multi-layer sub-epitaxial layer 21, based on the charge balance technology, under the same withstand voltage, the thickness of the first conductive type epitaxial layer 2 is reduced, thereby reducing the on-resistance, and the ion concentration and thickness of multiple sub-epitaxial layers 21 can be accurately controlled; by adopting a shielding grid 62, the first conductive type epitaxial layer 2 can be assisted to be depleted, thereby reducing the on-resistance and reducing the conduction loss. On this basis, the trench gate structure 6 arranged between two adjacent second conductive type columns 5 includes two or more gates 61, which can increase the conductive current path when the super junction MOSFET device is turned on, further reducing the on-resistance, so that the on-resistance of the entire structure is small and the current flow capacity is strong.

[0052] As a specific embodiment, multiple second conductive type columns 5 are arranged in parallel, and a trench gate structure 6 is provided between each adjacent second conductive type column 5, and the trench gate structure 6 is separated by a portion of the first conductive type epitaxial layer 2. The depth of the second conductive type column 5 is set to 30μm-60μm, the depth of the first trench 63 is set to 1.5μm-3μm, and the depth of the shielding gate 62 in the first trench 63 is greater than the depth of the gate 61 in the first trench 63.

[0053] As a specific embodiment, the sub-epitaxial layer 21 is stacked in sequence from the front side of the first conductive type substrate 1 to the second conductive type body region 3, that is, from bottom to top, with n layers, wherein the thickness of the nth sub-epitaxial layer 21 is not greater than the thickness of the n-1th sub-epitaxial layer 21, and the thickness of the nth sub-epitaxial layer 21 is less than the thickness of the 1st sub-epitaxial layer 21; in this embodiment, the sub-epitaxial layer 21 is provided with 7-13 layers, and further in this embodiment, the sub-epitaxial layer 21 is provided with 8 layers. By gradually reducing the thickness of multiple sub-epitaxial layers 21 from bottom to top, the electric field is evenly distributed, so that the electric field is more evenly distributed in the entire first conductive type epitaxial layer 2, thereby improving the voltage resistance of the device, effectively controlling the electric field gradient of each sub-epitaxial layer 21, and making the electric field gradually change between different layers, thereby avoiding the electric field mutation that may occur in the single-layer sub-epitaxial layer 21, refining the flow capacity, and achieving charge balance.

[0054] As a specific embodiment, the first conductive type ion concentration in the first conductive type substrate 1 is greater than the first conductive type ion concentration in the first conductive type epitaxial layer 2. At the same time, a first conductive type buffer layer 7 is provided between the first conductive type substrate 1 and the first conductive type epitaxial layer 2. The first conductive type ion concentration in the first conductive type buffer layer 7 is between the first conductive type ion concentration in the first conductive type substrate 1 and the first conductive type epitaxial layer 2, and is used to prevent the ions of the first conductive type substrate 1 from diffusing into the first conductive type epitaxial layer 2, thereby increasing the on-resistance of the super junction MOSFET device. When the first conductive type buffer layer 7 is formed, the second conductive type column 5 can extend all the way to the back side of the first conductive type epitaxial layer 2 until it contacts the first conductive type buffer layer 7 or penetrates into the first conductive type buffer layer 7.

[0055] As a specific embodiment, it also includes an insulating dielectric layer 8, a front metal layer 10 and a back metal layer 11, wherein the insulating dielectric layer 8 is arranged on the front of the second conductive type body region 3 and covers the entire second conductive type body region 3, and a plurality of metal contact holes 9 are opened in the insulating dielectric layer 8, a part of the metal contact holes 9 is arranged corresponding to the second conductive type column 5 and penetrates into the second conductive type body region 3 and is connected to the first conductive type source region 4, and another part of the metal contact holes 9 is arranged corresponding to the shielding grid 62 and is connected to the shielding grid 62; the front metal layer 10 is arranged on the front of the second conductive type body region 3 and covers the entire second conductive type body region 3. The front side of the insulating dielectric layer 8, and the front metal layer 10 is located at the metal contact through-hole 9 and partially extends into the metal contact through-hole 9 until the metal contact through-hole 9 is filled. At this time, the part of the front metal layer 10 in the metal contact through-hole 9 corresponding to the second conductive type column 5 will contact the second conductive type body region 3 and the first conductive type source region 4, and the part of the front metal layer 10 in the metal contact through-hole 9 corresponding to the shielding gate 62 will contact the shielding gate 62; the back metal layer 11 is arranged on the back side of the first conductive type substrate 1 and covers the entire back side of the first conductive type substrate 1.

[0056] The method for preparing the superjunction MOSFET device includes the following steps:

[0057] like Figure 1 As shown, S1, a first conductive type substrate 1 is selected, and a first sub-epitaxial layer 21 is grown on the front surface of the first conductive type substrate 1, wherein the first conductive type substrate 1 selects N-type silicon as the substrate, and the sub-epitaxial layer 21 is grown using an epitaxial process.

[0058] like Figure 2 As shown, in step S2 , second conductive type ions are implanted into a portion of the sub-epitaxial layer 21 through photolithography masking to form a second conductive type column region 51 .

[0059] like Figure 3 As shown, S3, multiple sub-epitaxial layers 21 are continuously epitaxially grown and second conductive type ions are implanted into partial regions of the multiple sub-epitaxial layers 21 to form multiple rows of second conductive type column regions 51. After completion, another sub-epitaxial layer 21 is epitaxially grown to form a first conductive type epitaxial layer 2;

[0060] like Figure 4 As shown, S4, high temperature advancement, the second conductive type column regions 51 are diffused, so that the second conductive type column regions 51 of each row are diffused and connected to form second conductive type columns 5;

[0061] like Figure 5As shown, S5, a general injection is performed directly on the front surface of the first conductive type epitaxial layer 2, the second conductive type ions are injected, and the injection is carried out at high temperature, thereby forming a second conductive type body region 3 on the front surface of the first conductive type epitaxial layer 2, and the second conductive type body region 3 covers the entire front surface of the first conductive type epitaxial layer 2.

[0062] As shown in Figure 6, S6, through photolithography blocking, a plurality of first trenches 63 are etched in a partial area of the front surface of the first conductive type epitaxial layer 2, and a first trench 63 is set between two adjacent second conductive type columns 5. The first trench 63 extends from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back surface of the first conductive type epitaxial layer 2 until it extends from the second conductive type body region 3 to the sub-epitaxial layer 2 below. The depth of the first trench 63 is set to 1.5μm-3μm.

[0063] like Figure 7 As shown, S7, a gate oxide layer 64 is deposited in the first groove 63, and selective etching is performed to etch three side-by-side grooves on the front of the first groove 63, wherein the depth of the middle groove is greater than the depth of the two grooves on both sides, conductive polysilicon is deposited in the grooves on both sides to form a gate 61, and conductive polysilicon is deposited in the middle groove to form a shielding gate 62. Compared with the commonly used thermal growth to form the gate oxide layer 64, the gate oxide layer 64 is prepared by deposition in this embodiment, so that the thickness of the gate oxide layer 64 can be more accurately controlled without being limited by the growth rate and event. At the same time, the deposition technology can be carried out on different substrates and manufacturing conditions, so that it can be suitable for large-scale production, and can be prepared more quickly, thereby improving production efficiency.

[0064] like Figure 8 As shown, S8, through photolithography blocking, first conductive type ions are injected into a partial area on the front side of the second conductive type body region 3, and high temperature is promoted, so as to form a first conductive type source region 4 in the second conductive type body region 3. Specifically, through the blocking of the photolithography plate, two unblocked areas are formed on both sides of the second conductive type body region 3 in the direction of the trench gate structure 6 toward the second conductive type column 5, and the first conductive type ions are injected into the unblocked areas. At this time, two undiffused first conductive type source regions 4 are formed in the second conductive type body region 3, and then high temperature promotion is performed to diffuse to form the first conductive type source region 4. The first conductive type source region 4 is provided on both sides of the plurality of trench gate structures 6, and the first conductive type source region 4 is in contact with the trench gate structure 6.

[0065] like Figure 9As shown, S9, an insulating dielectric layer 8 is deposited on the surface of one side of the first conductive type epitaxial layer 2 having the second conductive type body region 3, so that the insulating dielectric layer 8 covers the entire front surface of the first conductive type epitaxial layer 2, and then the insulating dielectric layer 8 is etched to etch a plurality of through holes on the insulating dielectric layer 8 to form metal contact through holes 9, wherein a portion of the metal contact through holes 9 is located directly above the second conductive type column 5, and during etching, an additional 0.3 mm to 0.4 mm is etched into the second conductive type body region 3 to ensure that the insulating dielectric layer 8 can be completely removed, so that the metal contact points are exposed, thereby ensuring the stability and reliability of the electrical connection, and another portion of the metal contact through holes 9 is located directly above the shielding grid 62.

[0066] like Figure 10 As shown, S10, metal is deposited on the front surface of the insulating dielectric layer 8 and filled with the metal contact through-holes 9 to form a front metal layer 10, and metal is deposited on the back surface of the first conductive type substrate 1 to form a back metal layer 11.

[0067] As another embodiment, Figure 11 As shown, after selecting the first conductive type substrate 1, before forming the first conductive type epitaxial layer 2, a first conductive type buffer layer 7 is grown on the first conductive type substrate 1. The first conductive type ion concentration in the first conductive type buffer layer 7 is between the first conductive type ion concentrations in the first conductive type substrate 1 and the first conductive type epitaxial layer 2, which is used to prevent the ions of the first conductive type substrate 1 from diffusing into the first conductive type epitaxial layer 2, resulting in an increase in the on-resistance of the super junction MOSFET device.

[0068] The above is only a specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the protection scope of the present invention.

Claims

1. A multi-layer epitaxial superjunction MOSFET device, characterized in that: include: a first conductive type substrate; A first conductive type epitaxial layer is provided on the front surface of the first conductive type substrate, wherein the first conductive type epitaxial layer includes a plurality of stacked sub-epitaxial layers; A second conductive type body region is provided on the front surface of the first conductive type epitaxial layer and is located within the first conductive type epitaxial layer; At least two second conductive type columns are provided, and the second conductive type columns extend from the sub-epitaxial layer close to the first conductive type substrate to the second conductive type body region; a trench gate structure, disposed between two adjacent second conductivity type pillars and extending from a front surface to a back surface of the first conductivity type epitaxial layer having a second conductivity type body region; A first conductive type source region is disposed on the front side of the second conductive type body region and is located within the second conductive type body region; In which, the trench gate structure includes a first trench opened on the front side of the first conductive type epitaxial layer, at least two gates are arranged in the first trench, a shielding gate is arranged between the two gates, and a gate oxide layer is arranged between the shielding gate and the gate, between the gate and the inner wall of the first trench, and between the shielding gate and the bottom wall of the first trench.

2. The multi-layer epitaxial superjunction MOSFET device according to claim 1, characterized in that: Multiple sub-epitaxial layers are stacked in sequence from the front side of the first conductive type substrate toward the second conductive type body region, wherein the thickness of the nth sub-epitaxial layer is not greater than the thickness of the n-1th sub-epitaxial layer, and the thickness of the nth sub-epitaxial layer is less than the thickness of the 1st sub-epitaxial layer.

3. The multi-layer epitaxial superjunction MOSFET device according to claim 1, characterized in that: The sub-epitaxial layer is provided with 7-13 layers.

4. The multi-layer epitaxial superjunction MOSFET device according to claim 1, characterized in that: A first conductive type buffer layer is provided between the first conductive type epitaxial layer and the first conductive type substrate.

5. The multi-layer epitaxial superjunction MOSFET device according to claim 4, characterized in that: The first conductivity type ion concentration in the first conductivity type buffer layer is between the first conductivity type ion concentration in the first conductivity type substrate and the first conductivity type epitaxial layer. 6 . The multi-layer epitaxial superjunction MOSFET device according to claim 1 , wherein the first conductivity type ion concentration in the first conductivity type substrate is greater than the first conductivity type ion concentration in the first conductivity type epitaxial layer.

7. The multi-layer epitaxial superjunction MOSFET device according to claim 1, characterized in that: An insulating dielectric layer is provided on the front side of the second conductive type body region, and a plurality of metal contact holes are opened in the insulating dielectric layer. A part of the metal contact holes are provided corresponding to the second conductive type columns and penetrate into the second conductive type body region and are connected with the second conductive type body region and the first conductive type source region. Another part of the metal contact holes are provided corresponding to the shielding gate and are connected with the shielding gate.

8. The multi-layer epitaxial superjunction MOSFET device according to claim 7, characterized in that: Also includes: a front metal layer, disposed on the front surface of the insulating dielectric layer, wherein a portion of the front metal layer located at the metal contact through-hole extends into the metal contact through-hole until the metal contact through-hole is completely filled; The back metal layer is arranged on the back side of the first conductive type substrate.

9. The multi-layer epitaxial superjunction MOSFET device according to claim 1, characterized in that: The depth of the first groove is set to 1.5 μm-3 μm.

10. The multi-layer epitaxial superjunction MOSFET device according to claim 1, characterized in that: The depth of the shield gate in the first trench is greater than the depth of the gate in the first trench.

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