Semiconductor device structure

Abstract

The embodiment of the utility model provides a semiconductor device structure. The semiconductor device structure comprises a first fin structure, a second fin structure and a dielectric wall located on a substrate. The dielectric wall includes a first dielectric layer and a second dielectric layer between the first fin structure and the second fin structure. A second dielectric layer is surrounded by the first dielectric layer and has a 'V'-shaped cross-sectional profile.

Description

Technical Field

[0001] The present invention relates to a semiconductor technology, and more particularly to a semiconductor device structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or circuit) that can be formed using a manufacturing process) has decreased. This miniaturization process generally provides benefits by increasing production efficiency and reducing associated costs. However, this miniaturization also increases the complexity of IC processing and manufacturing.

[0003] Therefore, there is a need for improvements in the processing and fabrication of integrated circuits (ICs). Utility Model Content

[0004] In some embodiments, a semiconductor device structure is provided, comprising: a first fin structure, a second fin structure, and a dielectric wall disposed on a substrate. The dielectric wall comprises: a first dielectric layer and a second dielectric layer disposed between the first and second fin structures. The second dielectric layer is surrounded by the first dielectric layer and has a V-shaped cross-sectional profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1-11 Schematic cross-sectional views illustrating various stages of fabricating a semiconductor device structure according to some embodiments are shown.

[0006] Figure 12-15 Schematic cross-sectional views of various stages of fabricating a semiconductor device structure according to some other embodiments are shown.

[0007] Figure 16 A top view of one of the various stages in fabricating a semiconductor device structure according to some embodiments.

[0008] Figures 17A-19A According to some other embodiments, Figure 16 Schematic cross-sectional view of various stages of manufacturing a semiconductor device structure taken along line AA.

[0009] Figures 17B-19B According to some other embodiments, Figure 16 Schematic cross-sectional view of various stages of manufacturing a semiconductor device structure taken along line BB.

[0010] Figures 17C-19CAccording to some other embodiments, Figure 16 Schematic cross-sectional view of various stages of manufacturing a semiconductor device structure taken along line CC.

[0011] The following are the descriptions of the reference numerals:

[0012] 50,101: base

[0013] 50N: n-type region

[0014] 50P: p-type region

[0015] 52: Multi-layer stacking

[0016] 52A: first semiconductor layer

[0017] 52B: Second semiconductor layer

[0018] 54: semiconductor fin

[0019] 56: Nanostructure

[0020] 56A: First Nanostructure

[0021] 56B: Second nanostructure

[0022] 58: Mask

[0023] 58A: first mask layer

[0024] 58B: second mask layer

[0025] 60A, 60B: Groove

[0026] 61: Gap

[0027] 62, 62N, 62P: Fin structure

[0028] 64: Lining

[0029] 66,67: Dielectric layer

[0030] 68: Dielectric wall

[0031] 72: Insulation material

[0032] 74: Shallow Trench Isolation (STI) area

[0033] 76: Sacrificial gate structure

[0034] 78: Sacrificial gate electrode layer

[0035] 80: Fork structure

[0036] 81: Gate spacer

[0037] 82N, 82P: Source / drain (S / D) regions

[0038] 84: Etch stop layer (CESL)

[0039] 86: Interlayer dielectric (ILD) layer

[0040] 90N, 90P: Gate electrode layer

[0041] 100:Semiconductor device structure

[0042] H1: First Height

[0043] H2: Second height

[0044] W1: first width

[0045] W2: Second width DETAILED DESCRIPTION

[0046] The following disclosure provides many different embodiments or examples to implement the different characteristic components of the present invention. The following disclosure describes specific examples of each component and its arrangement in order to simplify the embodiments of the present invention. Of course, these are only examples and are not used to define the present invention. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which additional characteristic components can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the embodiments of the present invention will repeat numbers and / or text in each different example. Repetition is for the purpose of simplicity and clarity, rather than to list and specify the relationship between the various embodiments and / or configurations being discussed.

[0047] Spatially relative terms such as "below," "beneath," "below," "above," "upper," "top," and the like are used herein to facilitate the relationship of elements or features to one another in the drawings of this specification. These spatially relative terms encompass not only the orientations depicted in the drawings, but also various orientations of the device during use or operation. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative symbols used herein should be interpreted accordingly.

[0048] Figure 1-11 1 is a cross-sectional view illustrating various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1As shown, semiconductor device structure 100 includes a substrate 50 and a multilayer stack 52 formed over substrate 50. Substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and may be doped (e.g., with a p-type or n-type dopant) or undoped. Substrate 50 may be a semiconductor wafer, such as a silicon wafer. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); an alloy semiconductor (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide); or combinations thereof.

[0049] The substrate 50 includes an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, such as an n-type field effect transistor (NFET), while the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, such as a p-type field effect transistor (PFET). As described in more detail below, although one n-type region 50N and one p-type region 50P are shown, the substrate 50 may include any desired number of these regions.

[0050] like Figure 1 As shown, the multilayer stack 52 includes alternating first semiconductor layers 52A and second semiconductor layers 52B. The first semiconductor layers 52A are formed of a first semiconductor material, while the second semiconductor layers 52B are formed of a second semiconductor material different from the first semiconductor material. Both semiconductor materials can be selected from the alternative semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes four layers each of the first semiconductor layers 52A and the second semiconductor layers 52B. It should be understood that the multilayer stack 52 can include any number of first semiconductor layers 52A and second semiconductor layers 52B. For example, the multilayer stack 52 can include approximately three to eight layers each of the first semiconductor layers 52A and the second semiconductor layers 52B.

[0051] In the illustrated embodiment, the second semiconductor layer 52B is used to form the channel region of the transistor within the n-type region 50N and the p-type region 50P. In some embodiments, the transistor is a field effect transistor (FET), such as a nanostructure transistor field effect transistor (FET), each having multiple channels surrounded by a gate electrode layer. The term "nanostructure" is used herein to refer to any material portion having nanometer-scale, or even micrometer-scale, dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions having circular and substantially circular cross-sections, as well as cylindrical or rod-shaped material portions including, for example, cylindrical or rectangular cross-sections. The channel of the semiconductor device structure 100 can be surrounded by a gate layer. The nanostructure transistor can be referred to as a nanosheet transistor, a nanowire transistor, a gate-all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate layer surrounding the channel. In some embodiments, the transistor may be a planar field effect transistor (FET), a fin field effect transistor (FinFET), a complementary FET (CFET), a forksheet FET, or other suitable devices.

[0052] First semiconductor layer 52A is a sacrificial layer (or dummy layer) that will be removed in subsequent processes to expose the upper and lower surfaces of second semiconductor layer 52B in two regions. In some embodiments, the second semiconductor material of second semiconductor layer 52B is a material suitable for both n-type and p-type nanometer field-effect transistors (FETs), such as silicon, while the first semiconductor material of first semiconductor layer 52A is a material having high etch selectivity to the second semiconductor material, such as silicon germanium.

[0053] Each layer of the multilayer stack 52 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE) or deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) or the like. Each layer can be formed to have a relatively small thickness, for example, a thickness in the range of about 5 nm to 30 nm. In some embodiments, one set of film layers (e.g., the second semiconductor layer 52B) is formed to be thinner than another set of film layers (e.g., the first semiconductor layer 52A). For example, in some embodiments, the first semiconductor layer 52A is a sacrificial layer (or dummy layer) and the second semiconductor layer 52B is used to form a channel region, and the second semiconductor layer 52B can be thicker than the first semiconductor layer 52A. The relative thickness of the film layers can depend on the desired channel height and the channel work function requirements of the resulting nanostructured field effect transistor (FET).

[0054] like Figure 2 As shown, trenches 60A and 60B (collectively, 60 ) are etched into substrate 50 and multilayer stack 52 to form fin structures 62 (including fin structure 62N located in n-type region 50N and fin structure 62P located in p-type region 50 ). Each fin structure 62 includes a semiconductor fin 54 and a nanostructure 56 . Semiconductor fin 54 is a patterned semiconductor strip within substrate 50 . Nanostructure 56 comprises the remaining portion of multilayer stack 52 above semiconductor fin 54 . Specifically, nanostructure 56 includes alternating first nanostructures 56A and second nanostructures 56B. First nanostructures 56A and second nanostructures 56B are formed from the remaining portions of first semiconductor layer 52A and second semiconductor layer 52B, respectively. In the illustrated embodiment, each second nanostructure 56B is disposed between two first nanostructures 56A. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or a combination thereof, and may be performed using a mask 58 having a pattern of fin structure 62. The etching may be anisotropic.

[0055] Mask 58 can be a single-layer mask or can be a multi-layer mask, for example, each of which includes a first mask layer 58A and a second mask layer 58B located on first mask layer 58A. First mask layer 58A and second mask layer 58B can both be formed of a dielectric material, such as silicon oxide, silicon nitride, combinations thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. The material of first mask layer 58A can have a high etch selectivity relative to the material of second mask layer 58B. For example, first mask layer 58A can be formed of silicon oxide, while second mask layer 58B can be formed of silicon nitride.

[0056] The fin structure 62 can be patterned using any suitable method. For example, the fin structure 62 can be patterned using one or more photolithography processes (including double patterning or multiple patterning processes). Generally speaking, double patterning or multiple patterning processes combine photolithography processes with self-alignment processes, thereby allowing the formation of patterns having a pitch smaller than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure 62. In some embodiments, the mask 58 (or other film layer) can remain on the fin structure 62.

[0057] The fin structure 62 may have a width in the range of approximately 5 nm to 20 nm. For illustrative purposes, the fin structures 62 in the n-type region 50N and the p-type region 50P are depicted as having substantially equal widths. In some embodiments, the fin structure 62 in one region (e.g., the n-type region 50N) may be wider or narrower than the fin structure 62 in the other region (e.g., the p-type region 50P).

[0058] In some embodiments, the fin structures 62 are formed into adjacent pairs. Each pair of fin structures 62 will be used to form a fork-type field-effect transistor (FET). One fin structure 62N in each pair is used to form an n-type device, while the other fin structure 62P in each pair is used to form a p-type device. Each pair of fin structures 62N and 62P is separated by a corresponding trench 60A. A dielectric wall (described in more detail below) will be formed in the trench 60A between each pair of fin structures 62N and 62P to provide electrical isolation between the different types of field-effect transistors (FETs) to be formed in the fin structures 62N and 62P. The trench 60A can have a first width W1 in the range of approximately 6nm to 30nm. Adjacent pairs of fin structures 62 are separated by corresponding trenches 60B. The trench 60B can have a second width W2 in the range of approximately 22nm to 46nm. The second width W2 is greater than the first width W1, so that adjacent pairs of fin structures 62 are separated further apart than the fin structures 62N, 62P of each pair. In some embodiments, each of the trenches 60A, 60B has a varying width. For example, the width at the bottom of the trenches 60A, 60B is substantially smaller than the width at the top of the trenches 60A, 60B.

[0059] like Figure 3 As shown, liner 64 is formed over mask 58 (if present), fin structure 62, and substrate 50. In some embodiments, liner 64 may be formed of a dielectric material, which may be formed by thermal oxidation or a conformal deposition process. Acceptable dielectric materials include low-k value (e.g., k value less than about 7) dielectric materials (e.g., silicon oxide, silicon nitride, silicon carbon nitride, silicon oxycarbide, silicon oxycarbon nitride, or the like); high-k value (e.g., k value greater than about 7) dielectric materials (e.g., hafnium oxide, zirconium oxide, zirconium aluminum oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, or the like); combinations thereof, or the like. In some embodiments, liner 64 may be formed of a semiconductor material (e.g., silicon). The silicon may be amorphous silicon and an annealing process may be performed after deposition of liner 64. Acceptable deposition processes include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular-beam deposition (MBD), physical vapor deposition (PVD), or similar deposition processes. In some embodiments, the liner layer 64 may be formed to a thickness approximately in the range of 1 nm to 10 nm.

[0060] A dielectric layer 66 is then formed on the liner 64. The dielectric layer 66 may be formed of a low-k dielectric material (e.g., one of the alternative dielectric materials selected from the liner 64), which may be deposited by a compliant deposition process (e.g., one of the alternative methods selected from the liner 64). In some embodiments, the dielectric layer 66 comprises SiN, SiC, SiCN, AlOx, or SiOCN and has a k value in the range of approximately 6.5 to 7.5. In some embodiments, the dielectric layer 66 comprises SiCN and is formed by atomic layer deposition (ALD). The atomic layer deposition (ALD) process may be plasma enhanced atomic layer deposition (PEALD) or thermal atomic layer deposition (thermal ALD). The plasma enhanced atomic layer deposition (PEALD) process may have a plasma power in the range of approximately 200 W to 500 W. The thermal atomic layer deposition (thermal ALD) process may have a process temperature in the range of approximately 600 degrees Celsius to 700 degrees Celsius. The process pressure of the atomic layer deposition (ALD) process may be approximately in the range of 100 Torr to 1200 Torr. In some embodiments, the Young's modulus of the dielectric layer 66 is approximately in the range of 55 GPa to 65 GPa. In some embodiments, the dielectric layer 66 has a thickness in the range of approximately 7 nm to 9 nm.

[0061] Because trenches 60A and 60B have different widths, they are filled with different amounts of dielectric material. Liner 64 is formed along the sidewalls and bottom of trenches 60A and 60B. Because trench 60A has a narrower width, it is completely filled (or overfilled) with dielectric layer 66 except for gap 61. However, because trench 60B has a larger width, it is not completely filled with dielectric layer 66. In other words, after dielectric layer 66 is deposited, trench 60A is completely filled (or overfilled) except for gap 61, but some portions of trench 60B remain unfilled. In some embodiments, gap 61 is formed within dielectric layer 66 within trench 60A, such as Figure 3 Portions of dielectric layer 66 formed on fin structures 62N and 62P may merge to form gaps 61 before completely filling trenches 60A.

[0062] The gap 61 may result in a defective device. Therefore, an additional process is performed to remove / reduce the gap 61 formed in the dielectric layer 66. In some embodiments, a first etching process is performed to remove a portion of the dielectric layer 66 to expose the gap 61, such as Figure 4 As shown. The first etching process can be an anisotropic etching process, such as an anisotropic dry etching process. In some embodiments, the gap 61 extends to the height of the upper surface of the liner 64, such as Figure 4In some embodiments, the slit 61 extends to a height between the upper surface of the second mask layer 58B and the lower surface of the second mask layer 58B. In some embodiments, the first etching process can be controlled to remove just enough dielectric layer 66 to expose the slit 61.

[0063] Next, if Figure 5 As shown, a second etching process is performed to increase the width of the top of the gap 61. In some embodiments, the second etching process is an isotropic etching process, such as a wet etching process. In some embodiments, the second etching process expands the opening of the gap 61, and the resulting gap 61 can have a "V" shaped cross-sectional profile, such as Figure 5 The second etching process may also remove the portion of dielectric layer 66 located within trench 60B. In some embodiments, a single etching process is performed to expose and expand gap 61.

[0064] like Figure 6 As shown, dielectric layer 67 is deposited on semiconductor device structure 100. Dielectric layer 67 fills gap 61 having an enlarged opening. In some embodiments, dielectric layer 67 comprises the same material as dielectric layer 66. In some embodiments, dielectric layer 67 comprises a material different from that of dielectric layer 66. In some embodiments, dielectric layer 67 comprises SiCN and is formed by a compliant process, such as atomic layer deposition (ALD). Because gap 61 has a "V"-shaped profile, dielectric layer 67 can completely fill gap 61 without creating another gap within dielectric layer 67. In some embodiments, dielectric layer 67 has a thickness of approximately 3 nm to 4 nm.

[0065] like Figure 7As shown, the dielectric layers 66 and 67 are etched back. Specifically, the portions of the dielectric layers 66 and 67 within the trench 60B and above the mask 58 (if present) or the fin structure 62 are removed by etching back to reform the trench 60B. The dielectric layers 66 and 67 are etched back using an acceptable etching technique, such as an etching process that is selective to the dielectric layers 66 and 67 (for example, etching the material of the dielectric layers 66 and 67 at a faster rate than etching the material of the liner 64). After the etching back is completed, the remaining portions of the dielectric layers 66 and 67 are located within the trench 60A due to the small width of the trench 60A. The remaining portions of the dielectric layers 66 and 67 form dielectric walls 68 that separate the fin structures 62N and 62P of each pair of fin structures 62. The dielectric wall 68 may partially or completely fill the 60A trench. The dielectric wall 68 may have a width W3 of approximately 6 nm to 30 nm. In some embodiments, dielectric walls 68 can have varying widths. For example, the bottom of dielectric wall 68 can have a width approximately in the range of 15 nm to 20 nm, while the top of dielectric wall 68 can have a width approximately in the range of 20 nm to 26 nm. After dielectric walls 68 are formed, fork-piece structures 80 extend from substrate 50. Each fork-piece structure 80 includes a dielectric wall 68 and a pair of fin structures 62 (e.g., fin structures 62N and 62P), with dielectric wall 68 disposed between fin structures 62.

[0066] In some embodiments, dielectric layers 66, 67 include the same material, and a single etching process can be performed to etch back dielectric layers 66, 67. After the etching back process, the upper surface of dielectric wall 68 can be substantially flat, as shown in FIG. Figure 7 In some embodiments, dielectric layers 66 and 67 include different materials, and two selective etching processes can be performed to etch back dielectric layers 66 and 67. For example, the first etching process selectively etches back dielectric layer 67, while the second etching process selectively etches back dielectric layer 66. In this way, the upper surface of dielectric wall 68 can be curved, such as Figure 8 The curved upper surface may be concave or convex.

[0067] As described above, although one n-type region 50N and one p-type region 50P are depicted, substrate 50 may include any desired number of these regions. In some embodiments, each prong structure 80 is disposed at the boundary between n-type region 50N and p-type region 50P. Furthermore, the fin structures 62N and 62P of each prong structure 80 alternate. In other words, each n-type region 50N includes a first fin structure 62N from a first prong structure 80 and a second fin structure 62N from a second prong structure 80.

[0068] like Figure 9As shown, insulating material 72 is deposited over dielectric wall 68 and liner 64. Insulating material 72 fills trench 60B and may also be formed over mask 58 (if present) or the fin. When dielectric wall 68 partially fills trench 60A, insulating material 72 may also be formed in the remaining portion of trench 60A, as shown in FIG. Figure 9 As shown. The insulating material 72 can be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. Once the insulating material 72 is formed, an annealing process can be performed. Although the insulating material 72 is shown as a single layer, in some embodiments, multiple layers can be used. A removal process is then applied to the insulating material 72 to remove excess material of the mask 58 (if present) or the liner 64 above the fin structure 62 and the insulating material 72, such as Figure 10 As shown. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like can be utilized. The planarization process exposes mask 58 or nanostructure 56 so that the upper surface of mask 58 or nanostructure 56, the remaining portion of liner 64, and insulating material 72 are coplanar (within process variations) after the planarization process is completed. In the illustrated embodiment, mask 58 is retained after the planarization process. In another embodiment, mask 58 can also be removed by the planarization process.

[0069] like Figure 11 As shown, insulating material 72 is recessed to form shallow trench isolation (STI) regions 74, thereby reforming local trench 60B. Recessing insulating material 72 causes at least a portion of nanostructure 56 to protrude from shallow trench isolation (STI) regions 74. Insulating material 72 can be recessed using an acceptable etching process, such as an etching process that is selective to insulating material 72 (e.g., an etching process that selectively etches the material of insulating material 72 at a faster rate than etching the material of liner 64 and dielectric layers 66 and 67).

[0070] After forming the shallow trench isolation (STI) regions 74, the fork-piece structure 80 extends from between adjacent shallow trench isolation (STI) regions 74. It should be understood that the above process is only one example of how to form the fork-piece structure 80. Other acceptable processes may also be used to form the fork-piece structure 80 and the shallow trench isolation (STI) regions 74. The fork-piece structure 80 can be processed using a method similar to the processing of semiconductor fins in the process of forming fin field effect transistors (FinFETs). Processing the fork-piece structure 80 in the manner described above allows n-type devices and p-type devices to be integrated into the same fork-piece structure 80.

[0071] Figure 12-15 1 is a cross-sectional view of various stages of manufacturing a semiconductor device structure 100 according to another embodiment. Figure 12 As shown, in some embodiments, Figure 5 The second etching process described in the above embodiment removes the entire dielectric layer 66 located within the trench 60B. Figure 13 As shown, the insulating material 72 fills the gap 61 with the enlarged opening and the trench 60B. In some embodiments, the insulating material 72 includes silicon oxide and is formed by flow chemical vapor deposition (FCVD). The flowable material of the initially deposited insulating material 72 can fill the gap 61 without forming another gap in the insulating material 72 in the trench 60A. An annealing process is then performed to anneal the flowable material and form the insulating material 72. Next, a Figure 10 The planarization process described in the above is used to planarize the upper surface of the semiconductor device structure 100, such as Figure 14 shown.

[0072] Next, a patterned mask layer (not shown) can be formed on the insulating material 72 in trench 60B, exposing the insulating material 72 in trench 60A. A doping process is then performed to implant dopants into the exposed insulating material 72 in trench 60A. In some embodiments, the dopants include carbon and / or nitrogen. Implanting carbon and / or nitrogen allows the insulating material 72 in trench 60A to have a substantially slower etch rate than the insulating material 72 in trench 60B during the subsequent process of forming shallow trench isolation (STI) regions 74.

[0073] like Figure 15As shown, insulating material 72 within trench 60B is recessed to form shallow trench isolation (STI) regions 74 within trench 60B. Because insulating material 72 within trench 60A is doped with carbon and / or nitrogen, and the width of trench 60A is substantially smaller than the width of trench 60B, insulating material 72 within trench 60A is substantially unaffected by the process of recessing insulating material 72 within trench 60B. Insulating material 72 and dielectric layer 66 may comprise different materials with different etch selectivities. In some embodiments, insulating material 72 may be recessed using an acceptable etch process, such as an etch process that is selective for insulating material 72 (e.g., selectively etches insulating material 72 within trench 60B at a faster rate than the etch rates of liner 64, dielectric layer 66, and insulating material 72 within trench 60A). As a result, when shallow trench isolation (STI) regions 74 are formed, a majority of insulating material 72 between dielectric layers 66 is retained. In some embodiments, the upper surface of the insulating material 72 located within the trench 60A may have a concave profile and may be located below the height of the upper surface of the dielectric layer 66 located within the trench 60A, as shown in FIG. Figure 15 shown.

[0074] In some embodiments, the process of forming shallow trench isolation (STI) regions 74 also removes mask 58 (if not already removed by a planarization process after forming insulating material 72 ).

[0075] Figure 16 FIG. 1 is a top view schematically illustrating one of the various stages of fabricating a semiconductor device structure 100 according to some embodiments. For clarity, Figure 16 Details of the dielectric wall 68 are omitted. Figure 16 As shown, one or more sacrificial gate structures 76 are formed above the semiconductor device structure 100. The sacrificial gate structure 76 is formed above a portion of the fin structure 62. Each sacrificial gate structure 76 may include a sacrificial gate dielectric layer (not shown), a sacrificial gate electrode layer 78, and a mask layer (not shown). The sacrificial gate structure 76 may be formed by sequentially depositing a blanket layer of a sacrificial gate dielectric layer, a sacrificial gate electrode layer 78, and a mask layer, and then patterning these layers. Gate spacers 81 ( Figure 17C For example, the gate spacers 81 may be formed by conformally depositing one or more film layers for the gate spacers 81 and anisotropically etching the one or more film layers.

[0076] The sacrificial gate dielectric layer may include one or more layers of dielectric material, such as silicon oxide. The sacrificial gate electrode layer 78 may include polycrystalline silicon or amorphous silicon. The mask layer may include more than one film layer, such as an oxide layer and a nitride layer. The gate spacer 81 may be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0077] Figures 17A-19A Depicted are diagrams according to some embodiments. Figure 16 Schematic cross-sectional views of various stages of manufacturing the semiconductor device structure 100 are taken along line AA. Figures 17B-19B Depicted are diagrams according to some embodiments. Figure 16 BB line is a schematic cross-sectional view of various stages of manufacturing the semiconductor device structure 100. Figures 17C-19C Depicted are diagrams according to some embodiments. Figure 16 1 is a schematic cross-sectional view of various stages of manufacturing the semiconductor device structure 100 taken along line CC. Figures 17A to 19C Details of the dielectric wall 68 are omitted. Figure 17A and 17B FIG. 4 shows a cross-sectional view of the channel region below the sacrificial gate structure 76. Figure 17C A schematic cross-sectional view of the source / drain region is shown.

[0078] like Figure 17A 、 17B As shown in FIG. 17C , the portion of the nanostructure 56 not covered by the sacrificial gate structure 76 is recessed to expose a portion of the semiconductor fin 54. The recessed portion of the nanostructure 56 can be recessed by an etching process, an isotropic or an anisotropic etching process, and the etching process is selective with respect to one or more crystal planes of the substrate 101. The etching process can be a dry etch, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a wet etch (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or any suitable etchant). In some embodiments, recessing the local nanostructure 56 also recesses the exposed portion of the dielectric wall 68, such as Figure 17C As shown. As a result, the portion of the dielectric wall 68 located below the sacrificial gate structure 76 has a first height H1, and the portion of the dielectric wall 68 not covered by the sacrificial gate structure 76 has a second height H2, which is substantially less than the first height H1. In some embodiments, as Figure 17B As shown, a distance D1 is provided between the upper surface of the portion of the dielectric wall 68 below the sacrificial gate structure 76 and the upper surface of the uppermost second nanostructure 56B. The distance D1 may be approximately in the range of 10 nm to 20 nm.

[0079] Although Figure 17A 、 17B Although not shown in FIG17C , after recessing the portion of first nanostructure 56A not covered by sacrificial gate structure 76 , the edge portion of each first nanostructure 56A is horizontally removed along the X-direction. Removal of the edge portion of first nanostructure 56A forms a cavity. In some embodiments, the edge portion of first nanostructure 56A is removed by a selective wet etching process. When first nanostructure 56A is made of SiGe and second nanostructure 56B is made of silicon, a wet etchant (such as, but not limited to, ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution) can be used to selectively etch first nanostructure 56A.

[0080] After removing the edge portions of each first nanostructure 56A, a dielectric layer is deposited within the cavity to form dielectric spacers (not shown). The dielectric spacers can be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers can be formed by first forming the compliant dielectric layer using a compliant deposition process (e.g., atomic layer deposition (ALD)), followed by an anisotropic etching process to remove portions of the compliant dielectric layer except for the dielectric spacers. During the anisotropic etching process, the dielectric spacers are protected by the second nanostructures 56B. The remaining first nanostructures 56A are covered between the dielectric spacers along the X-direction.

[0081] like Figure 17CAs shown, source / drain (S / D) regions 82P, 82N are formed by the exposed portions of the semiconductor fin 54. The source / drain (S / D) regions 82P, 82N can be grown vertically and horizontally to form facets, which can correspond to the crystal planes of the material used for the semiconductor fin 54. In embodiments of the present invention, source regions and drain regions can be used interchangeably, and their structures are substantially the same. Furthermore, the source / drain regions can be referred to as source or drain, either alone or together, depending on the context. For an n-type field effect transistor (NFET), the source / drain (S / D) region 82N can be made of one or more layers of Si, SiP, and SiAs, and for a p-type field effect transistor (PFET), the source / drain (S / D) region 82P can be made of one or more layers of SiGe, SiGeB, and GeSn. For a p-type field effect transistor (PFET), a p-type dopant (e.g., boron (B)) may also be included in the source / drain (S / D) region 82P. The source / drain (S / D) regions 82P, 82N may be formed by epitaxial growth methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). The source / drain (S / D) regions 82P, 82N may be formed at different times using one or more masks (not shown). In some embodiments, the source / drain (S / D) regions 82P, 82N are separated by a dielectric wall 68, such as Figure 17C shown.

[0082] like Figure 18A 、 18BAs shown in FIG18C and FIG18C , a contact etch stop layer (CESL) 84 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 84 covers the gate spacers 81 (formed on the sidewalls of the semiconductor device structure 100), the sacrificial gate structure 76, the shallow trench isolation (STI) region 74, the dielectric wall 68, and the source / drain (S / D) regions 82P and 82N. The CESL 84 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof, and may be formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or any other suitable deposition technique. Next, an interlayer dielectric (ILD) layer 86 is formed on the CESL 84 over the semiconductor device structure 100. The material of the interlayer dielectric (ILD) layer 86 may include a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for the interlayer dielectric (ILD) layer 86. The interlayer dielectric (ILD) layer 86 may be deposited using a plasma enhanced chemical vapor deposition (PECVD) process or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric (ILD) layer 86, the semiconductor device structure 100 may be thermally treated to anneal the interlayer dielectric (ILD) layer 86.

[0083] After forming the interlayer dielectric (ILD) layer 86, the semiconductor device structure 100 is planarized (e.g., chemical mechanical polishing (CMP)) until the sacrificial gate electrode layer 78 ( Figure 17A ). Next, the sacrificial gate structure 76 and the first nanostructure 56A are removed. The removal of the sacrificial gate structure 76 and the first nanostructure 56A forms openings between the gate spacers 81 and between the second nanostructures 56B. The interlayer dielectric (ILD) layer 86 protects the source / drain (S / D) regions 82P, 82N during the removal process. The sacrificial gate structure 76 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 78 can be first removed by any suitable process (e.g., dry etching, wet etching, or a combination thereof), followed by the removal of the sacrificial gate dielectric layer, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant (e.g., a tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 78 without removing the gate spacers 81, the interlayer dielectric (ILD) layer 86, and the contact etch stop layer (CESL) 84.

[0084] The first nanostructure 56A may be removed using a selective wet etching process. In one embodiment, the first nanostructure 56A may be removed using a wet etchant (e.g., but not limited to, hydrofluoric acid (HF), nitric acid (HNO 3 ), hydrochloric acid (HCl), phosphoric acid (H 3 PO 4 )), a dry etchant (e.g., a fluorine-based gas (e.g., F 2 ) or a chlorine-based gas (e.g., Cl 2 )), or any suitable isotropic etchant.

[0085] like Figure 19A 、 19B As shown in FIG19C , after the nanostructure channel (ie, the exposed portion of the second nanostructure 56B) is formed, a gate dielectric layer 88 is formed to surround the exposed portion of the second nanostructure 56B, and gate electrode layers 90P and 90N are formed on the gate dielectric layer 88 .

[0086] The gate dielectric layer 88 and the gate electrode layer 90P or 90N may be collectively referred to as a gate structure. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 88 and the exposed surface of the second nanostructure 56B. In some embodiments, the gate dielectric layer 88 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 88 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or any suitable deposition technique. The gate electrode layer 90P may include one or more layers of conductive materials, such as TiN, TaN, Ru, Mo, Al, WN, TiSiN, TiTaN, TiAlN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, or other suitable materials or any combination thereof. The gate electrode layer 90N may include one or more layers of conductive materials, such as Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, TiAl, TiTaN, Mn, Zr, or other suitable N-type work function materials or any combination thereof. The gate electrode layers 90N and 90P may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, or other suitable deposition techniques. The gate electrode layers 90N and 90P may also be deposited over the upper surface of the interlayer dielectric (ILD) layer 86. The gate dielectric layer 88 and the gate electrode layers 90N and 90P formed on the ILD layer 86 are then removed by using, for example, chemical mechanical polishing (CMP) until the upper surface of the ILD layer 86 is exposed.

[0087] It should be understood that the semiconductor device structure 100 may undergo further processing to form conductive contacts within the interlayer dielectric (ILD) layer 86 to electrically connect to the source / drain (S / D) regions 82N, 82P, and to form conductive contacts to electrically connect to the gate electrode layers 90N, 90P. Interconnect structures may be formed above the semiconductor device structure 100 to provide an electrical path to devices formed on the substrate 50.

[0088] In various embodiments, the present invention provides a dielectric wall 68 that electrically isolates source / drain (S / D) regions 82N and 82P. Dielectric wall 68 can be formed by a first deposition process (e.g., an atomic layer deposition (ALD) process), followed by first and second etching processes (e.g., an anisotropic etching process and an isotropic etching process), and a second deposition process. Some embodiments can achieve various advantages. For example, the first and second etching processes can expand the opening of gap 61, thereby completely filling gap 61. Dielectric wall 68 electrically isolates source / drain (S / D) regions 82N and 82P.

[0089] In one embodiment, a method for forming a semiconductor device structure is provided. The method includes forming first and second fin structures on a substrate and forming a dielectric wall between the first and second fin structures. Forming the dielectric wall includes depositing a first dielectric layer between the first fin structure and the second fin structure, and forming a gap in the first dielectric layer. Forming the dielectric wall also includes performing an anisotropic etching process to remove a portion of the first dielectric layer to expose the gap; performing an isotropic etching process to expand the opening of the gap, and the gap has a "V"-shaped cross-sectional profile. Forming the dielectric wall also includes depositing a second dielectric layer between the first fin structure and the second fin structure, and filling the gap. The method also includes forming a plurality of shallow trench isolation regions adjacent to the first and second fin structures.

[0090] In some embodiments, the first dielectric layer and the second dielectric layer include the same material. Furthermore, in some embodiments, the material of the first dielectric layer and the second dielectric layer is SiCN, the thickness of the first dielectric layer is in the range of 7nm to 9nm, and the thickness of the second dielectric layer is in the range of 3nm to 4nm. In some embodiments, the first dielectric layer is formed by atomic layer deposition. In some embodiments, the first dielectric layer and the second dielectric layer are formed by the same process. In some embodiments, the first dielectric layer and the second dielectric layer are formed by different processes. In some embodiments, the above method also includes forming a third fin structure on the substrate before forming the dielectric wall. Furthermore, in some embodiments, the first dielectric layer and the second dielectric layer are formed between the second fin structure and the third fin structure. Furthermore, in some embodiments, the above method also includes removing the first and second dielectric layers formed between the second and third fin structures before forming the shallow trench isolation region.

[0091] In another embodiment, a method for forming a semiconductor device structure is provided. The method includes: forming first, second, and third fin structures on a substrate; depositing a liner around the first, second, and third fin structures; and depositing a dielectric layer between the first and second fin structures and between the second and third fin structures, with a gap formed in the dielectric layer between the first and second fin structures. The method also includes: removing a portion of the dielectric layer between the first and second fin structures to expose the gap and a portion of the dielectric layer between the second and third fin structures to expose the liner; and depositing an insulating material to bury the first, second, and third fin structures, the insulating material contacting the liner between the second and third fin structures and filling the gap between the first and second fin structures. The method also includes: implanting a dopant into the insulating material between the first and second fin structures; and performing an etching process. The insulating material between the first and second fin structures is etched at a slower etch rate than the insulating material between the second and third fin structures.

[0092] In some embodiments, the dielectric layer and the insulating material comprise different materials. Furthermore, in some embodiments, the dielectric layer comprises SiN, SiC, SiCN, AlOx, or SiOCN, and the insulating material comprises silicon oxide. In some embodiments, the liner comprises a semiconductor material. In some embodiments, the dielectric layer is deposited by atomic layer deposition, and the insulating material is deposited by flow chemical vapor deposition. In some embodiments, the distance between the first fin structure and the second fin structure is substantially less than the distance between the second fin structure and the third fin structure. In some embodiments, each of the first, second, and third fin structures comprises alternating first and second nanostructures.

[0093] In yet another embodiment, a method for forming a semiconductor device structure is provided. The method includes: forming first, second, and third fin structures above a substrate, a first trench having a first width formed between the first and second fin structures, and a second trench having a second width substantially greater than the first width formed between the second and third fin structures. The method also includes: depositing a first dielectric layer in the first trench and the second trench, a gap formed in the first dielectric layer in the first trench, and the first dielectric layer being a compliant layer. The method also includes: removing portions of the first dielectric layer located in the first trench and the second trench, and exposing the gap located in the first trench. The method also includes: depositing a second dielectric layer in the first trench and the second trench, filling the gap located in the first trench with the second dielectric layer, and forming a dielectric wall having the first and second dielectric layers in the first trench. The method also includes: removing the first dielectric layer and the second dielectric layer located in the second trench, and an upper surface of the dielectric wall is located below the height of an upper surface of the first fin structure. The method further includes forming a shallow trench isolation region in the second trench.

[0094] In some embodiments, the method further includes: forming a sacrificial gate structure on a portion of the first fin structure, on a portion of the second fin structure, and on a portion of the dielectric wall; recessing the exposed portion of the first fin structure, the exposed portion of the second fin structure, and the exposed portion of the dielectric wall; forming first and second source / drain (S / D) regions from the recessed first and second fin structures, wherein the first source / drain (S / D) region is separated from the second source / drain (S / D) region by the dielectric wall; and forming an interlayer dielectric (ILD) layer over the first and second source / drain (S / D) regions. Furthermore, in some embodiments, the method further includes: removing the sacrificial gate structure; and forming a first gate electrode layer on the portion of the first fin structure and a second gate electrode layer on the portion of the second fin structure, wherein the portion of the dielectric wall is located below the first gate electrode layer and the second gate electrode layer. In some embodiments, the portion of the dielectric wall separating the first and second source / drain (S / D) regions has a height substantially smaller than a height of the portion of the dielectric wall below the first and second gate electrode layers.

[0095] The above briefly describes the characteristic components of several embodiments of the present invention, so that those skilled in the art can more easily understand the types of embodiments of the present invention. Anyone skilled in the art should understand that the embodiments of the present invention can be easily used as a basis for changes or designs of other processes or structures to achieve the same purposes and / or obtain the same advantages as the embodiments described herein. Anyone skilled in the art will also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the embodiments of the present invention, and can be changed, replaced, and modified without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A semiconductor device structure, characterized in that: include: A first fin structure and a second fin structure are located on a substrate; as well as A dielectric wall comprising: A first dielectric layer and a second dielectric layer are located between the first fin structure and the second fin structure, wherein the second dielectric layer is surrounded by the first dielectric layer and has a V-shaped cross-sectional profile.

2. The semiconductor device structure according to claim 1, wherein: The first dielectric layer contacts the “V”-shaped cross-sectional profile of the second dielectric layer.

3. The semiconductor device structure according to claim 1, wherein: The thickness of the first dielectric layer is in a range of 7 nm to 9 nm, and the thickness of the second dielectric layer is in a range of 3 nm to 4 nm.

4. The semiconductor device structure according to claim 1, wherein: Also includes: A plurality of shallow trench isolation regions are adjacent to the first fin structure and the second fin structure.

5. The semiconductor device structure according to claim 1, wherein: Also includes: A third fin structure is formed on the substrate.

6. The semiconductor device structure according to claim 5, wherein: The first dielectric layer and the second dielectric layer are located between the second fin structure and the third fin structure.

7. The semiconductor device structure according to claim 6, wherein: A distance between the first fin structure and the second fin structure is smaller than a distance between the second fin structure and the third fin structure.

8. The semiconductor device structure according to claim 5, wherein: Each of the first fin structure, the second fin structure, and the third fin structure includes alternating first nanostructures and second nanostructures.

9. The semiconductor device structure according to claim 1, wherein: Also includes: a first source / drain region located on the first fin structure; a second source / drain region located on the second fin structure; as well as An interlayer dielectric layer is located above the first source / drain region and the second source / drain region.

10. The semiconductor device structure according to claim 9, wherein: The first source / drain region is separated from the second source / drain region by the dielectric wall.

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