Display panel

Abstract

The display panel includes a base layer, a pixel defining film defining a plurality of light-emitting opening portions, a conductive partition defining a plurality of partition opening portions, a first light-emitting element disposed in the first light-emitting opening portion and including a first light-emitting layer, and a second light-emitting element disposed in the second light-emitting opening portion and including a second light-emitting layer. The area of the first light-emitting layer in contact with the partition wall and the area of the second light-emitting layer in contact with the partition wall are different from each other.

Description

Technical Field

[0001] The utility model relates to a display device, and more particularly, to a display panel with improved display quality. Background Art

[0002] Display devices such as televisions, monitors, smartphones, and tablets that provide images to users include display panels for displaying these images. Various display panels are currently under development, including liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels.

[0003] An organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern may be separated according to each light emitting area, and the cathode provides a common voltage to each light emitting area. Utility Model Content

[0004] The utility model can provide a display panel and a method for manufacturing the display panel, which can improve the display quality in a display panel in which light-emitting elements are formed without using a metal mask.

[0005] According to one embodiment of the present invention, a display panel is provided, comprising: a base layer; a pixel defining film, arranged on the base layer and defining a plurality of light-emitting openings separated from each other; a partition wall, arranged on the pixel defining film, defining a plurality of partition wall openings respectively overlapping with the light-emitting openings, and having conductivity; a first light-emitting element, arranged at a first light-emitting opening among the light-emitting openings, and comprising a first anode, a first light-emitting layer, arranged on the first anode and formed of a light-emitting substance that generates light of a first color, and a first cathode, arranged on the first light-emitting layer and connected to the partition wall; and a second light-emitting element, arranged at a second light-emitting opening among the light-emitting openings, and comprising a second anode, a second light-emitting layer, arranged on the second anode and formed of a light-emitting substance that generates light of a second color different from the first color, and a second cathode, arranged on the second light-emitting layer and connected to the partition wall, wherein an area of the first light-emitting layer in contact with the partition wall is different from an area of the second light-emitting layer in contact with the partition wall.

[0006] A display panel may be provided, wherein a cross-sectional shape of a portion of the first light-emitting layer in contact with the partition wall is different from a cross-sectional shape of a portion of the second light-emitting layer in contact with the partition wall.

[0007] It may be that a display panel is provided, wherein the first light-emitting layer includes: a first light-emitting layer portion, which is arranged on the first anode and includes an upper portion located at a first height from the upper portion of the base layer; and a second light-emitting layer portion, which is arranged on the pixel defining film and includes an upper portion located at a second height higher than the first height, and the height of the upper portion of the second light-emitting layer portion increases from the upper portion of the base layer as it is adjacent to the partition wall.

[0008] It may be that a display panel is provided, wherein the second cathode includes: a first cathode portion, arranged on the second light-emitting layer, and including an upper portion located at a third height from the upper portion of the base layer; and a second cathode portion, arranged on the second light-emitting layer, and including an upper portion located at a fourth height higher than the third height, and the height of the upper portion of the second cathode portion increases from the upper portion of the base layer as it is adjacent to the partition wall.

[0009] It may be that a display panel is provided, wherein the first color is blue.

[0010] It may be that a display panel is provided, which further includes: a first encapsulation layer, including a first encapsulation pattern covering the first light-emitting opening portion and a second encapsulation pattern separated from the first encapsulation pattern and covering the second light-emitting opening portion; and a second encapsulation layer covering the first encapsulation layer.

[0011] It may be that a display panel is provided, which further includes: a third light-emitting element, which is arranged in a third light-emitting opening portion in the light-emitting opening portion, and includes a third anode, a third light-emitting layer arranged on the third anode and formed by a light-emitting material that generates light of a third color different from the first color, and a third cathode arranged on the third light-emitting layer and connected to the adjacent wall, wherein the second color and the third color are different colors of green or red respectively.

[0012] Alternatively, a display panel is provided, wherein the second encapsulation pattern further covers the third light-emitting element.

[0013] A display panel may be provided, wherein a portion of the second light-emitting layer in contact with the partition wall has the same cross-sectional shape as a portion of the third light-emitting layer in contact with the partition wall.

[0014] According to one embodiment of the present invention, a display panel is provided, comprising: a base layer; a pixel defining film, arranged on the base layer, and defining a plurality of light-emitting openings separated from each other; a partition wall, arranged on the pixel defining film, and defining a plurality of partition wall openings respectively overlapping with the light-emitting openings, and having conductivity; a first light-emitting element, arranged in a first light-emitting opening among the light-emitting openings, and comprising a first anode, a first light-emitting layer, arranged on the first anode and formed of a light-emitting substance that generates light of a first color, and a first cathode, arranged on the first light-emitting layer and connected to the partition wall; a second light-emitting element, arranged in a second light-emitting opening among the light-emitting openings, and comprising a second anode, a first light-emitting layer, arranged on the first light-emitting layer, and connected to the partition wall. A second light-emitting layer formed on the second anode by a light-emitting material that generates light of a second color different from the first color, and a second cathode arranged on the second light-emitting layer and connected to the next wall; a third light-emitting element, arranged in a third light-emitting opening portion in the light-emitting opening portion, and including a third anode, a third light-emitting layer formed on the third anode by a light-emitting material that generates light of a third color different from the first color, and a third cathode arranged on the third light-emitting layer and connected to the next wall; and a first packaging layer, including a first packaging pattern covering the first light-emitting opening portion and a second packaging pattern separated from the first packaging pattern and covering the second light-emitting opening portion and the third light-emitting opening portion.

[0015] Alternatively, a display panel is provided, further comprising: a second encapsulation layer covering the first encapsulation pattern and the second encapsulation pattern.

[0016] It may be that a display panel is provided, wherein the cross-sectional shape of the portion of the first light-emitting layer in contact with the partition wall is different from the cross-sectional shape of the portion of the second light-emitting layer in contact with the partition wall, and the cross-sectional shape of the portion of the second light-emitting layer in contact with the partition wall is the same as the cross-sectional shape of the portion of the third light-emitting layer in contact with the partition wall.

[0017] It may be that a display panel is provided, wherein the first light-emitting layer includes: a first light-emitting layer portion, arranged on the first anode, and including an upper portion located at a first height from the upper portion of the base layer; and a second light-emitting layer portion, arranged on the pixel defining film, and including an upper portion higher than the first height, and the height of the upper portion of the second light-emitting layer portion increases from the upper portion of the base layer toward the partition wall.

[0018] According to one embodiment of the present invention, a method for manufacturing a display panel is provided, comprising: providing a preliminary display panel including a base layer, an anode arranged on the base layer, and a preliminary pixel defining film arranged on the base layer and covering the anode; forming a partition wall arranged on the preliminary pixel defining film and having a plurality of partition wall openings; patterning the preliminary pixel defining film to form a plurality of light-emitting openings overlapping with each of the plurality of partition wall openings and exposing at least a portion of the anode, thereby forming a pixel defining film; and forming a first light-emitting layer and a second light-emitting layer in each partition wall opening, each including a first light-emitting substance and a second light-emitting substance that respectively generate light of a first color and a second color different from each other, and a first cathode and a second cathode in contact with the partition wall, wherein the first light-emitting layer is formed by thermal evaporation, and the second light-emitting layer is formed by a method different from the first light-emitting layer.

[0019] Alternatively, a method for manufacturing a display panel is provided, wherein the second light-emitting layer is formed by inkjet.

[0020] Alternatively, a method for manufacturing a display panel may be provided, wherein when evaporating the first light-emitting layer and the first cathode, the evaporation angle of the first light-emitting layer and the evaporation angle of the first cathode are different.

[0021] It may be that a display panel manufacturing method is provided, wherein the steps of forming the partition wall include: a step of forming a first layer on the pixel defining film using a conductive material; a step of forming a second layer on the first layer using a material different from the conductive material; a first etching step of patterning the first layer and the second layer to form a first pattern; and a second etching step of undercutting the first layer relative to the second layer, and the side of the second layer protruding from the side of the first layer to form a pointed end.

[0022] It may be that a display panel manufacturing method is provided, wherein the multiple light-emitting opening portions include a first light-emitting opening portion and a second light-emitting opening portion, and the display panel manufacturing method further includes: a step of forming a first packaging pattern covering the first light-emitting opening portion; and a step of forming a second packaging pattern covering the second light-emitting opening portion, the first packaging pattern and the second packaging pattern are formed to be separated from each other.

[0023] Alternatively, a method for manufacturing a display panel may be provided, wherein the first cathode and the second cathode are formed to be separated from each other.

[0024] It may be that a display panel manufacturing method is provided, wherein the multiple light-emitting openings include first to third light-emitting openings, and the display panel manufacturing method also includes: a step of forming a third light-emitting layer including a third light-emitting material that generates light of a third color different from the first color and the second color in each adjacent opening; a step of forming a third cathode separated from the first cathode; a step of forming a first packaging pattern covering the first light-emitting opening; and a step of forming a second packaging pattern that covers the second light-emitting opening and the third light-emitting opening and is separated from the first packaging pattern, and the third light-emitting layer is formed in a manner different from the first light-emitting layer.

[0025] According to an embodiment of the present invention, a display panel and a method for manufacturing the display panel can form a light-emitting element without using a metal mask.

[0026] A display panel and a method for manufacturing the display panel according to an embodiment of the present invention can form a light-emitting element with improved process reliability.

[0027] According to an embodiment of the present invention, a display panel and a method for manufacturing the display panel can coat a portion of the luminescent material in an inkjet manner, thereby increasing process efficiency and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a It is a three-dimensional diagram of a display device according to an embodiment of the present invention.

[0029] Figure 1b It is an exploded perspective view of a display device according to an embodiment of the present invention.

[0030] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present invention.

[0031] Figure 3 is a plan view of a display panel according to an embodiment of the present invention.

[0032] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0033] Figure 5 It is a plan view of an enlarged portion of a display panel according to an embodiment of the present invention.

[0034] Figure 6a as well as Figure 6b is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention.

[0035] Figure 7a as well as Figure 7b It is a cross-sectional view showing an enlarged portion of a display panel according to an embodiment of the present invention.

[0036] Figure 8a as well as Figure 8b It is a cross-sectional view showing an enlarged portion of a display panel according to an embodiment of the present invention.

[0037] Figures 9a to 9c It is a cross-sectional view showing a portion of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0038] Figures 10a to 10i It is a cross-sectional view showing a portion of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0039] Figures 11a to 11c It is a cross-sectional view showing a portion of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0040] (Explanation of Reference Numerals)

[0041] DP: Display Panel BL: Base Layer

[0042] OP-E: light-emitting opening PDL: pixel definition layer

[0043] OP-P: Opening of next door PW: Next door

[0044] AE: Anode EL: Light Emitting Layer

[0045] CE: cathode ED: light emitting element

[0046] L1: first partition wall layer L2: second partition wall layer

[0047] SP: Sacrifice Pattern DETAILED DESCRIPTION

[0048] In this specification, when any constituent element (or region, layer, part, etc.) is mentioned as being "on" other constituent elements, "connected to" or "combined to" other constituent elements, it means that any constituent element can be directly configured / connected / combined to other constituent elements or a third constituent element can be configured between them.

[0049] The same reference numerals refer to the same components. In the accompanying drawings, the thickness, proportions, and dimensions of the components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" includes all possible combinations of the associated components.

[0050] Terms such as "first" and "second" may be used to describe various constituent elements, but the constituent elements are not limited by these terms. These terms are used solely to distinguish one constituent element from other constituent elements. For example, without departing from the scope of the present invention, the first constituent element may be named the second constituent element, and similarly, the second constituent element may be named the first constituent element. Unless otherwise expressly indicated in the context, a singular expression encompasses a plural expression.

[0051] In addition, terms such as “below,” “lower side,” “above,” and “upper side” are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0052] Terms such as "including" or "having" should be understood as being used to specify the existence of features, numbers, steps, tasks, constituent elements, parts or their combinations recorded in the specification, and do not preclude the existence or additional possibilities of one or more other features or numbers, steps, tasks, constituent elements, parts or their combinations.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meanings as those commonly understood by those skilled in the art to which this utility model belongs. In addition, terms such as terms defined in commonly used dictionaries should be interpreted as having the same meanings as those in the context of the relevant technology, and unless otherwise explicitly defined, should not be interpreted as having overly idealized or formalized meanings.

[0054] Hereinafter, a display panel and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0055] Figure 1a is a perspective view of a display device according to an embodiment of the present invention. Figure 1b It is an exploded perspective view of a display device according to an embodiment of the present invention.

[0056] In one embodiment of the present invention, the display device DD may be a large electronic device such as a television, a monitor, or an external advertising board. Alternatively, the display device DD may be a small or medium-sized electronic device such as a personal computer, a notebook computer, a personal digital terminal, a car navigation unit, a game console, a smart phone, a tablet, or a camera. However, this is for illustrative purposes only, and other display devices may also be used without departing from the concept of the present invention. Figure 1a as well as Figure 1b , the display device DD is exemplarily shown as a smart phone.

[0057] Reference Figure 1a as well as Figure 1bThe display device DD can display an image IM toward the third direction DR3 on a display surface FS that is parallel to each of the first direction DR1 and the second direction DR2. The image IM may include a dynamic image and a still image. Figure 1a , a clock window and an icon are shown as an example of the image IM. The display surface FS displaying the image IM may correspond to the front surface of the display device DD.

[0058] In this embodiment, the front (or top) and back (or bottom) of each component are defined based on the direction in which the image IM is displayed. The front and back may be opposite each other in a third direction DR3, and the normal direction of each of the front and back may be parallel to the third direction DR3. Meanwhile, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and can be converted to other directions. In this specification, "on a plane" can be defined as a state viewed in the third direction DR3.

[0059] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be combined with each other to form the appearance of the display device DD.

[0060] The window WP may comprise an optically transparent insulating material. For example, the window WP may comprise glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmissive area TA and a frame area BZA. The transmissive area TA may be an optically transparent area. For example, the transmissive area TA may have a visible light transmittance of approximately 90% or greater.

[0061] The frame area BZA may have a relatively lower light transmittance than the transmissive area TA. The frame area BZA may define the shape of the transmissive area TA. The frame area BZA may be adjacent to and surround the transmissive area TA. However, this is shown as an example, and the frame area BZA of the window WP may be omitted. The window WP may include at least one functional layer selected from the group consisting of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to any one embodiment.

[0062] The display module DM may be disposed below the window WP. The display module DM may be a structure that substantially generates an image IM. The image IM generated in the display module DM is displayed on the display surface IS of the display module DM and is externally visible to a user through the transmissive area TA.

[0063] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be activated by an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. As the non-display area NDA is covered by the bezel area BZA, it may not be visible from the outside.

[0064] The housing HAU can be combined with the window WP to provide a predetermined internal space. The display module DM can be accommodated in the internal space.

[0065] The housing HAU can be made of a relatively rigid material. For example, the housing HAU can be made of glass, plastic, or metal, or a combination thereof, including multiple frames and / or panels. The housing HAU can stably protect the structure of the display device DD housed within the interior from external impacts.

[0066] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present invention.

[0067] Reference Figure 2 The display module DM may include a display panel DP and an input sensor INS. Although not shown separately, the display device DD according to an embodiment of the present invention (see FIG. Figure 1a ) may further include a protective component arranged below the display panel DP or an anti-reflection component and / or a window component arranged above the input sensor INS.

[0068] The display panel DP may be a light-emitting display panel. However, this is merely an example and is not particularly limiting. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in an organic light-emitting display panel may include an organic light-emitting substance. The light-emitting layer in an inorganic light-emitting display panel may include quantum dots, quantum rods, or micro-LEDs. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0069] The display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS may be disposed directly on the thin film encapsulation layer TFE. In this specification, "structure A is disposed directly on structure B" means that no adhesive layer is disposed between the structures A and B.

[0070] The base layer BL may include at least one plastic film. As a flexible substrate, the base layer BL may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. Figure 1bThe display area DA and the non-display area NDA described in the accompanying drawings may be identically defined on the base layer BL.

[0071] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer may include at least one inorganic layer and at least one organic layer. The circuit elements may include signal lines, pixel driving circuits, etc.

[0072] The display element layer DP-OLED may include a partition wall and a light-emitting element. The light-emitting element may include an anode, an intermediate layer, and a cathode.

[0073] The thin film encapsulation layer TFE may include multiple thin films, some of which may be configured to improve optical efficiency, and some of which may be configured to protect the organic light emitting diode.

[0074] The input sensor INS obtains coordinate information of an external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single or multiple conductive layers. Furthermore, the input sensor INS may include a single or multiple insulating layers. The input sensor INS may sense the external input capacitively. However, this is merely an example and is not limiting. For example, in one embodiment, the input sensor INS may also sense the external input using electromagnetic induction or pressure sensing. Alternatively, in another embodiment of the present invention, the input sensor INS may be omitted.

[0075] Figure 3 is a plan view of a display panel according to an embodiment of the present invention.

[0076] Reference Figure 3 The display panel DP may define a display area DA and a non-display area NDA surrounding the display area DA. The display area DA and the non-display area NDA may be divided by the presence or absence of pixels PX. Pixels PX may be disposed in the display area DA. A scan driver SDV, a data driver, and a light driver EDV may be disposed in the non-display area NDA. The data driver may be part of the circuitry of the driver chip DIC.

[0077] The display panel DP may include pixels PX, initialization scan lines GIL1-GILm, compensation scan lines GCL1-GCLm, write scan lines GWL1-GWLm, black scan lines GBL1-GBLm, emission control lines ECL1-ECLm, data lines DL1-DLn, first and second control lines CSL1 and CSL2, a driving voltage line PVL, and a plurality of pads PD. Here, m and n are natural numbers greater than or equal to 2.

[0078] The pixels PX may be connected to initialization scan lines GIL1 -GILm, compensation scan lines GCL1 -GCLm, write scan lines GWL1 -GWLm, black scan lines GBL1 -GBLm, emission control lines ECL1 -ECLm, and data lines DL1 -DLn.

[0079] The initialization scan lines GIL1-GILm, compensation scan lines GCL1-GCLm, write scan lines GWL1-GWLm, and black scan lines GBL1-GBLm may extend in a first direction DR1 and be electrically connected to the scan driver SDV. The data lines DL1-DLn may extend in a second direction DR2 and be electrically connected to the driver chip DIC. The emission control lines ECL1-ECLm may extend in the first direction DR1 and be electrically connected to the emission driver EDV.

[0080] The driving voltage line PVL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be configured on different layers. The driving voltage line PVL may provide a driving voltage to the pixel PX.

[0081] The first control line CSL1 may be connected to the scan driving part SDV, and the second control line CSL2 may be connected to the light emitting driving part EDV.

[0082] The driver chip DIC, the driving voltage line PVL, the first control line CSL1, and the second control line CSL2 can be electrically connected to the pad PD. The flexible circuit film FCB can be electrically connected to the pad PD via an anisotropic conductive adhesive layer. The pad PD can be used to connect the flexible circuit film FCB to the display panel DP. The pad PD can be connected to the corresponding pixel PX via the driving voltage line PVL, the first control line CSL1, and the second control line CSL2.

[0083] In addition, the pad PD may also include an input pad. The input pad may be used to connect the flexible circuit film FCB to the input sensor INS (see Figure 2 However, without limitation thereto, the input pad may be configured in the input sensor INS, thereby being connected to the pad PD and a separate circuit substrate. Alternatively, the input sensor INS may be omitted, and the input pad may not be included.

[0084] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0085] exist Figure 4 A plurality of pixels PX are exemplarily shown in FIG. Figure 3) is an equivalent circuit diagram of one pixel PXij in FIG. Each of the plurality of pixels PX has the same circuit configuration, so the circuit configuration of the pixel PXij is described first and the detailed description of the remaining pixels PX is omitted.

[0086] Reference Figure 3 as well as Figure 4 Pixel PXij is connected to the i-th data line DLi among the data lines DL1-DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1-GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1-GCLm, the j-th write scan line GWLj among the write scan lines GWL1-GWLm, the j-th black scan line GBLj among the black scan lines GBL1-GBLm, the j-th emission control line ECLj among the emission control lines ECL1-ECLm, the first and second drive voltage lines VL1 and VL2, and the first and second initialization voltage lines VL3 and VL4. i is an integer greater than 1 and less than n, and j is an integer greater than 1 and less than m.

[0087] Pixel PXij includes a light-emitting element ED and a pixel circuit PDC. The light-emitting element ED may be a light-emitting diode. As an example of the present invention, the light-emitting element ED may be an organic light-emitting diode including an organic light-emitting layer, but is not particularly limited thereto. The pixel circuit PDC controls the amount of current flowing into the light-emitting element ED in response to a data signal Di. The light-emitting element ED emits light at a predetermined brightness in response to the current supplied by the pixel circuit PDC.

[0088] The pixel circuit PDC may include first to seventh transistors T1, T2, T3, T4, T5, T6, T7 and first to third capacitors Cst, Cbst, Nbst. According to the present invention, the structure of the pixel circuit PDC is not limited to Figure 4 The embodiment shown. Figure 4 The pixel circuit PDC shown is merely an example, and the structure of the pixel circuit PDC may be modified.

[0089] At least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a transistor having an oxide semiconductor layer. For example, the third and fourth transistors T3 and T4 may be oxide semiconductor transistors, and the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be LTPS transistors.

[0090] Specifically, in the case of the first transistor T1 that directly affects the brightness of the light-emitting element ED, it can be constructed to include a semiconductor layer composed of reliable polycrystalline silicon, and a high-resolution display device can be realized therethrough. On the other hand, oxide semiconductors have high carrier mobility and low leakage current, so even if the driving time is long, the voltage drop is not large. That is, when driven at a low frequency, the color change of the image according to the voltage drop is not large, so it can be driven at a low frequency. In this way, in the case of oxide semiconductors, there is an advantage of low leakage current, so at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 is used as an oxide semiconductor to prevent leakage current that may flow to the gate electrode while reducing power consumption.

[0091] Some of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be P-type transistors, and the remaining may be N-type transistors. For example, the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be P-type transistors, and the third and fourth transistors T3 and T4 may be N-type transistors.

[0092] The structure of the pixel circuit PDC according to the present invention is not limited to Figure 4 The embodiment shown. Figure 4 The pixel circuit PDC shown is merely an example, and its structure can be modified. For example, the first through seventh transistors T1, T2, T3, T4, T5, T6, and T7 can all be P-type transistors or N-type transistors. Alternatively, the first, second, fifth, and sixth transistors T1, T2, T5, and T6 can be P-type transistors, while the third, fourth, and seventh transistors T3, T4, and T7 can be N-type transistors.

[0093] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj can respectively transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di can have the same value as that input to the display device DD (refer to Figure 1a 、 Figure 1b )’s image signal.

[0094] The first and second driving voltage lines VL1 and VL2 can transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixels PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 can transmit the first initialization voltage VINT and the second initialization voltage VAINT to the pixels PXij, respectively.

[0095] The first transistor T1 is connected between a first driving voltage line VL1 receiving a first driving voltage ELVDD and the light-emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or anode) of the light-emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end of the first capacitor Cst (e.g., a first node N1). The first transistor T1 can receive an i-th data signal Di transmitted from an i-th data line DLi based on the switching operation of the second transistor T2 and supply a driving current to the light-emitting element ED.

[0096] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 can be turned on in response to the j-th write scan signal GWj received via the j-th write scan line GWLj to transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst can be connected to the third electrode of the second transistor T2, and the other end of the second capacitor Cbst is connected to the first node N1.

[0097] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 can be turned on in response to the j-th compensation scan signal GCj transmitted via the j-th compensation scan line GCLj, thereby connecting the third electrode of the first transistor T1 and the second electrode of the first transistor T1 to each other, thereby diode-connecting the first transistor T1. One end of the third capacitor Nbst can be connected to the third electrode of the third transistor T3, and the other end of the third capacitor Nbst is connected to the first node N1.

[0098] The fourth transistor T4 is connected between the first initialization voltage line VL3, which applies the first initialization voltage VINT, and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 that transmits the first initialization voltage VINT, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line GILj. The fourth transistor T4 is turned on in response to the j-th initialization scan signal GIj received via the j-th initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1, thereby initializing the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0099] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode of the light-emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj.

[0100] The fifth and sixth transistors T5 and T6 are simultaneously turned on according to the j-th emission control signal EMj received through the j-th emission control line ECLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be transferred to the light-emitting element ED through the sixth transistor T6 after being compensated by the first transistor T1 connected via the diode.

[0101] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 transmitting a second initialization voltage VAINT, a second electrode connected to the second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level lower than or equal to the first initialization voltage VINT.

[0102] One end of the first capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the first capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light-emitting element ED may be connected to the second driving voltage line VL2 that transmits the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the first driving voltage ELVDD.

[0103] Figure 5 It is a plan view of a portion of a display area of a display panel according to an embodiment of the present invention. Figure 5The plane of the display module is shown when it is viewed from the display surface of the display module, and the arrangement of the light-emitting areas is shown.

[0104] Reference Figure 5 The display area DA may include a light emitting area PXA including first to third light emitting areas PXA-B, PXA-G, and PXA-R, and a peripheral area NPXA surrounding the first to third light emitting areas PXA-B, PXA-G, and PXA-R. The first to third light emitting areas PXA-B, PXA-G, and PXA-R may be connected to the light emitting elements ED1, ED2, and ED3 (refer to FIG. Figure 6b ) corresponding to the area of light provided by the first to third light emitting areas PXA-B, PXA-G, PXA-R according to the direction of the display module DM (refer to Figure 2 ) is divided by the color of the light emitted from the outside.

[0105] The first to third light-emitting regions PXA-B, PXA-G, and PXA-R can respectively provide first to third colors of light having different colors. For example, the first color of light can be blue, the second color of light can be green, and the third color of light can be red. However, the examples of the first to third colors of light are not necessarily limited to these examples.

[0106] Each of the first to third light-emitting regions PXA-B, PXA-G, and PXA-R can be defined as a region where the upper surface of the anode is exposed through a light-emitting opening, which will be described later. The peripheral region NPXA can define the boundaries of the first to third light-emitting regions PXA-B, PXA-G, and PXA-R and prevent color mixing between the first to third light-emitting regions PXA-B, PXA-G, and PXA-R.

[0107] Each of the first to third light-emitting regions PXA-B, PXA-G, and PXA-R may be provided in a plurality and arranged in a predetermined, repetitive manner within the display area DA. For example, the first light-emitting regions PXA-B and the third light-emitting regions PXA-R may be arranged alternately along the first direction DR1 to form a "first group." The second light-emitting regions PXA-G may be arranged along the first direction DR1 to form a "second group." Each of the "first group" and the "second group" may be provided in a plurality and may be arranged alternately along the second direction DR2.

[0108] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-B or one third light emitting region PXA-R in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first and second directions DR1 and DR2.

[0109] on the other hand, Figure 5The arrangement of the first to third light emitting regions PXA-B, PXA-G, and PXA-R is shown as an example, but is not limited thereto and can be arranged in various forms. In one embodiment, the first to third light emitting regions PXA-B, PXA-G, and PXA-R can be arranged as follows: Figure 5 Shown with PENTILET Alternatively, the first to third light emitting regions PXA-B, PXA-G, and PXA-R may also have a stripe arrangement or a diamond arrangement. ) arrangement format.

[0110] The first to third light emitting regions PXA-B, PXA-G, and PXA-R may have various shapes on a plane, such as polygonal, circular, or elliptical shapes. Figure 5 The first and third light emitting regions PXA-B and PXA-R having a quadrangular shape (or a diamond shape) on a plane and the second light emitting region PXA-G having an octagonal shape are exemplarily shown.

[0111] The first to third light emitting regions PXA-B, PXA-G, and PXA-R may have the same shape as each other on a plane, or at least a portion thereof may have different shapes from each other. Figure 5 The first and third light emitting regions PXA-B and PXA-R having the same shape as each other on a plane and the second light emitting region PXA-G having a shape different from the first and third light emitting regions PXA-B and PXA-R are exemplarily shown.

[0112] At least a portion of the first to third light-emitting regions PXA-B, PXA-G, and PXA-R may have different areas on a plane. In one embodiment, the area of the first light-emitting region PXA-B emitting blue light may be larger than the area of the second light-emitting region PXA-G emitting green light, and larger than the area of the third light-emitting region PXA-R emitting red light. However, the size relationship between the first to third light-emitting regions PXA-B, PXA-G, and PXA-R according to the light-emitting color is not limited to this. Depending on the display module DM (refer to Figure 2 ) can be designed in various ways. In addition, without limitation thereto, the first to third light emitting regions PXA-B, PXA-G, and PXA-R may also have the same area as each other on a plane.

[0113] According to an embodiment of the present invention, the display panel DP (referring to Figure 2) may include a first encapsulation pattern TFE-PT1 and a second encapsulation pattern TFE-PT2 covering the first to third light emitting regions PXA-B, PXA-G, and PXA-R.

[0114] The first encapsulation pattern TFE-PT1 and the second encapsulation pattern TFE-PT2 may be spaced apart from each other on a plane. The first encapsulation pattern TFE-PT1 may cover the first light emitting layer EL1 (see FIG. Figure 6b ) of the first light emitting opening OP1-E (refer to Figure 6b The second packaging pattern TFE-PT2 may cover and be configured with a second light emitting layer EL2 (refer to Figure 6b ) of the second light emitting opening OP2-E (refer to Figure 6b ) and is provided with a third light emitting layer EL3 (refer to Figure 6b ) of the third light emitting opening OP3-E (refer to Figure 6b The first encapsulation pattern TFE-PT1 may not overlap with the second light emitting region PXA-G and the third light emitting region PXA-R on a plane, and the second encapsulation pattern TFE-PT2 may not overlap with the first light emitting region PXA-B on a plane.

[0115] As described later, the first encapsulation pattern TFE-PT1 and the second encapsulation pattern TFE-PT2 can be formed in different process steps and separated from each other. However, this is not limited to this. The first encapsulation pattern TFE-PT1 and the second encapsulation pattern TFE-PT2 can be formed separately in the same process step and are not limited to any one embodiment.

[0116] The display module DM of the present invention (refer to Figure 2 The shapes, areas, and arrangements of the first to third light-emitting regions PXA-B, PXA-G, and PXA-R may be determined based on the color of the emitted light or the display module DM (see Figure 2 ) size, structure and various designs are made, not limited to Figure 5 The embodiment shown.

[0117] Figure 6a as well as Figure 6b FIG. 1 is a partial cross-sectional view of a display panel according to an embodiment of the present invention. Figure 6a The display area DA is shown in an enlarged manner (see Figure 5 ) within a light emitting area PXA. Figure 6b A first light emitting region PXA-B, a second light emitting region PXA-G, and a third light emitting region PXA-R are shown in an enlarged manner. Figure 6a as well as Figure 6b When, refer to Figure 5 , and descriptions of the same reference numerals will be omitted.

[0118] Reference Figure 6a as well as Figure 6b The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and an encapsulation layer TFE.

[0119] The display panel DP may include multiple insulating layers, as well as semiconductor patterns, conductive patterns, signal lines, and the like. These insulating layers, semiconductor layers, and conductive layers are formed by coating, vapor deposition, and other methods. Subsequently, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. This method allows the semiconductor patterns, conductive patterns, signal lines, and the like included in the circuit element layer DP-CL and the display element layer DP-OLED to be formed.

[0120] The circuit element layer DP-CL may be disposed on the base layer BL and may include a buffer layer BFL, a transistor TR1 , a signal transfer region SCL, first to fifth insulating layers 10 , 20 , 30 , 40 , 50 , an electrode EE, and a plurality of connection electrodes CNE1 and CNE2 .

[0121] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may enhance the bonding strength between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0122] A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, but is not limited thereto. The semiconductor pattern may also include amorphous silicon or metal oxide. Figure 6a Only a portion of the semiconductor pattern is shown, and in the plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see Figure 5 ) can further be configured with a semiconductor pattern. The semiconductor pattern can span multiple light emitting regions PXA-R, PXA-G, PXA-B (refer to Figure 5 ) are arranged in a specific pattern. The electrical properties of the semiconductor pattern vary depending on whether it is doped or not. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a first region doped with a P-type dopant.

[0123] The first region has a greater conductivity than the second region and essentially functions as an electrode or signal line. The second region can essentially correspond to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern can be the active region of the transistor, another portion can be the source or drain of the transistor, and yet another portion can be a conductive region.

[0124] The source S, active area A, and drain D of the transistor TR1 may be formed from a semiconductor pattern. Figure 6a A portion of a signal transmission region SCL formed from a semiconductor pattern is shown in . Although not shown separately, the signal transmission region SCL may be connected to the drain D of the transistor TR1 in a planar manner.

[0125] The first to fifth insulating layers 10 to 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10 to 50 may be inorganic layers or organic layers.

[0126] A first insulating layer 10 may be disposed on the buffer layer BFL. A gate G may be disposed on the first insulating layer 10. A second insulating layer 20 may be disposed on the first insulating layer 10 and cover the gate G. An electrode EE may be disposed on the second insulating layer 20. A third insulating layer 30 may be disposed on the second insulating layer 20 and cover the electrode EE.

[0127] A first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL via a contact hole CNT-1 that penetrates the first through third insulating layers 10 to 30. A fourth insulating layer 40 may be disposed on the third insulating layer 30 and cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0128] A second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 that penetrates the fourth insulating layer 40. A fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0129] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL and may include a light emitting element ED, a pixel definition layer PDL, a partition wall PW, and a dummy pattern DMP.

[0130] In the present invention, the light emitting element ED may include an anode AE (or a first electrode), a conductive pattern, a light emitting layer EL, and a cathode CE (or a second electrode).

[0131] The anode AE can be arranged on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE can be conductive. For example, as long as the anode AE has conductivity such as metal, transparent conductive oxide (TCO), or a conductive polymer, it can be formed from various materials. The anode AE can also be configured as a single layer or as a multilayer. In one embodiment, the anode AE can be configured as three layers including indium oxide (ITO), silver (Ag), and indium oxide (ITO).

[0132] The anode AE can be connected to the second connection electrode CNE2 through the connection contact hole CNT-3 defined by penetrating the fifth insulating layer 50. Therefore, the anode AE can be electrically connected to the signal transmission region SCL and corresponding circuit elements through the first and second connection electrodes CNE1 and CNE2.

[0133] According to an embodiment of the present invention, the display panel DP may further include sacrificial patterns SP (i.e., sacrificial patterns SP1, SP2, and SP3). The sacrificial patterns SP1, SP2, and SP3 may be disposed above the anode AE. The sacrificial patterns SP1, SP2, and SP3 may define a sacrificial opening OP-S that exposes a portion of the top surface of the anode AE. The sacrificial patterns SP1, SP2, and SP3 may include an amorphous transparent conductive oxide.

[0134] The pixel defining layer (PDL) may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The pixel defining layer (PDL) may define a plurality of light-emitting openings (OP-E) (i.e., light-emitting openings OP1-E, OP2-E, and OP3-E). The light-emitting openings OP1-E, OP2-E, and OP3-E may overlap with the anode AE, respectively. The pixel defining layer (PDL) may expose at least a portion of the anode AE through the light-emitting openings OP1-E, OP2-E, and OP3-E.

[0135] Furthermore, the light-emitting openings OP1-E, OP2-E, and OP3-E may correspond to the sacrificial openings OP-S of the sacrificial patterns SP1, SP2, and SP3. According to this embodiment, the top surface of the anode AE may be separated from the pixel definition layer PDL in a cross-section via the sacrificial patterns SP1, SP2, and SP3. This protects the anode AE from damage during the formation process of the light-emitting openings OP1-E, OP2-E, and OP3-E.

[0136] The width of the light-emitting openings OP1-E, OP2-E, and OP3-E in one direction may be smaller than the width of the sacrificial opening OP-S in one direction. In this specification, one direction may refer to a direction perpendicular to the thickness direction of the display panel DP (i.e., the third direction DR3). The inner side surface of the pixel defining film PDL that defines the light-emitting openings OP1-E, OP2-E, and OP3-E may be closer to the center of the anode AE than the inner side surface of the sacrificial pattern SP1, SP2, and SP3 that defines the sacrificial opening OP-S. However, this is not limited to the above. The inner side surface of the sacrificial pattern SP1, SP2, and SP3 that defines the sacrificial opening OP-S may also be substantially aligned with the inner side surface of the pixel defining film PDL that defines the corresponding light-emitting openings OP1-E, OP2-E, and OP3-E. In this case, the light-emitting area PXA may also be regarded as the area of the anode AE exposed by the corresponding sacrificial opening OP-S. On the other hand, in one embodiment of the present invention, the sacrificial patterns SP1, SP2, and SP3 may also be omitted.

[0137] The pixel definition layer PDL may include an inorganic insulating material. For example, the pixel definition layer PDL may include silicon nitride (SiN x The pixel defining layer PDL may be disposed between the anode AE and the partition wall PW to prevent the anode AE and the partition wall PW from being electrically connected to each other.

[0138] The partition wall PW may be disposed on the pixel definition layer PDL. The partition wall PW may include a plurality of partition wall openings OP-P (i.e., partition wall openings OP1-P, OP2-P, and OP3-P). The partition wall openings OP1-P, OP2-P, and OP3-P may correspond to the light emitting openings OP1-E, OP2-E, and OP3-E and may expose at least a portion of the anode AE.

[0139] The partition wall PW may have an undercut shape in cross section. The partition wall PW may include a plurality of sequentially stacked layers, at least one of which may be recessed compared to adjacent stacked layers, thereby including a plurality of tip portions TP (ie, tip portions TP1, TP2, TP3).

[0140] In this embodiment, the partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the pixel definition layer PDL, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. Figure 6aAs shown, the thickness of the first partition wall layer L1 can be greater than the thickness of the second partition wall layer L2, but is not limited to this. The drawings only illustrate the configuration of the partition wall PW with the first partition wall layer L1 and the second partition wall layer L2, but are not limited to this. A third partition wall layer can be configured on the second partition wall layer L2, and this is not limited to any one embodiment. Furthermore, the thickness of the third partition wall layer can be greater than the thickness of the second partition wall layer L2, but is not limited to this.

[0141] The first partition layer L1 may be conductive. The first partition layer L1 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The metal nitride may include titanium nitride (TiN). The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (IGZO), or aluminum zinc oxide (Aluminum Zinc Oxide).

[0142] The second partition wall layer L2 is disposed on the first partition wall layer L1. The second partition wall layer L2 may include a material having an etching selectivity ratio with the first partition wall layer L1. As an example, the reactivity of the second partition wall layer L2 may be lower than that of the first partition wall layer L1.

[0143] In this embodiment, the first partition wall layer L1 may be recessed relative to the second partition wall layer L2 relative to the light emitting region PXA. That is, the first partition wall layer L1 may be undercut relative to the second partition wall layer L2. The portion of the second partition wall layer L2 that protrudes from the first partition wall layer L1 toward the light emitting region PXA may define the tip portions TP1, TP2, and TP3 within the partition wall PW.

[0144] The second partition layer L2 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The metal nitride may include titanium nitride (TiN). The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (IGZO), or aluminum zinc oxide (Aluminum Zinc Oxide).

[0145] Alternatively, in another embodiment of the present invention, the second partition layer L2 may include an insulating material. For example, the second partition layer L2 may include an inorganic insulating material, such as silicon nitride (SiN x ) or silicon oxide (SiO x On the other hand, this is an exemplary case, and in the partition wall PW according to an embodiment of the present invention, the second partition wall layer L2 may be omitted.

[0146] In this embodiment, the second inner side surface SL2 of the second partition wall layer L2 may be closer to the center of the anode AE than the first inner side surface SL1 of the first partition wall layer L1. In other words, the first inner side surface SL1 of the first partition wall layer L1 may be recessed relative to the second inner side surface SL2 of the second partition wall layer L2 in a direction away from the center of the anode AE. Thus, the second partition wall layer L2 may include a lower surface exposed by the first partition wall layer L1.

[0147] The partition wall PW may have an undercut shape in cross section. As previously described, the undercut shape of the partition wall PW can be defined by a step between the first inner side surface SL1 of the first partition wall layer L1 and the second inner side surface SL2 of the second partition wall layer L2. However, the cross-sectional shape of the partition wall PW is not limited thereto and may have various shapes, such as an inverted cone and an overhang, and is not limited to any one embodiment.

[0148] exist Figure 6a In the example, the first inner side surface SL1 of the first partition wall layer L1 and the second inner side surface SL2 of the second partition wall layer L2 are each perpendicular to the upper surface of the fifth insulating layer 50, but the present invention is not limited thereto. Figure 6b In the figure, the first inner side surface SL1 of the first partition wall layer L1 is perpendicular to the upper surface of the fifth insulating layer 50 , and the second inner side surface SL2 of the second partition wall layer L2 is inclined with respect to the upper surface of the fifth insulating layer 50 .

[0149] The light-emitting layer EL can be disposed on the anode AE. The light-emitting layer EL can be patterned by defining the tip portions TP1, TP2, and TP3 of the partition wall PW. At least a portion of the light-emitting layer EL can be disposed within the light-emitting openings OP1-E, OP2-E, and OP3-E. Alternatively, the light-emitting layer EL can be disposed entirely within the light-emitting openings OP1-E, OP2-E, and OP3-E. The light-emitting layer EL can be disposed not only within the light-emitting openings OP1-E, OP2-E, and OP3-E but also within the partition wall openings OP1-P, OP2-P, and OP3-P. In an embodiment including sacrificial patterns SP1, SP2, and SP3, the light-emitting layer EL can also be disposed within the sacrificial opening OP-S.

[0150] The light-emitting layer EL may include a light-emitting substance. A hole injection layer (HIL) and a hole transport layer (HTL) may be disposed between the light-emitting layer EL and the anode AE. An electron transport layer (ETL) and an electron injection layer (EIL) may be disposed above the light-emitting layer EL.

[0151] Reference Figure 6b The light-emitting layer EL may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3. The first light-emitting layer EL1 may be arranged in the first partition wall opening OP1-P, the second light-emitting layer EL2 may be arranged in the second partition wall opening OP2-P, and the third light-emitting layer EL3 may be arranged in the third partition wall opening OP3-P.

[0152] The first light-emitting layer EL1 may include a first light-emitting substance that generates light of a first color, the second light-emitting layer EL2 may include a second light-emitting substance that generates light of a second color, and the third light-emitting layer EL3 may include a third light-emitting substance that generates light of a third color. For example, the first color may be blue, and the second and third colors may be different colors of green and red, respectively.

[0153] According to one embodiment of the present invention, the area of the first light-emitting layer EL1 in contact with the partition wall PW and the area of the second light-emitting layer EL2 in contact with the partition wall PW may be different from each other. The area of the second light-emitting layer EL2 in contact with the partition wall PW and the area of the third light-emitting layer EL3 in contact with the partition wall PW may be substantially the same.

[0154] In addition, the cross-sectional shape of the portion of the first light-emitting layer EL1 in contact with the partition wall PW and the cross-sectional shape of the portion of the second light-emitting layer EL2 in contact with the partition wall PW may be different from each other. The cross-sectional shape of the portion of the second light-emitting layer EL2 in contact with the partition wall PW and the cross-sectional shape of the portion of the third light-emitting layer EL3 in contact with the partition wall PW may be substantially the same.

[0155] The cathode CE can be disposed on the light-emitting layer EL. The cathode CE can be patterned by defining the tip portions TP1, TP2, and TP3 of the partition wall PW. At least a portion of the cathode CE can be disposed within the partition wall openings OP1-P, OP2-P, and OP3-P. In one embodiment of the present invention, depending on the thickness of the light-emitting layer EL or the thickness of the pixel definition layer PDL, a portion of the cathode CE can also be disposed within the light-emitting openings OP1-E, OP2-E, and OP3-E.

[0156] The cathode CE may be conductive, and may be made of various materials, such as metal, transparent conductive oxide (TCO), or conductive polymer, as long as the cathode CE is conductive.

[0157] The cathode CE may include a first cathode CE1, a second cathode CE2, and a third cathode CE3. The first cathode CE1 may be disposed in the first partition wall opening OP1-P, the second cathode CE2 may be disposed in the second partition wall opening OP2-P, and the third cathode CE3 may be disposed in the third partition wall opening OP3-P.

[0158] Refer again Figure 6b The areas of the first cathode CE1, the second cathode CE2, and the third cathode CE3 in contact with the partition wall PW may be substantially the same. By setting the areas of the first to third cathodes CE1 to CE3 in contact with the partition wall PW to be substantially the same, the reliability of the electrical connection and the ease of signal transmission can be ensured.

[0159] However, the cross-sectional shapes of the first cathode CE1 and the second cathode CE2 may be different. The cross-sectional shapes of the second cathode CE2 and the third cathode CE3 may be substantially the same, and are not limited to any one embodiment.

[0160] According to one embodiment of the present invention, the display panel DP may further include a capping pattern. The capping pattern may be disposed on the cathode CE. The capping pattern may be patterned by the tip portions TP1, TP2, and TP3 defined by the partition walls PW. At least a portion of the capping pattern may be disposed within the partition wall openings OP1-P, OP2-P, and OP3-P.

[0161] The dummy pattern DMP may be disposed on the partition wall PW. The dummy pattern DMP may include a first dummy pattern DMP1, a second dummy pattern DMP2, and a third dummy pattern DMP3.

[0162] The first dummy pattern DMP1 may include an organic material. For example, the first dummy pattern DMP1 may include the same material as the first light-emitting layer EL1. The first dummy pattern DMP1 may be formed simultaneously with the first light-emitting layer EL1 through a single process and separated from the first light-emitting layer EL1 by the undercut shape of the partition wall PW.

[0163] The second dummy pattern DMP2 may include a conductive material. For example, the second dummy pattern DMP2 may include the same material as the first cathode CE1. The second dummy pattern DMP2 may be formed simultaneously with the first cathode CE1 through a single process and separated from the first cathode CE1 by the undercut shape of the partition wall PW.

[0164] The third dummy pattern DMP3 may include a conductive material. For example, the third dummy pattern DMP3 may include the same material as the second cathode CE2 and / or the third cathode CE3. The third dummy pattern DMP3 may be formed simultaneously with the second cathode CE2 and / or the third cathode CE3 through a single process and may be separated from the second cathode CE2 and / or the third cathode CE3 by the undercut shape of the partition wall PW.

[0165] The encapsulation layer TFE may be disposed on the display element layer DP-OLED and may include a first encapsulation layer TFE1 , a second encapsulation layer TFE2 , and a third encapsulation layer TFE3 .

[0166] The first encapsulation layer TFE1 may cover the light emitting element ED. Specifically, the first encapsulation layer TFE1 may cover the cathode CE. In one embodiment, the first encapsulation layer TFE1 may also cover the capping pattern configured on the cathode CE.

[0167] Continue to refer to Figure 6bA portion of the first encapsulation layer TFE1 may be disposed within the light-emitting openings OP1-E, OP2-E, and OP3-E, as well as the adjacent wall openings OP1-P, OP2-P, and OP3-P. The first encapsulation layer TFE1 may include a first encapsulation pattern TFE-PT1 and a second encapsulation pattern TFE-PT2. The first encapsulation pattern TFE-PT1 may cover the first adjacent wall opening OP1-P, and the second encapsulation pattern TFE-PT2 may cover the second adjacent wall opening OP2-P and the third adjacent wall opening OP3-P. On a plane, the first encapsulation pattern TFE-PT1 and the second encapsulation pattern TFE-PT2 may be separated from each other. As an example, the first encapsulation layer TFE1 may include an inorganic substance.

[0168] The second encapsulation layer TFE2 may cover the first encapsulation layer TFE1. The second encapsulation layer TFE2 may also be disposed between the first encapsulation pattern TFE-PT1 and the second encapsulation pattern TFE-PT2. The second encapsulation layer TFE2 may provide a flat upper surface. The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2. As an example, the second encapsulation layer TFE2 may include an organic material, and the third encapsulation layer TFE3 may include an inorganic material.

[0169] The first encapsulation layer TFE1 and the third encapsulation layer TFE3 can protect the display element layer DP-OLED from moisture / oxygen, and the second encapsulation layer TFE2 can protect the display element layer DP-OLED from foreign matter.

[0170] Figure 7a as well as Figure 7b 1 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention. Figure 7a It is magnified Figure 6b An enlarged view of the F7A section, Figure 7b It is magnified Figure 7a Magnified view of the F7B section.

[0171] Reference Figure 7a as well as Figure 7b According to an embodiment of the present invention, the first light emitting element ED1 may include a first anode AE1, a first light emitting layer EL1 and a first cathode CE1.

[0172] The first light-emitting layer EL1 may include a 1-1 light-emitting layer portion EL1-P1 and a 1-2 light-emitting layer portion EL1-P2. The 1-1 light-emitting layer portion EL1-P1 may be disposed on the first anode AE1 and include an upper surface EL1-US1 located at a first height H1 from an upper surface BL-US of the base layer BL. The 1-2 light-emitting layer portion EL1-P2 may be disposed on the pixel defining layer PDL and include an upper surface EL1-US2 located between the first height H1 and a third height H3 higher than the first height H1. The 1-2 light-emitting layer portion EL1-P2 may be disposed adjacent to the partition wall PW relative to the 1-1 light-emitting layer portion EL1-P1.

[0173] According to an embodiment of the present invention, the height of the upper surface EL1-US2 of the 1-2 light emitting layer portion EL1-P2 may increase from the upper surface BL-US of the base layer BL closer to the partition wall PW. Specifically, the second height H2 may increase closer to the partition wall PW.

[0174] As described above, the cross-sectional shapes of the 1-1 light-emitting layer portion EL1-P1 and the 1-2 light-emitting layer portion EL1-P2 of the first light-emitting layer EL1 may be the same as those of the second light-emitting layer EL2 (see FIG. Figure 6b ) and the third light-emitting layer EL3 (refer to Figure 6b )different.

[0175] The first light-emitting layer EL1 may include a first light-emitting substance that generates blue light. The first light-emitting substance may be deposited in the first partition wall opening OP1-P by a thermal evaporation process, as described below. The thermal evaporation process may form the first light-emitting layer EL1 into a 1-2 light-emitting layer portion EL1-P2 including an upper surface EL1-US2 disposed at a position higher than the upper surface EL1-US1 of the 1-1 light-emitting layer portion EL1-P1.

[0176] The first cathode CE1 may include a 1-1 cathode portion CE1-P1 and a 1-2 cathode portion CE1-P2. The 1-1 cathode portion CE1-P1 may be disposed on the first light-emitting layer EL1 and include an upper surface CE1-US1 located at a second height H2 from an upper surface BL-US of the base layer. The 1-2 cathode portion CE1-P2 may be disposed on the first light-emitting layer EL1 and include an upper surface CE1-US2 located between the second height H2 and a fourth height H4 higher than the second height H2 from an upper surface BL-US of the base layer. The 1-2 cathode portion CE1-P2 may be disposed adjacent to the partition wall PW relative to the 1-1 cathode portion CE1-P1.

[0177] According to an embodiment of the present invention, the height of the upper surface CE1-US2 of the 1-2 cathode portion CE1-P2 may increase from the upper surface BL-US of the base layer BL closer to the partition wall PW. Specifically, the fourth height H4 may increase closer to the partition wall PW.

[0178] The cross-sectional shape of the first cathode CE1 may be the same as that of the second cathode CE2 (see Figure 6b ) and the third cathode CE3 (refer to Figure 6b ) is different, but the area CTA1 of the first cathode CE1 in contact with the partition wall PW may be the same as the area CTA2 of the second cathode CE2 in contact with the partition wall PW (refer to Figure 8b ) and the contact area between the third cathode CE3 and the partition wall PW are substantially the same.

[0179] Figure 8a as well as Figure 8b 1 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention. Figure 8a It is magnified Figure 6b An enlarged view of the F8A part, Figure 8b It is magnified Figure 8a Magnified view of the F8B portion.

[0180] Reference Figure 8a as well as Figure 8b According to an embodiment of the present invention, the second light emitting element ED2 may include a second anode AE2, a second light emitting layer EL2 and a second cathode CE2.

[0181] The second light-emitting layer EL2 may include a 2-1st light-emitting layer portion EL2-P1 and a 2-2nd light-emitting layer portion EL2-P2. The 2-1st light-emitting layer portion EL2-P1 may be disposed on the second anode AE2 and include an upper surface EL2-US1 located at a predetermined height from the upper surface BL-US of the base layer BL. The 2-2nd light-emitting layer portion EL2-P2 may include an upper surface EL2-US2 disposed on the pixel defining layer PDL. The 2-2nd light-emitting layer portion EL2-P2 may be disposed adjacent to the partition wall PW relative to the 2-1st light-emitting layer portion EL2-P1. In this case, the heights of the 2-1st light-emitting layer portion EL2-P1 and the upper surface BL-US of the base layer BL adjacent to the 2-2nd light-emitting layer portion EL2-P2 may be substantially the same. That is, the upper surface EL2-US1 of the 2-1st light-emitting layer portion EL2-P1 and the upper surface EL2-US2 of the 2-2nd light-emitting layer portion EL2-P2 may refer to the same surface having substantially the same height H1'.

[0182] According to one embodiment of the present invention, the height H1' of the top surface EL2-US1 of the 2-2 luminescent layer portion EL2-P2 can vary from the top surface BL-US of the base layer BL closer to the partition wall PW. This can vary depending on the properties of the second luminescent material constituting the second luminescent layer EL2 and is not limited to any one embodiment.

[0183] The second light emitting layer EL2 may include a second light emitting substance that generates green or red. The second light emitting substance may be arranged in the second partition wall opening by an inkjet process as described later (see Figure 6b According to the inkjet process, the second light emitting layer EL2 may be formed into a 2-2 light emitting layer portion EL2-P2 including an upper surface EL2-US2 disposed at substantially the same position as the upper surface EL2-US1 of the 2-1 light emitting layer portion EL2-P1.

[0184] As mentioned above, the first light emitting layer EL1 (refer to Figure 7b ) of the 1-1 light-emitting layer portion EL1-P1 (refer to Figure 7b ) and the 1st-2nd light emitting layer part EL1-P2 (refer to Figure 7b ) may be different from the cross-sectional shapes of the 2-1 light-emitting layer portion EL2-P1 and the 2-2 light-emitting layer portion EL2-P2 of the second light-emitting layer EL2.

[0185] The second cathode CE2 may include a 2-1 cathode portion CE2-P1 and a 2-2 cathode portion CE2-P2. The 2-1 cathode portion CE2-P1 may be disposed on the second light-emitting layer EL2 and include an upper surface CE2-US1 located at a second height H2' from an upper surface BL-US of the base layer BL. The 2-2 cathode portion CE2-P2 may be disposed on the second light-emitting layer EL2 and include an upper surface CE2-US2 located between a second height H2' and a third height H3' higher than the second height H2' from an upper surface BL-US of the base layer. The 2-2 cathode portion CE2-P2 may be disposed adjacent to the partition wall PW relative to the 2-1 cathode portion CE2-P1.

[0186] According to an embodiment of the present invention, the height of the top surface CE2-US2 of the 2-2 cathode portion CE2-P2 may increase from the top surface BL-US of the base layer BL as it becomes closer to the partition wall PW. In addition, the third height H3' may increase along with the partition wall PW.

[0187] The cross-sectional shape of the second cathode CE2 may be similar to that of the first cathode CE1 (see Figure 7b ) is different, the area CTA2 of the second cathode CE2 in contact with the partition wall PW may be the same as that of the first cathode CE1 (refer to Figure 7b ) and the contact area CTA1 of the next wall PW (refer to Figure 7b ) are substantially the same.

[0188] Figure 8a as well as Figure 8b The description is made for the second light emitting element ED2, but the same is applicable to the third light emitting element ED3 (see Figure 6b )'s structure and configuration relationship for each one.

[0189] Figures 9a to 9c 、 Figures 10a to 10i 1 is a cross-sectional view showing a portion of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 1a to 8b The structures described in and the same / similar structures are denoted by the same / similar reference numerals, and repeated descriptions are omitted.

[0190] According to one embodiment of the present invention, a display panel manufacturing method may include the steps of providing a preliminary display panel including: a base layer, an anode, and a preliminary pixel defining film; a step of forming a partition wall having a plurality of partition wall openings; a step of patterning the preliminary pixel defining film to form a pixel defining film having a light-emitting opening portion; and a step of forming a first light-emitting layer, a second light-emitting layer, a third light-emitting layer, a first cathode, a second cathode, and a third cathode.

[0191] In addition, a display panel manufacturing method according to an embodiment of the present invention may include: a step of forming a first encapsulation layer including a first encapsulation pattern covering the first light-emitting opening portion and a second encapsulation pattern covering the second light-emitting opening portion and the third light-emitting opening portion and separated from the first encapsulation pattern; and a step of forming a second encapsulation layer covering the first encapsulation layer.

[0192] Below, through Figures 9a to 10i , a method of forming the light emitting elements ED1 , ED2 , and ED3 , a first encapsulation layer TFE1 covering the light emitting elements ED1 , ED2 , and ED3 , and a second encapsulation layer TFE2 will be described.

[0193] Reference Figure 9a , may include the step of forming a preliminary photoresist layer PR-I on the first preliminary display panel DP-I1.

[0194] The first preliminary display panel DP-I1 provided in this embodiment may include a base layer BL, a circuit element layer DP-CL, first to third anodes AE1, AE2, AE3, first to third sacrificial patterns SP1, SP2, SP3, a preliminary pixel defining layer PDL-I and a preliminary conductive partition layer PW-I.

[0195] The circuit element layer DP-CL can be formed by forming an insulating layer, a semiconductor layer and a conductive layer by coating, evaporation, etc., and selectively patterning the insulating layer, the semiconductor layer and the conductive layer by photolithography and etching processes to form a common circuit element manufacturing process such as a semiconductor pattern, a conductive pattern and a signal line.

[0196] The anodes AE1, AE2, AE3 and the sacrificial patterns SP1, SP2, SP3 can be formed by the same patterning process. The preliminary pixel defining layer PDL-I can cover all of the anodes AE1, AE2, AE3 and the sacrificial patterns SP1, SP2, SP3.

[0197] The preliminary conductive partition layer PW-1 may include a first partition layer L1 and a second partition layer L2 disposed on the first partition layer L1. The first partition layer L1 may have a first conductivity and a first thickness, and the second partition layer L2 may have a second conductivity lower than the second conductivity and a second thickness thinner than the first thickness.

[0198] After forming a preliminary photoresist layer on the preliminary conductive barrier layer PW-I, the preliminary photoresist layer can be patterned using a photomask to form an initial photoresist layer PR-I. Through the patterning process, an initial opening OP-I1 can be formed in the preliminary photoresist layer PR-I to overlap with the first anode AE1.

[0199] Afterwards, refer to Figure 9b as well as Figure 9c , which may include forming a conductive partition wall having a first partition wall opening defined therein from a preliminary conductive partition wall layer through a first etching process.

[0200] First, if Figure 9b As shown, the first etching process may include the step of dry etching the first and second partition walls L1 and L2 using the initial photoresist layer PR-I as a mask, thereby forming a first preliminary partition wall opening OP1-PI in the preliminary conductive partition wall layer PW-I. The dry etching of the first etching process may be performed in an etching environment in which the etching selectivity between the first and second partition walls L1 and L2 is substantially the same. As a result, the inner side surface of the first partition wall layer L1 and the inner side surface of the second partition wall layer L2 defining the first preliminary partition wall opening OP1-PI may be substantially aligned.

[0201] Afterwards, if Figure 9cAs shown, the first etching process may include the step of wet etching the first and second partition wall layers L1 and L2 using the preliminary photoresist layer PR-I as a mask, thereby forming the first partition wall opening OP1-P from the first preliminary partition wall opening OP1-PI. Thus, the conductive partition wall PW can be formed from the preliminary conductive partition wall layer PW-I defining the first preliminary partition wall opening OP1-PI.

[0202] The wet etching process in the first etching process can be formed in an environment where the etching selectivity between the first and second partition walls L1 and L2 is large. As a result, the inner side surface of the conductive partition wall PW that defines the first partition wall opening OP1-P can have an undercut shape in cross section. Specifically, since the etching rate of the first partition wall layer L1 with respect to the etching solution is greater than the etching rate of the second partition wall layer L2, the first partition wall layer L1 can be mainly etched. As a result, the inner side surface of the first partition wall layer L1 can be formed to be more recessed inwardly than the inner side surface of the second partition wall layer L2. A pointed portion can be formed on the conductive partition wall PW by the portion of the second partition wall layer L2 that protrudes from the first partition wall layer L1.

[0203] In addition, the step of patterning the preliminary pixel defining layer PDL-I by a second etching process to form the pixel defining layer PDL defining the first light-emitting opening OP1-E may be included. The second etching process may be performed by dry etching and may use the preliminary photoresist layer PR-I and the conductive partition wall PW (e.g., the second partition wall layer L2) as masks.

[0204] In addition, the step of forming a first sacrificial opening OP1-S in the first sacrificial pattern SP1 by a third etching process according to the present embodiment in such a manner that at least a portion of the first anode AE1 is exposed may be included. The third etching process may be performed in a wet etching manner and may be performed using the initial photoresist layer PR-I and the pixel defining layer PDL defining the first light-emitting opening OP1-E as a mask. The first sacrificial pattern SP1 may include an azo compound. The first sacrificial pattern SP1 may be zinc oxide (ZnO) doped with aluminum (Al). x In this case, the content of aluminum (Al) may be greater than or equal to 2 at % and less than or equal to 5 at %. Alternatively, the first sacrificial pattern SP1 may be gallium zinc oxide (GZO).

[0205] The inner side surface of the first sacrificial pattern SP1 defining the first sacrificial opening OP1-S may be recessed inward relative to the inner side surface of the pixel defining layer PDL defining the first light-emitting opening OP1-E. However, the inner side surface of the first sacrificial pattern SP1 may be aligned with the inner side surface of the pixel defining layer PDL, as shown by way of example only and is not intended to be limiting.

[0206] The third etching process can be performed in an environment where the etching selectivity between the first sacrificial pattern SP1 and the first anode AE1 is large, thereby preventing the first anode AE1 from being etched together. That is, the first sacrificial pattern SP1, which has a higher etch rate than the first anode AE1, is arranged between the pixel defining layer PDL and the first anode AE1, thereby preventing the first anode AE1 from being etched together and damaged during the etching process. For example, the etch rate of the first sacrificial pattern SP1 including an azo compound can be 370 angstroms / sec, and the etch rate of the first partition layer L1 can be approximately 19 angstroms / sec. The etch rate of the first sacrificial pattern SP1 can be 18 to 30 times faster than the etch rate of the first partition layer L1. Therefore, etching loss of the partition wall PW can be reduced.

[0207] The third etching process may also be performed in an etching process separate from the second etching process, or may be performed in the same etching process as the second etching process.

[0208] Afterwards, according to this embodiment, the step of removing the initial photoresist layer PR-I may be included. In this specification, it can be considered that after the step of removing the initial photoresist layer PR-I, a second preliminary display panel DP-I2 (preliminary display panel) is provided. That is, the second preliminary display panel DP-I2 may include a base layer BL, a circuit element layer DP-CL, first to third anodes AE1, AE2, and AE3, a pixel defining layer PDL defining a first light-emitting opening OP1-E, and a conductive partition PW defining a first partition opening OP1-P.

[0209] According to one embodiment of the present invention, the second partition wall opening OP2-P and the third partition wall opening OP3-P can be formed after the first partition wall opening OP1-P is formed, using the same or similar process. Furthermore, the second light-emitting opening OP2-E and the third light-emitting opening OP3-E can be formed after the first light-emitting opening OP1-E is formed, using the same or similar process. However, this is not limiting. The second partition wall opening OP2-P and the third partition wall opening OP3-P can be formed simultaneously with the first partition wall opening OP1-P, and the second light-emitting opening OP2-E and the third light-emitting opening OP3-E can be formed simultaneously with the first light-emitting opening OP1-E. This is not limited to any one embodiment.

[0210] In addition, although the sacrificial patterns SP1 , SP2 , and SP3 are shown in this drawing, the sacrificial patterns SP1 , SP2 , and SP3 may be omitted, and the present invention is not limited to any one embodiment.

[0211] Reference Figures 10a to 10d The method for manufacturing a display panel according to an embodiment of the present invention may include forming a first light emitting layer EL1, forming a first cathode CE1, and forming a first encapsulation pattern TFE-PT1.

[0212] Reference Figure 10a The step of forming the first light emitting layer EL1 may include removing the initial photoresist layer PR-I (referring to Figure 9c ) on the second preliminary display panel DP-I2. The step of forming the first light-emitting pattern EL1-P can be performed by an evaporation process. In one embodiment, the step of forming the first light-emitting pattern EL1-P can be performed by a thermal evaporation process. As an example, it can be performed by a vacuum thermal evaporation process.

[0213] According to an embodiment of the present invention, before forming the first light emitting pattern EL1-P, a first lifting member LFT1 covering the second partition wall opening OP2-P and a portion of the partition wall PW may be formed. The first light emitting pattern EL1-P may be disposed on the first lifting member LFT1.

[0214] In the step of forming the first light emitting pattern EL1-P, the first light emitting pattern EL1-P may be separated by the tip TP1 formed at the partition wall PW, so that the first light emitting layer EL1 is disposed in the first light emitting opening OP1-E and the first partition wall opening OP1-P.

[0215] According to one embodiment of the present invention, the first light-emitting material ELM1 constituting the first light-emitting pattern EL1-P may be a light-emitting material that generates blue light. The step of forming the first light-emitting pattern EL1-P using the first light-emitting material ELM1 is performed by a thermal evaporation process other than an inkjet process, thereby improving the lifespan of the first light-emitting material ELM1. The first light-emitting material ELM1 is thermally evaporated to form the first light-emitting pattern EL1-P and the first light-emitting layer EL1, thereby forming the 1-1 light-emitting layer portion EL1-P1 (see FIG. 1-1). Figure 7b ) and the 1st-2nd light emitting layer part EL1-P2 (refer to Figure 7b ).

[0216] Reference Figure 10bThe step of forming the first cathode CE1 may include forming a first cathode pattern CEa on the first light emitting pattern EL1-P. The step of forming the first cathode pattern CEa may be performed by an evaporation process. As an example, the step of forming the first cathode pattern CEa may be performed by a sputtering process, but is not limited thereto.

[0217] In the step of forming the first cathode pattern CEa, the first cathode pattern CEa may be separated by the tip portion TP1 formed at the partition wall PW so as to be arranged in the first partition wall opening OP1 -P.

[0218] In addition, the step of forming the first encapsulation pattern TFE-PT1 may include the step of forming a first preliminary encapsulation pattern TFE-P1 on the first cathode pattern CEa. The first preliminary encapsulation pattern TFE-P1 may be formed by an evaporation process. In one embodiment, the first preliminary encapsulation pattern TFE-P1 may be formed by a chemical vapor deposition (CVD) process. The first preliminary encapsulation pattern TFE-P1 may be formed on the partition wall PW and the first cathode pattern CEa, and a portion of the first preliminary encapsulation pattern TFE-P1 may be formed inside the first partition wall opening OP1-P.

[0219] Specifically, Figure 10c It is magnified Figure 10b An enlarged view of the F10C.

[0220] Reference Figure 10c According to one embodiment of the present invention, the evaporation angle of the first cathode pattern CEa and the evaporation angle of the first light emitting pattern EL1-P may be different.

[0221] The first cathode pattern CEa can be deposited at a higher evaporation angle θ2 than the first light-emitting pattern EL1-P at a higher evaporation angle θ1. This allows the first-second cathode portion CE1-P2 to be formed in contact with the inner side surface L1-E of the first partition layer L1. As shown in the accompanying drawings, the first light-emitting pattern EL1-P can be deposited along a first evaporation direction line DML1 having a predetermined evaporation angle, and the first-second cathode portion CE1-P2 can be deposited along a second evaporation direction line DML2. This allows the first-second cathode portion CE1-P2 to be positioned above the second light-emitting portion EL1-P2 formed along the inner side surface L1-E of the first partition layer L1 in the first light-emitting pattern EL1-P. The first-second cathode portion CE1-P2 can then contact the inner side surface L1-E of the first partition layer L1 above the second light-emitting portion EL1-P2. This ensures the electrical reliability of the first cathode CE1, described later.

[0222] Reference Figure 10b as well as Figure 10d According to an embodiment of the present invention, the step of patterning the first preliminary encapsulation pattern TFE-P1 to form the first encapsulation pattern TFE-PT1 may be included.

[0223] In the step of patterning the first preliminary encapsulation pattern TFE-P1, the first lifting member LFT1, a portion of the first light emitting pattern EL1-P, a portion of the first cathode pattern CEa, and a portion of the first preliminary encapsulation pattern TFE-P1 may be removed. As an example, the first lifting member LFT1 may be removed, and a portion of the first light emitting pattern EL1-P, a portion of the first cathode pattern CEa, and a portion of the first preliminary encapsulation pattern TFE-P1 may be removed.

[0224] According to an embodiment of the present invention, after removing the first lifting member LFT1 , a step of grinding or processing the upper portion of the partition wall PW may be additionally performed, which is not limited to any one embodiment.

[0225] However, the display panel manufacturing method according to an embodiment of the present invention may not be limited to the patterning method of configuring the first lifting component LFT1 on the first adjacent wall opening OP1-P, the second adjacent wall opening OP2-P and the adjacent wall PW, and removing the first lifting component LFT1 while removing the first preliminary packaging pattern TFE-P1. In addition, an etching method may also be used, and it is not limited to any one embodiment.

[0226] Reference Figure 10e According to an embodiment of the present invention, a method for manufacturing a display panel may include the steps of forming a second light-emitting layer EL2 and a third light-emitting layer EL3.

[0227] In the step of forming the second light-emitting layer EL2 and the third light-emitting layer EL3, the second light-emitting layer EL2 and the third light-emitting layer EL3 can be formed on the second anode AE2 and the third anode AE3. In one embodiment, the step of forming the second light-emitting layer EL2 and the third light-emitting layer EL3 can be performed using an inkjet process. The inkjet unit IU can spray the second light-emitting material ELM2 and the third light-emitting material ELM3 on each of the second anode AE2 and the third anode AE3. In this case, the second light-emitting material ELM2 and the third light-emitting material ELM3 can be respectively accommodated in the second partition wall opening OP2-P and the third partition wall opening OP3-P.

[0228] In the step of forming the second light-emitting layer EL2 and the third light-emitting layer EL3, the respective tip portions TP2 and TP3 can prevent the second light-emitting material ELM2 and the third light-emitting material ELM3 from being separated from the second partition wall opening OP2-P and the third partition wall opening OP3-P, respectively.

[0229] The second light-emitting layer EL2 and the third light-emitting layer EL3 can be formed at the same time, but are not limited thereto. They can be formed in different steps through separate processes and are not limited to any one embodiment.

[0230] According to an embodiment of the present invention, the second light-emitting material ELM2 constituting the second light-emitting layer EL2 and the third light-emitting material ELM3 constituting the third light-emitting layer EL3 may be light-emitting materials that generate light of different colors, green or red.

[0231] The steps of forming the second light-emitting layer EL2 using the second light-emitting material ELM2 and the third light-emitting layer EL3 using the third light-emitting material ELM3 can be performed using an inkjet process rather than a thermal evaporation process. Compared to thermal evaporation, the use of an inkjet process may partially reduce the lifespan characteristics of the second and third light-emitting layers EL2 and EL3. However, the actual reduction in the lifespan characteristics of the second and third light-emitting layers EL2 and EL3 is not significant, and instead can increase process efficiency and save costs.

[0232] Reference Figure 10f The method for manufacturing a display panel according to an embodiment of the present invention may include the step of forming a second cathode pattern CEb.

[0233] The step of forming the second cathode pattern CEb may be performed by an evaporation process. As an example, the step of forming the second cathode pattern CEb may be performed by a sputtering process, but is not limited thereto.

[0234] In the step of forming the second cathode pattern CEb, the second cathode pattern CEb can be formed to be separated from the tip portions TP2 and TP3 of the partition wall PW, so as to be respectively arranged in the second partition wall opening OP2-P and the third partition wall opening OP3-P. The second cathode pattern CEb can be provided at a high evaporation incident angle relative to the second light emitting pattern and the third light emitting pattern, so that the second cathode pattern CEb is formed to contact the inner side surface of the first partition wall layer L1 (refer to FIG. Figure 10c L1-E).

[0235] According to an embodiment of the present invention, before forming the second cathode pattern CEb, a second lifting member LFT2 covering the first encapsulation pattern TFE-PT1 may be formed. The second cathode pattern CEb may be disposed on the second lifting member LFT2.

[0236] Reference Figure 10g According to an embodiment of the present invention, the method for manufacturing a display panel may include the step of forming a second preliminary encapsulation pattern TFE-P2.

[0237] The second preliminary encapsulation pattern TFE-P2 can be formed by an evaporation process. In one embodiment, the second preliminary encapsulation pattern TFE-P2 can be formed by a chemical vapor deposition process. The second preliminary encapsulation pattern TFE-P2 can be formed on the second cathode pattern CEb or the partition wall PW, and a portion of the second preliminary encapsulation pattern TFE-P2 can be formed inside the second partition wall opening OP2-P and the third partition wall opening OP3-P.

[0238] Reference Figure 10h According to an embodiment of the present invention, the method for manufacturing a display panel may include patterning a second preliminary encapsulation pattern TFE-P2 (referring to Figure 10g ) steps.

[0239] In the step of patterning the second preliminary encapsulation pattern TFE-P2, the second lifting member LFT2 (see FIG. 1 ) disposed on the first encapsulation pattern TFE-PT1 may be removed. Figure 10f ), the second cathode pattern CEb (refer to Figure 10f ) and a portion of the second preliminary packaging pattern TFE-P2 (refer to Figure 10g As an example, the second lifting member LFT2 (see Figure 10f ), the second cathode pattern CEb (refer to Figure 10f ) and a portion of the second preliminary packaging pattern TFE-P2 (refer to Figure 10g However, the display panel manufacturing method according to an embodiment of the present invention is not limited to configuring the second lifting component LFT2 on the first packaging pattern TFE-PT1 (refer to Figure 10f ) and remove the second lifting component LFT2 (refer to Figure 10f ) while removing the second cathode pattern CEb (refer to Figure 10f ) and the patterning method of the second preliminary packaging pattern TFE-P2, as shown in the figure, can borrow the patterning method that can separate or separate the first packaging pattern TFE-PT1 and the second packaging pattern TFE-PT2. As an example, the etching method can also be borrowed, and is not limited to any one embodiment.

[0240] Reference Figure 10i According to an embodiment of the present invention, the method for manufacturing a display panel may include the step of forming a second encapsulation layer TFE2.

[0241] The second encapsulation layer TFE2 may be formed on the first encapsulation layer TFE1. The second encapsulation layer TFE2 may cover the first and second encapsulation patterns TFE-PT1 and TFE-PT2, and the partition wall PW not covered by the first and second encapsulation patterns TFE-PT1 and TFE-PT2.

[0242] The second encapsulation layer TFE2 may be formed by applying an organic material in an inkjet manner, but is not limited thereto. The second encapsulation layer TFE2 may provide a planarized upper surface.

[0243] A third encapsulation layer may be formed on the second encapsulation layer TFE2. The third encapsulation layer may be formed by evaporating an inorganic substance, thereby forming a display panel DP.

[0244] Figures 11a to 11c It is a cross-sectional view showing a portion of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 11a to 11c Show and according to Figures 10a to 10i The method for manufacturing a display panel of an embodiment shown in FIG. 1 is different from the method for manufacturing a display panel of an embodiment shown in FIG. Figure 10i The structures described in and the same / similar structures are denoted by the same / similar reference numerals, and repeated descriptions are omitted.

[0245] Reference Figure 11a According to an embodiment of the present invention, the method for manufacturing a display panel may include the steps of forming a second light-emitting layer EL2 and a third light-emitting layer EL3.

[0246] With Figures 10a to 10i Unlike the above-mentioned embodiment, the second light-emitting layer EL2 and the third light-emitting layer EL3 may be formed before the first light-emitting layer EL1. The second light-emitting layer EL2 and the third light-emitting layer EL3 may be formed by an inkjet process.

[0247] At this time, the second light-emitting substance constituting the second light-emitting layer EL2 and the third light-emitting substance constituting the third light-emitting layer EL3 can be light-emitting substances that generate light of different colors, green or red.

[0248] Reference Figure 11b The display panel manufacturing method according to an embodiment of the present invention may include the steps of forming a second cathode CE2, a third cathode CE3, and a second encapsulation pattern TFE-PT2.

[0249] With Figures 10a to 10i Different from the aforementioned embodiment, the second cathode CE2, the third cathode CE3, and the second encapsulation pattern TFE-PT2 may be formed before the first cathode CE1 and the first encapsulation pattern TFE-PT1.

[0250] At this time, the second encapsulation pattern TFE-PT2 may be formed by using a lifting member, but is not limited thereto. The second encapsulation pattern TFE-PT2 may be patterned by an etching process, and is not limited to any one embodiment.

[0251] Reference Figure 11cThe display panel manufacturing method according to an embodiment of the present invention may include the step of forming a first encapsulation pattern TFE-PT1.

[0252] According to an embodiment of the present invention, after forming the second encapsulation pattern TFE-PT2, the first light emitting layer EL1, the first cathode CE1, and the first encapsulation pattern TFE-PT1 can be formed. The first encapsulation pattern TFE-PT1 is spaced apart from the second encapsulation pattern TFE-PT2 on the plane.

[0253] The first light emitting layer EL1 may be formed by thermal evaporation and patterning, the first cathode CE1 may be formed by sputtering and patterning, and the first encapsulation pattern TFE-PT1 may be formed by chemical vapor deposition and patterning, which is not limited to any one embodiment.

[0254] At this time, the first light-emitting substance constituting the first light-emitting layer EL1 may be a light-emitting substance that generates blue light.

[0255] At this time, the first encapsulation pattern TFE-PT1 may be formed by using a lifting member, but is not limited thereto. The first encapsulation pattern TFE-PT1 may be patterned by an etching process, and is not limited to any one embodiment.

[0256] While the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will appreciate that various modifications and variations may be made to the present invention without departing from the scope of the present invention and the technical scope as set forth in the appended claims. Therefore, the technical scope of the present invention is not limited to the details set forth in the specification but is determined by the claims.

Claims

1. A display panel, characterized in that: include: basal layer; a pixel defining film, disposed on the base layer and defining a plurality of light-emitting openings separated from each other; a partition wall disposed on the pixel defining film and defining a plurality of partition wall openings respectively overlapping with the light emitting openings, and having conductivity; a first light-emitting element disposed in a first light-emitting opening of the light-emitting openings, and including a first anode, a first light-emitting layer disposed on the first anode and formed of a light-emitting substance that generates light of a first color, and a first cathode disposed on the first light-emitting layer and connected to the partition wall; as well as a second light-emitting element, arranged in a second light-emitting opening in the light-emitting opening, and including a second anode, a second light-emitting layer arranged on the second anode and formed of a light-emitting material that generates light of a second color different from the first color, and a second cathode arranged on the second light-emitting layer and connected to the partition wall; An area of the first light-emitting layer in contact with the partition wall and an area of the second light-emitting layer in contact with the partition wall are different from each other.

2. The display panel according to claim 1, wherein: A cross-sectional shape of a portion of the first light-emitting layer in contact with the partition wall is different from a cross-sectional shape of a portion of the second light-emitting layer in contact with the partition wall.

3. The display panel according to claim 1, wherein: The first light-emitting layer includes: A first light emitting layer portion is disposed on the first anode and includes an upper surface located at a first height from an upper surface of the base layer; and The second light emitting layer portion is disposed on the pixel defining film and includes an upper portion located at a second height higher than the first height. The height of the upper surface of the second light-emitting layer portion increases from the upper surface of the base layer toward the partition wall.

4. The display panel according to claim 1, wherein: The second cathode comprises: a first cathode portion disposed on the second light emitting layer and including an upper surface located at a third height from an upper surface of the base layer; and a second cathode portion, disposed on the second light emitting layer, and including an upper portion located at a fourth height higher than the third height; The height of the upper surface of the second cathode portion increases from the upper surface of the base layer toward the partition wall.

5. The display panel according to claim 1, wherein: The first color is blue.

6. The display panel according to claim 1, wherein: The display panel further includes: a first encapsulation layer including a first encapsulation pattern covering the first light-emitting opening and a second encapsulation pattern spaced apart from the first encapsulation pattern and covering the second light-emitting opening; and The second packaging layer covers the first packaging layer.

7. The display panel according to claim 6, wherein: The display panel further includes: a third light-emitting element, disposed in a third light-emitting opening in the light-emitting opening, and including a third anode, a third light-emitting layer disposed on the third anode and formed of a light-emitting substance that generates light of a third color different from the first color, and a third cathode disposed on the third light-emitting layer and connected to the partition wall; The second color and the third color are respectively different colors of green or red.

8. The display panel according to claim 7, wherein: The second encapsulation pattern also covers the third light emitting element.

9. The display panel according to claim 7, wherein: A cross-sectional shape of a portion of the second light-emitting layer in contact with the partition wall is the same as a cross-sectional shape of a portion of the third light-emitting layer in contact with the partition wall.

10. A display panel, characterized in that: include: basal layer; a pixel defining film, disposed on the base layer and defining a plurality of light-emitting openings separated from each other; a partition wall disposed on the pixel defining film and defining a plurality of partition wall openings respectively overlapping with the light emitting openings, and having conductivity; a first light-emitting element disposed in a first light-emitting opening of the light-emitting openings, and including a first anode, a first light-emitting layer disposed on the first anode and formed of a light-emitting substance that generates light of a first color, and a first cathode disposed on the first light-emitting layer and connected to the partition wall; a second light-emitting element disposed in a second light-emitting opening of the light-emitting opening, comprising a second anode, a second light-emitting layer disposed on the second anode and formed of a light-emitting substance that generates light of a second color different from the first color, and a second cathode disposed on the second light-emitting layer and connected to the partition wall; a third light-emitting element disposed in a third light-emitting opening of the light-emitting opening, comprising a third anode, a third light-emitting layer disposed on the third anode and formed of a light-emitting substance that generates light of a third color different from the first color, and a third cathode disposed on the third light-emitting layer and connected to the partition wall; as well as The first encapsulation layer includes a first encapsulation pattern covering the first light emitting opening and a second encapsulation pattern separated from the first encapsulation pattern and covering the second light emitting opening and the third light emitting opening.

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