Composite wafer

Abstract

A composite wafer is provided that includes a first dielectric oxide layer on an upper surface of a disposal substrate. The composite wafer also includes a two-dimensional array of a plurality of plates of transfer material affixed to the first dielectric oxide layer and laterally separated from each other by a plurality of intersecting channels extending vertically from a plurality of planar upper surfaces of the plates of transfer material to an upper surface of the first dielectric oxide layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor technology, and in particular to a composite wafer. Background Art

[0002] A thin film transfer process can be used to provide a film-on-insulator substrate. The thin film transfer process can include bonding a donor wafer and an acceptor wafer. The donor wafer contains a thin film that is partially cut from the bulk wafer after wafer bonding. However, bonding two materials with mismatched thermal expansion coefficients can cause cracking of the bonded wafer during post-bonding annealing. Therefore, the post-bonding annealing temperature is limited due to the mismatch, which limits the bond strength between the transferred film and the insulator layer within the film-on-insulator substrate. Summary of the Invention

[0003] In some embodiments, a composite wafer is provided that includes: a first dielectric oxide layer disposed on an upper surface of a handling substrate; and a two-dimensional array of a plurality of transfer material plates attached to the first dielectric oxide layer and laterally separated from each other by a plurality of intersecting channels extending vertically from a plurality of planar upper surfaces of the transfer material plates to an upper surface of the first dielectric oxide layer.

[0004] In one embodiment, each of the plurality of intersecting channels has a variable lateral width that decreases with increasing vertical distance from a top surface of the first dielectric oxide layer.

[0005] In one embodiment, the invention further comprises a two-dimensional array of a plurality of dielectric oxide plates, sandwiched between the two-dimensional array of the plurality of transfer material plates and the first dielectric oxide layer.

[0006] In one embodiment, a two-dimensional array of the plurality of transfer material plates is in contact with the upper surface of the first dielectric oxide layer.

[0007] In one embodiment, a peripheral region exists on the upper surface of the first dielectric oxide layer surrounding the two-dimensional array of the plurality of transfer material plates, the peripheral region being free of any of the plurality of transfer material plates; and

[0008] The peripheral region has a lateral width greater than twice the width of each of the plurality of intersecting channels.

[0009] In some embodiments, a composite wafer is provided, comprising: a dielectric oxide layer located on an upper surface of a handling substrate; a plurality of dielectric oxide plates located on the upper surface of the dielectric oxide layer; and a plurality of transfer material plates correspondingly located on the upper surfaces of the dielectric oxide plates, wherein the dielectric oxide plates are in direct contact with the dielectric oxide layer and the transfer material plates.

[0010] In one embodiment, the plurality of transfer material plates are laterally separated from one another by a plurality of intersecting channels, and the plurality of dielectric oxide plates are laterally separated from one another by the plurality of intersecting channels.

[0011] In one embodiment, each of the plurality of intersecting channels extends from an upper surface of each of the plurality of transfer material plates to the upper surface of the dielectric oxide layer.

[0012] In one embodiment, each of the plurality of intersecting channels has two opposing tapered sidewalls.

[0013] In one embodiment, a distance between the plurality of opposed tapered sidewalls decreases as a vertical distance from the upper surface of the dielectric oxide layer increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figures 1A-1G Schematic diagrams of sequential vertical cross-sections illustrating a first embodiment structure during formation of a composite wafer according to an embodiment of the present disclosure.

[0015] Figure 1H Show Figure 1G Top view of the composite wafer.

[0016] Figures 2A-2C Schematic diagrams of sequential vertical cross-sections illustrating a second embodiment structure during formation of a composite wafer according to an embodiment of the present disclosure.

[0017] Figures 3A-3G Schematic diagrams of sequential vertical cross-sections illustrating a third embodiment structure during formation of a composite wafer according to an embodiment of the present disclosure.

[0018] Figures 4A-4C Schematic diagrams of sequential vertical cross-sections illustrating a fourth embodiment structure during formation of a composite wafer according to an embodiment of the present disclosure.

[0019] Figure 5A 、 5B 5D and 5D are sequential vertical cross-sectional views of the structure of the fifth embodiment during formation of a composite wafer according to an embodiment of the present disclosure.

[0020] Figure 5C Show Figure 5B A top view of the fifth structure.

[0021] Figure 5E Show Figure 5D Top view of the composite wafer.

[0022] Figure 6A 、 6C 6D and 6D are sequential vertical cross-sectional views of the sixth embodiment structure during composite wafer formation according to an embodiment of the present disclosure.

[0023] Figure 6B Show Figure 6A Top view of the donor wafer.

[0024] Figure 6E Show Figure 6D Top view of the composite wafer.

[0025] Figure 7A 、 7C 7D and 7D are sequential vertical cross-sectional views of the structure of the seventh embodiment during formation of a composite wafer according to an embodiment of the present disclosure.

[0026] Figure 7B Show Figure 7A Top view of the donor wafer.

[0027] Figure 7E Show Figure 7D Top view of the composite wafer.

[0028] Figure 8 A first flow chart illustrating process steps for forming a composite wafer according to an embodiment of the present disclosure.

[0029] Figure 9 A second flow chart illustrating process steps for forming a composite wafer according to an embodiment of the present disclosure.

[0030] Description of reference numerals:

[0031] 100: donor wafer

[0032] 105: Ion implantation layer

[0033] 108: Bearing layer

[0034] 109: Donor material layer

[0035] 110: Transfer material plate

[0036] 111: Intersecting grooves

[0037] 111': intersecting channels; intersecting transversely extending channels

[0038] 110L: Transfer material layer

[0039] 113: Horizontal notch

[0040] 117: Patterned etching mask layer 117

[0041] 120: Dielectric oxide board

[0042] 120L: Donor side dielectric oxide layer

[0043] 200: Acceptor wafer

[0044] 208: Disposal of base

[0045] 220: Acceptor side dielectric oxide layer

[0046] 300: Composite wafer

[0047] 810,820,830,840,910,920,930,940,950: Steps

[0048] hd1: first horizontal direction

[0049] hd2: second horizontal direction

[0050] α: taper angle DETAILED DESCRIPTION

[0051] The following disclosure provides many different embodiments or examples for implementing different characteristic components of the present invention. The following disclosure describes specific examples of each component and its arrangement in order to simplify the present disclosure. Of course, these are only examples and are not used to define the present invention. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which additional characteristic components can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat numbers and / or text in each different example. Repetition is for the purpose of simplicity and clarity, rather than to list and specify the relationship between the various embodiments and / or configurations discussed.

[0052] Spatially relative terms such as "below," "beneath," "below," "above," "upper," "top," and the like are used herein to facilitate the relationship of elements or features to other elements or features in the drawings shown in this specification. These spatially relative terms encompass not only the orientations shown in the drawings, but also various orientations of the device during use or operation. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative symbols used herein should be interpreted accordingly.

[0053] Various embodiments disclosed herein relate to composite wafers having transfer material plates and methods for forming the same. A donor wafer comprising a transfer material layer can be provided. The transfer material layer can be patterned into an array of transfer material plates by forming intersecting grooves. The lateral dimensions of the transfer material plates can be reduced relative to the lateral dimensions of the transfer material layer. The transfer material plates can be transferred to a recipient wafer to form a composite wafer comprising multiple transfer material plates, a dielectric oxide layer, and a disposal substrate. The dielectric oxide layer can be directly bonded to the multiple transfer material plates. Alternatively, the dielectric oxide plates can serve as an intermediate structure between the dielectric oxide layer and the multiple transfer material plates. The reduction in the lateral dimensions of the transfer material plates can reduce the risk of cracking at the bonding interface during the bonding process used to connect the multiple transfer material plates to the dielectric oxide layer. Thus, materials with a large mismatch relative to the material of the disposal substrate can be used for the transfer material plates without the risk of cracking during the wafer bonding process. Various aspects of the embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0054] Figures 1A-1G Schematic diagrams of sequential vertical cross-sections of a first embodiment structure during formation of a composite wafer 300 according to an embodiment of the present disclosure are shown.

[0055] Please refer to Figure 1A , a first embodiment structure may include a donor wafer 100 having a donor material layer 109. The donor wafer 100 may have a lateral dimension (e.g., diameter) in the range of 50 mm to 450 mm, however, smaller and larger lateral dimensions may also be used. The donor material layer 109 may have a thickness that provides sufficient mechanical strength to the donor wafer 100. For example, the thickness of the donor material layer 109 may be in the range of 100 microns to 2,000 microns, such as 200 microns to 1,000 microns. However, smaller and larger thicknesses may also be used. The donor material layer 109 includes and / or consists essentially of a material to be transferred to an upper portion of the acceptor wafer to provide a composite wafer. Therefore, the material of the donor material layer 109 is referred to herein as a transfer material.

[0056] The transfer material may comprise a semiconductor material, an insulating material, or a conductive material. Embodiments of the present disclosure may be used with any transfer material that can be directly bonded to a dielectric material within a recipient wafer, or in combination with another dielectric material that can be deposited on the transfer material and subsequently bonded to a dielectric material within a recipient wafer. Generally, the transfer material may be a high-quality, high-purity material, and may comprise a single crystal material. According to one aspect of the present disclosure, the transfer material may comprise a material having a large mismatch in thermal expansion coefficient relative to the material of a disposal substrate within a subsequently used recipient wafer.

[0057] In illustrative examples, the donor material layer 109 within the donor wafer 100 may include and / or consist essentially of a semiconductor material (e.g., silicon, germanium, or a silicon-germanium alloy) or a compound semiconductor material (e.g., a semiconductor metal oxide material). In one embodiment, the donor material layer 109 within the donor wafer 100 may include and / or consist essentially of a single crystalline semiconductor material, which may include single crystalline silicon, single crystalline germanium, a single crystalline silicon-germanium alloy, or a single crystalline compound semiconductor material. In one embodiment, the donor material layer 109 within the donor wafer 100 may include and / or consist essentially of a single crystalline compound semiconductor material, such as single crystalline lithium niobate (LiNbO 3 ), single crystalline lithium tantalate (LiTa O 3 ), crystalline zinc oxide, single crystalline titanium oxide, single crystalline indium tin oxide, single crystalline gallium oxide, single crystalline tin oxide, single crystalline tungsten trioxide, etc. In one embodiment, the donor material layer 109 in the donor wafer 100 may include and / or may consist essentially of the following materials: single crystal lithium niobate or single crystal lithium tantalate.

[0058] Please refer to Figure 1B , an ion implantation process may be performed to implant light element ions (e.g., hydrogen and / or helium) into the donor wafer 100. The kinetic energy of the ions implanted into the donor wafer 100 may be selected based on the target ion implantation depth and may be in the range of 50 keV to 500 keV, such as in the range of 100 keV to 400 keV, although lesser and greater kinetic energies may also be used. The implantation depth may be in the range of 0.2 microns to 1.5 microns, such as in the range of 0.4 microns to 1.2 microns, although lesser and greater implantation depths may also be used. The dose of the ion implantation process may be selected to provide for subsequent separation of the donor wafer 100 at a film layer formed by the ion implantation process, which layer is referred to herein as the ion implantation layer 105. In an illustrative example, the dose of the ion implantation process may be in the range of 1.0×1016 ions / cm2 to 5.0×1017 ions / cm2, although lesser and greater doses may also be used. The upper portion of the donor material layer 109 above the ion implantation layer 105 is referred to herein as the transfer material layer 110L, which includes the material to be transferred to the acceptor wafer. The lower portion of the donor material layer 109 below the ion implantation layer 105 is referred to herein as the carrier layer 108, which is used to support the transfer material layer 110L until the carrier layer 108 is separated from the acceptor wafer. Generally speaking, a film layer stack (110L, 105, 108) including the carrier layer 108, the ion implantation layer 105, and the transfer material layer 110L can be formed by implanting ions into the donor wafer 100.

[0059] Please refer to Figure 1C and Figure 1H, a patterned etching mask layer 117 can be formed above the transfer material layer 110L, and the patterned etching mask layer 117 includes intersecting laterally extending openings. For example, the patterned etching mask layer 117 may include a patterned photoresist layer. In this embodiment, a blanket (unpatterned) photoresist layer can be applied to the transfer material layer 110L and can be optically patterned to form two groups of intersecting linear openings. A group of first linear openings can extend laterally with a uniform width along a first horizontal direction hd1, and a group of second linear openings can extend laterally with a uniform width along a second horizontal direction hd2. The second horizontal direction hd2 can be perpendicular to the first horizontal direction hd1. The pattern of the first linear openings can be periodic along the second horizontal direction hd2, and the pattern of the second linear openings can be periodic along the first horizontal direction hd1.

[0060] In one embodiment, each patterned portion of the patterned etch mask layer 117 can have a horizontally lying rectangular cross-sectional shape. According to one aspect of the present disclosure, the lateral dimensions (e.g., length and width) of each patterned portion of the patterned etch mask layer 117 can be selected to prevent cracks from forming within the material of the transfer material layer 110L during the bonding process of bonding the material of the transfer material layer 110L to the receptor wafer. For example, the lateral dimensions (e.g., length and width) of each patterned portion of the patterned etch mask layer 117 can be in the range of 5 mm to 100 mm, such as in the range of 10 nm to 50 mm, although smaller and larger lateral dimensions can also be used. The width of each linear opening in the patterned etch mask layer 117 can be in the range of 30 microns to 300 microns, such as 60 microns to 150 microns, although smaller and larger widths can also be used.

[0061] An anisotropic etching process can be performed to transfer the pattern of linear openings in the patterned etch mask layer 117 through the material layer 110L and the ion implantation layer 105 to the upper portion of the carrier layer 108. The chemistry of the anisotropic etching process can be selected depending on the transfer material (i.e., the material of the transfer material layer 110L and the carrier layer 108). In illustrative examples, in embodiments where the transfer material comprises single-crystal lithium niobate or single-crystal lithium tantalate, the anisotropic etching process can include an etching chemistry using a combination of carbon tetrafluoride and oxygen. In embodiments where the transfer material comprises single-crystal lithium niobate or single-crystal lithium tantalate, the anisotropic etching process can include an etching chemistry using a combination of carbon tetrafluoride and hydrogen or a combination of sulfur hexafluoride and oxygen. In general, the transfer material layer 110L can be patterned into a plurality of transfer material plates 110 by the anisotropic etching process.

[0062] The anisotropic etching process forms intersecting trenches 111 through the transfer material layer 110L, the ion implantation layer 105, and the upper portion of the carrier layer 108. In one embodiment, the sidewalls of the intersecting trenches 111 can be formed to have a tapering angle α relative to the vertical direction. The tapering angle α can be in the range of 0.1 degrees to 10 degrees, for example, 0.3 degrees to 5 degrees, although smaller and larger values of the tapering angle α can also be used. The width of each intersecting trench 111 decreases as the vertical distance from the horizontal plane of the upper surface of the patterned portion of the transfer material layer 110L (i.e., the transfer material plate 110) increases downward.

[0063] Reference Figure 1D , an isotropic etching process can be performed to selectively etch the material of the ion implantation layer 105 relative to the transferred material (i.e., the material of the carrier layer 108 and the transferred material layer 110L). For example, a wet etching process using a mixture of hydrofluoric acid and nitric acid can be performed to selectively etch the surface portion of the physically exposed ion implantation layer 105. The lateral recess distance of the isotropic etching process can be in the range of 10 nm to 1,000 nm, for example, 30 nm to 300 nm, although smaller and larger lateral recess distances can also be used. By laterally recessing the ion implantation layer 105 with respect to the material selectivity of the carrier layer 108 and the transferred material layer 110L, lateral recesses 113 can be formed around the intersecting trenches 111. The height of each lateral recess 113 can be the same as the thickness of the ion implantation layer 105. The patterned etch mask layer 117 can then be removed, for example, by ashing or dissolving.

[0064] Please refer to Figure 1E , providing an acceptor wafer 200 including a handle substrate 208 and a first dielectric oxide layer. The first dielectric oxide layer is referred to herein as an acceptor-side dielectric oxide layer 220. The handle substrate 208 can comprise any material, which may include a semiconductor material (e.g., silicon), an insulating material, or a conductive material (e.g., a metal). The thickness of the handle substrate 208 can range from 300 microns to 2,000 microns, such as 500 microns to 1,000 microns, although lesser and greater thicknesses may also be used.

[0065] The acceptor-side dielectric oxide layer 220 comprises a layer of dielectric material that facilitates bonding with the transfer material of the transfer material plate 110. For example, the acceptor-side dielectric oxide layer 220 can comprise undoped silicate glass, doped silicate glass, or thermally grown silicon oxide (i.e., silicon oxide formed by oxidation of silicon). The thickness of the acceptor-side dielectric oxide layer 220 can range from 50 nm to 500 nm, although lesser and greater thicknesses can also be used. In an illustrative example, the handle substrate 208 can comprise single crystal silicon or polycrystalline silicon, and the acceptor-side dielectric oxide layer 220 can comprise thermally grown silicon oxide, which is a stoichiometric silicon oxide that does not contain carbon or hydrogen. Alternatively, the acceptor-side dielectric oxide layer 220 can comprise undoped silicate glass or doped silicate glass.

[0066] Acceptor wafer 200 can have the same lateral dimensions as donor wafer 100, or can have larger lateral dimensions than donor wafer 100. Donor wafer 100 can be oriented such that the two-dimensional array of transfer material slabs 110 faces the acceptor-side dielectric oxide layer 220. Subsequently, donor wafer 100 can be brought into contact with acceptor wafer 200 such that the two-dimensional array of transfer material slabs 110 contacts the physically exposed, planar surface of acceptor-side dielectric oxide layer 220.

[0067] Please refer to Figure 1F The film layer stack (110, 105, 108) of the donor wafer 100 can be attached to the acceptor wafer 200 by bonding the film layer stack (110, 105, 108) of the donor wafer 100 to a first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220 of the acceptor wafer 200). Specifically, the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) can be bonded to a two-dimensional array of transfer material plates 110, which includes patterned portions of the transfer material layer 110L. In an illustrative example, the bonding process can include a first thermal annealing process with a ramp temperature in the range of 130 degrees Celsius to 250 degrees Celsius. The duration of the first thermal annealing process can be in the range of 2 hours to 48 hours, for example, 4 hours to 24 hours, although shorter and longer durations can also be used.

[0068] Intersecting laterally extending channels 111', i.e., laterally extending channels that intersect one another, are formed when acceptor wafer 200 is attached to transfer material plate 110. Surface sections of the first dielectric oxide layer (e.g., acceptor-side dielectric oxide layer 220) may be exposed in the intersecting laterally extending channels 111'. This can form a bonded assembly between donor wafer 100 and acceptor wafer 200. The intersecting laterally extending channels 111' are interconnected and extend laterally to the peripheral sidewalls of donor wafer 100.

[0069] Please refer to Figure 1F and 1G, the film layer stack (110, 105, 108) can be separated at the ion implantation layer 105. The separation of the film layer stack (110, 105, 108) can be affected by performing a second thermal annealing process, which can be a continuation of the first thermal annealing process at a higher temperature. For example, the second thermal annealing process can be performed at an elevated temperature in the range of 230 degrees Celsius to 400 degrees Celsius, such as 250 degrees Celsius to 350 degrees Celsius. The duration of the second thermal annealing process can be in the range of from 10 minutes to 12 hours, such as 30 minutes to 4 hours, although shorter and longer durations can also be used.

[0070] The carrier layer 108 can be separated from the assembly of the handle substrate 208, the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220), and the two-dimensional array of transfer material plates 110 (hereinafter referred to as a composite wafer 300). Thus, the composite wafer 300 includes the acceptor wafer 200 and the transfer material plates 110 (which include a patterned portion of the transfer material layer 110L). The first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) can be located on the upper surface of the handle substrate 208, and the two-dimensional array of transfer material plates 110 can be attached to the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220). The two-dimensional array of transfer material plates 110 can be laterally separated from each other by intersecting channels 111'. The intersecting channels 111' can extend vertically from the flat upper surface of the transfer material plate 110 to the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220). In one embodiment, the height of each intersecting channel 111 ′ may be the same as the thickness of the transfer material plate 110 .

[0071] In one embodiment, the sidewalls of the transfer material plates 110 can have an inverted tapered profile such that the lateral extent of each transfer material plate 110 increases as the vertical distance from the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) increases. The sidewalls of the transfer material plates 110 can have a tapered angle α. In one embodiment, each intersecting channel 111' can have a variable lateral width that decreases as the vertical distance from the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) increases. In one embodiment, the two-dimensional array of transfer material plates 110 can be in contact with the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220).

[0072] Figures 2A-2C Schematic diagrams of sequential vertical cross-sections illustrating a second embodiment structure during formation of a composite wafer 300 according to an embodiment of the present disclosure.

[0073] Please refer to Figure 2A , by using mechanical means to form intersecting grooves 111 from Figure 1BThe structure of the first embodiment shown leads to the structure of the second embodiment. For example, the intersecting grooves 111 can be formed by mechanically cutting the upper portion of the transfer material layer 110L, the ion implantation layer 105, and the carrier layer 108. In this embodiment, a cutting tool can be used, and the height of the cutting blade can be set so that the cutting depth is greater than the vertical distance from the horizontal plane including the upper surface of the transfer material layer 110L to the upper surface of the carrier layer 108. Figure 2A The intersecting trenches 111 in the donor wafer 100 may have Figure 1C The transfer material plate 110 may be formed into a pattern of intersecting trenches 111 in the same manner as the donor wafer 100. The width of each selected trench from the intersecting trenches 111 may be in the range of 30 μm to 300 μm, for example, 50 μm to 150 μm, although smaller and larger widths may also be used. Each selected trench from the intersecting trenches 111 may be laterally defined by a pair of vertical sidewalls of the transfer material plate 110.

[0074] Please refer to Figure 2B , which can be used for reference Figure 1D The process steps are described to form lateral recesses 113 around the intersecting trenches 111. The isotropic etching process can selectively etch the material of the ion implantation layer 105 relative to the transferred material (ie, the material of the carrier layer 108 and the transferred material layer 110L).

[0075] Please refer to Figure 2C , you can refer to Figure 1E 、 1F and the process steps described in 1G to form the composite wafer 300. In this embodiment, each transferred material plate 110 in the composite wafer 300 may include corresponding groups of four vertical sidewalls adjoining four vertically extending edges.

[0076] Figures 3A to 3G Schematic diagrams of sequential vertical cross-sections of a third embodiment structure during formation of a composite wafer 300 according to an embodiment of the present disclosure are shown.

[0077] Please refer to Figure 3A , which shows a third exemplary structure of the donor chip 100, which may be the same as that of the reference Figure 1B The donor chip 10 provided after the process steps includes the donor material layer 109 being transformed into a combination of the transferred material layer 110L, the ion implantation layer 105 and the carrier layer 108 .

[0078] Please refer to Figure 3BA dielectric oxide layer may be formed on the upper surface of the transferred material layer 110L. The dielectric oxide layer formed on the upper surface of the transferred material layer 110L is referred to herein as the donor-side dielectric oxide layer 120L and may be referred to as the first dielectric oxide layer or the second dielectric oxide layer in the claims. Generally speaking, the donor-side dielectric oxide layer 120L may be formed before or after ion implantation into the donor wafer 100 (forming the ion implantation layer 105).

[0079] The donor side dielectric oxide layer 120L includes a dielectric oxide material that facilitates bonding with another dielectric oxide material. For example, the donor side dielectric oxide layer 120L may include and / or may consist essentially of undoped silicate glass or doped silicate glass. The donor side dielectric oxide layer 120L may be formed via chemical vapor deposition or physical vapor deposition. The thickness of the donor side dielectric oxide layer 120L may be in the range of 50 nm to 500 nm, although smaller and larger thicknesses may also be used. When combined with the donor side dielectric oxide layer 120L, the donor wafer 100 includes a film layer stack (120L, 110L, 105, 108), which includes the donor side dielectric oxide layer 120L, the transfer material layer 110L, the ion implantation layer 105, and the carrier layer 108.

[0080] Please refer to Figure 3C , the donor side dielectric oxide layer 120L in the donor wafer 100 can be used as a reference Figure 1C The anisotropic etching process can be modified to include an anisotropic etching step (which etches the material of the donor-side dielectric oxide layer 120L before etching the material of the transfer material layer 110L) to form intersecting trenches 111 through the donor-side dielectric oxide layer 120L, the transfer material layer 110L, the ion implantation layer 105, and the upper portion of the carrier layer 108. During the anisotropic etching process (i.e., during the formation of the intersecting trenches 111), the donor-side dielectric oxide layer 120L is patterned into dielectric oxide plates 120. As described above, the sidewalls of the intersecting trenches 111 can be formed to have a tapering angle α relative to the vertical direction. In one embodiment, the tapered sidewalls of the intersecting trenches 111 can include physically exposed sidewalls of the dielectric oxide plates 120 having the tapering angle α.

[0081] Please refer to Figure 3D , you can refer to Figure 1DThe process steps are described to form lateral recesses 113 around the intersecting trenches 111. Specifically, the ion implantation layer 105 can be laterally recessed selectively from the materials of the carrier layer 108 and the transferred material layer 110L, and selectively from the material of the dielectric oxide plate 120. The height of each lateral recess 113 can be the same as the thickness of the ion implantation layer 105. The patterned etch mask layer 117 can then be removed, for example, by ashing or dissolution.

[0082] Please refer to Figure 3E , which can be used for reference Figure 1E The process steps are described to provide an acceptor wafer 200 including a handle substrate 208 and an acceptor-side dielectric oxide layer 220. In the claims, the acceptor-side dielectric oxide layer 220 may be referred to as a first dielectric oxide layer or a second dielectric oxide layer. The donor wafer 100 may be oriented such that the two-dimensional array of transfer material slabs 110 faces the acceptor-side dielectric oxide layer 220. Subsequently, the donor wafer 100 may be brought into contact with the acceptor wafer 200 such that the two-dimensional array of dielectric oxide slabs 120 contacts the physically exposed, planar surface of the acceptor-side dielectric oxide layer 220.

[0083] Please refer to Figure 3F The film layer stack (120, 110, 105, 108) of the donor wafer 100 can be attached to the acceptor wafer 200 by bonding the film layer stack (120, 110, 105, 108) to the first dielectric oxide layer (e.g., acceptor-side dielectric oxide layer 220) of the acceptor wafer 200. Specifically, the first dielectric oxide layer (e.g., acceptor-side dielectric oxide layer 220) is bonded to a two-dimensional array of dielectric oxide plates 120, which includes a patterned portion of a second dielectric oxide layer (e.g., donor-side dielectric oxide layer 120L). In an illustrative example, the bonding process can include a first thermal annealing process at an elevated temperature in the range of 130 degrees Celsius to 250 degrees Celsius. The duration of the first thermal annealing process can be in the range of 2 hours to 48 hours, for example, 4 hours to 24 hours, although shorter and longer durations can also be used. The first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) is bonded to the dielectric oxide plate 120 via dielectric-to-dielectric bonding. If the first dielectric oxide layer and the dielectric oxide plate 120 comprise silicon oxide materials, the first dielectric oxide layer and the dielectric oxide plate 120 may be bonded to each other via silicon oxide-to-silicon oxide bonding.

[0084] Intersecting laterally extending channels 111', i.e., laterally extending channels that intersect one another, are formed when acceptor wafer 200 is attached to transfer material plate 110. Surface sections of the first dielectric oxide layer (e.g., acceptor-side dielectric oxide layer 220) may be exposed in the intersecting laterally extending channels 111'. This can form a bonded assembly between donor wafer 100 and acceptor wafer 200. The intersecting laterally extending channels 111' are interconnected and extend laterally to the peripheral sidewalls of donor wafer 100.

[0085] like Figure 3G As shown, the film stack (120, 110, 105, 108) can be separated at the ion implantation layer 105. The separation of the film stack (120, 110, 105, 108) can be achieved by performing a second thermal annealing process, which can be a continuation of the first thermal annealing process at a higher temperature. For example, the second thermal annealing process can be performed at an elevated temperature in the range of 230 degrees Celsius to 400 degrees Celsius, such as 250 degrees Celsius to 350 degrees Celsius. The duration of the second thermal annealing process can be in the range of 10 minutes to 12 hours, such as 30 minutes to 4 hours, although shorter and longer durations can also be used.

[0086] The carrier layer 108 can be separated from an assembly consisting of a handle substrate 208, a first dielectric oxide layer (e.g., an acceptor-side dielectric oxide layer 220), a two-dimensional array of dielectric oxide plates 120 (including a patterned portion of a second dielectric oxide layer (e.g., a donor-side dielectric oxide layer), and a two-dimensional array of transfer material plates 110. This assembly is hereinafter referred to as a composite wafer 300. Thus, the composite wafer 300 includes the acceptor wafer 200 and the transfer material plates 110 (including a patterned portion of a transfer material layer 110L). The first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) can be located on the upper surface of the handle substrate 208 and the transfer material plates 110 can be located on the upper surface of the handle substrate 208. The two-dimensional array formed by the transfer material plate 110 can be attached to the first dielectric oxide layer (e.g., the acceptor side dielectric oxide layer 220) by a two-dimensional array composed of a dielectric oxide plate 120 (which includes a patterned portion composed of a second dielectric oxide layer, e.g., the donor side dielectric oxide layer). The two-dimensional array composed of the transfer material plate 110 can be laterally separated from each other by intersecting channels 111'. The intersecting channels 111' can extend vertically from the flat upper surface of the transfer material plate 110 to the upper surface of the first dielectric oxide layer (e.g., the acceptor side dielectric oxide layer 220). In one embodiment, the height of each intersecting channel 111' can be the same as the sum of the thickness of the transfer material plate 110 and the thickness of the dielectric oxide plate 120.

[0087] In one embodiment, the sidewalls of the transfer material plates 110 may have an inversely tapered profile, such that the lateral extent of each transfer material plate 110 increases as the vertical distance from the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) increases. The sidewalls of the transfer material plates 110 may have a tapered angle α. In one embodiment, the sidewalls of the dielectric oxide plates 120 may have an inversely tapered profile, such that the lateral extent of each dielectric oxide plate 120 increases as the vertical distance from the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) increases. The sidewalls of the dielectric oxide plates 120 may have a tapered angle α. In one embodiment, each intersecting channel 111' may have a variable lateral width, which decreases as the vertical distance from the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) increases.

[0088] In one embodiment, the two-dimensional array of transfer material plates 110 may be vertically separated from the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) by a two-dimensional array of dielectric oxide plates 120. In this embodiment, the two-dimensional array of dielectric oxide plates (e.g., dielectric oxide plates 120) may be sandwiched between the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220).

[0089] Figures 4A to 4C Schematic diagrams of sequential vertical cross-sections illustrating a fourth embodiment structure during formation of a composite wafer 300 according to an embodiment of the present disclosure.

[0090] Please refer to Figure 4A The structure of the fourth embodiment can be obtained by forming the intersecting grooves 111 by mechanical means. Figure 3B The structure of the third embodiment is shown. For example, the intersecting trenches 111 can be formed by mechanically cutting the donor-side dielectric oxide layer 120L, the transferred material layer 110L, the ion implantation layer 105, and the upper portion of the carrier layer 108. In this embodiment, the cutting can be performed using a cutting tool, and the height of the cutting blade can be set so that the cutting depth is greater than the vertical distance from the horizontal plane including the upper surface of the transferred material layer 110L to the upper surface of the carrier layer 108. Figure 4A The intersecting trenches 111 in the donor wafer 100 may have the same Figure 3C The donor wafer 100 may include a pattern of intersecting trenches 111. The width of each trench selected from the intersecting trenches 111 may range from 30 microns to 300 microns, such as 50 microns to 150 microns, although smaller and larger widths may also be used. Each trench selected from the intersecting trenches 111 may be laterally defined by a pair of vertical sidewalls of the transfer material plate 110.

[0091] Please refer to Figure 4B , you can refer to Figure 3D The process steps are described to form lateral recesses 113 around the intersecting trenches 111. The isotropic etching process can selectively etch the material of the ion implantation layer 105 relative to the transferred material (ie, the material of the carrier layer 108 and the transferred material layer 110L).

[0092] Please refer to Figure 4C , you can refer to Figure 3E and 3F The process steps are repeated to form the composite wafer 300. In this embodiment, each transferred material plate 110 in the composite wafer 300 may include a corresponding set of four vertical sidewalls adjacent to four vertically extending edges.

[0093] Figure 5A 、 Figure 5B and 5D Schematic diagrams of sequential vertical cross-sections illustrating a fifth embodiment structure during formation of a composite wafer 300 according to an embodiment of the present disclosure. Figure 5C yes Figure 5B A top view of a fifth exemplary structure. Figure 5E yes Figure 5D A top view of a fifth exemplary structure.

[0094] Please refer to Figure 5A , a plurality of donor wafers 100 may be provided, each of the donor wafers 100 including a corresponding film layer stack (120 (optional), 110, 105, 108) in any of the above-described embodiments. Thus, each donor wafer 100 may include a corresponding film layer stack (120L (optional), 110L, 105, 108), which includes a corresponding optional dielectric oxide layer (e.g., a donor-side dielectric oxide layer 120L), a transfer material layer 110L, a corresponding additional ion implantation layer 105, and a corresponding additional carrier layer 108. Intersecting trenches 111 pass through the upper portions of each layer in at least one additional film layer stack (120L (optional), 110L, 105, 108). Each patterned film layer stack may include a two-dimensional array (not shown) of optional dielectric oxide plates, a two-dimensional array of transfer material plates 110, an ion implantation layer 105, and a carrier layer 108.

[0095] In the fifth embodiment structure, the area of the donor wafer 100 in a planar view (e.g., a top-down view) is smaller than the area of the acceptor wafer 200 in a planar view. In one embodiment, the acceptor wafer 200 can have a sufficiently large area to accommodate two or more donor wafers 100. Each donor wafer 100 can be oriented such that the two-dimensional array of transfer material plates 110 faces the acceptor-side dielectric oxide layer 220. Subsequently, the donor wafer 100 can be brought into contact with the acceptor wafer 200 such that the two-dimensional array of transfer material plates 110 contacts the physically exposed flat surface of the acceptor-side dielectric oxide layer 220.

[0096] Please refer to Figure 5B and 5C , which can be used for reference Figure 1F The process steps or reference Figure 3F The process steps described can be modified by pressing each donor wafer 100 against the acceptor wafer 200 during the bonding process. Generally speaking, each donor wafer 100 including the corresponding film layer stack (120 (optional), 110, 105, 108) can be attached to the acceptor wafer 200 by bonding the respective film layer stack (120 (optional), 110, 105, 108) to a first dielectric oxide layer (e.g., acceptor-side dielectric oxide layer 220).

[0097] The illustrated example corresponds to an embodiment in which a total of seven donor wafers 100 are attached to an acceptor wafer 200. Generally speaking, in the fifth exemplary structure, two or more donor wafers 100 can be attached to the same acceptor wafer 200. Furthermore, while the present disclosure is described using an embodiment in which each donor wafer 100 has a circular shape in plan view, the donor wafer 100 can generally have any two-dimensional shape with a closed perimeter in plan view. For example, the donor wafer 100 can have an elliptical shape, a polygonal shape, or any two-dimensional curved shape with a closed perimeter in plan view. The sizes of the donor wafers 100 can be the same as or different from one another.

[0098] Please refer to Figure 5D and 5E , which can be used for reference Figure 1G and 1H or refer to Figure 3GThe process steps are described to separate the individual film layer stacks (120 (optional), 110, 105, 108) at the corresponding additional ion implantation layer 105. A composite wafer 300 is provided, which includes the acceptor wafer 200 and a plurality of two-dimensional arrays of transfer material plates 110 (including a patterned portion of the transfer material layer 110L). A first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) can be located on the upper surface of the handling substrate 208, and the plurality of two-dimensional arrays of transfer material plates 110 can be attached to the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) via a plurality of two-dimensional arrays of dielectric oxide plates 120 (including a patterned portion of the second dielectric oxide layer (e.g., the donor-side dielectric oxide layer)).

[0099] The two-dimensional arrays of transfer material plates 110 can be of different sizes. In other words, the arrays of multiple transfer material plates 110 transferred from different donor wafers 100 may not have periodicity. The gap between adjacent pairs of transfer material plate 110 arrays can be at least three times greater than the width of each intersecting channel 111', and typically 10 times or more, and / or 100 times or more.

[0100] The transfer material plates 110 within each two-dimensional array of transfer material plates 110 can be laterally separated from each other by intersecting channels 111'. The intersecting channels 111' can extend vertically from the flat upper surface of the transfer material plate 110 to the upper surface of the first dielectric oxide layer (e.g., the receptor-side dielectric oxide layer 220). The height of each intersecting channel 111' can be equal to the thickness of the transfer material plate 110, or can be equal to the sum of the thickness of the transfer material plate 110 and the thickness of the dielectric oxide plate 120.

[0101] In one embodiment, the sidewalls of the transfer material plates 110 may have an inverted tapered profile such that the lateral extent of each transfer material plate 110 increases as the vertical distance from the first dielectric oxide layer (e.g., the receptor-side dielectric oxide layer 220) increases. In some embodiments, the sidewalls of the transfer material plates 110 may have a profile such as Figure 1G Or the tapering angle α shown in FIG3G. In one embodiment, the sidewalls of the dielectric oxide plates 120 may have an inverted tapered profile such that the lateral extent of each dielectric oxide plate 120 increases with increasing vertical distance from the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220). The sidewalls of the dielectric oxide plates 120 may have a tapering angle α. In one embodiment, each intersecting channel 111' may have a variable lateral width that decreases with increasing vertical distance upward from the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220).

[0102] Figure 6A 、6C 6D and 6D are sequential vertical cross-sectional views of a sixth embodiment structure during formation of a composite wafer 300 according to an embodiment of the present disclosure. Figure 6B Show Figure 6A FIG. 1 is a top view of the donor wafer 100 . Figure 6E Show Figure 6D A top view of the composite wafer 300 is shown.

[0103] Please refer to Figure 6A and 6B , which shows a donor wafer 100 of the sixth embodiment structure, which can be removed from the donor wafer 100 by removing the peripheral area of the film layer stack (120 (optional), 110, 105, 108) located outside the area constituting the patterned portion of the transfer material layer 110L (i.e., the transfer material plate 110). Figure 3D 、 4B 5B . In one embodiment, each transfer material plate 110 can have a corresponding horizontally lying rectangular cross-sectional shape, and a peripheral region of the film stack (optional 120, 110, 105, 108) (which may not accommodate the full-size rectangular transfer material plate 110 region) can be removed to provide a field region having all material portions removed from a horizontal plane including the lower surface of the intersecting trenches 111. Generally speaking, the peripheral region can extend continuously along the edge of the donor wafer 100 and laterally surround the two-dimensional periodic array of transfer material plates 110, and can have a variable lateral width that varies along an azimuthal angle about a vertical axis passing through the geometric center of the donor wafer 100. In one embodiment, the variable lateral width can be at least twice the width of the intersecting trenches 111.

[0104] Please refer to Figure 6C , which can be used for reference Figure 6C Figure 3E and 3F or Figure 5B and 5C The process steps are performed to bond each donor wafer 100 to the acceptor wafer 200. When forming the bonded assembly of the acceptor wafer 200 and each donor wafer 100, a continuous gap may be formed between the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) of the acceptor wafer 200 and the recessed surface of the carrier layer 108 of each donor wafer 100.

[0105] Please refer to Figure 6D and 6E , which can be used for reference Figure 3G 、 4C or Figure 5D and 5EThe process steps are described to separate the composite wafer 300 from the carrier layer 108. The composite wafer 300 includes a handle substrate 208, a first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220), a two-dimensional array of at least one optional dielectric oxide plate 120, and a two-dimensional array of at least one optional transfer material plate 110. In one embodiment, a peripheral region without any transfer material plate 110 may exist on the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) surrounding the two-dimensional array of transfer material plates 110. In one embodiment, the lateral width of the peripheral region may be greater than twice the width of each intersecting channel 111'.

[0106] Figure 7A 、 7C 7D and 7D are sequential vertical cross-sectional views of the structure of the seventh embodiment during the formation of the composite wafer 300 according to an embodiment of the present disclosure. Figure 7B for Figure 7A FIG. 1 is a top view of the donor wafer 100 . Figure 7E for Figure 7D A top view of the composite wafer 300 is shown.

[0107] Please refer to Figure 7A and 7B , which shows a donor wafer 100 of a seventh embodiment structure, which can be removed from the outer periphery of the film layer stack (120 (optional), 110, 105, 108) located outside the area of the patterned portion composed of the transfer material layer 110L (i.e., the transfer material plate 110). Figure 1D 、 2B 5B . In one embodiment, each transfer material plate 110 can have a corresponding horizontally lying rectangular cross-sectional shape, and a peripheral region of the film stack (optional 120, 110, 105, 108) (which may not accommodate the full-size rectangular transfer material plate 110 region) can be removed to provide a field region having all material removed from a horizontal plane above the bottom surface of the intersecting trenches 111. In general, the peripheral region can extend continuously along the edge of the donor wafer 100 and laterally around the two-dimensional periodic array of transfer material plates 110, and have a variable lateral width that varies azimuthally about a vertical axis passing through the geometric center of the donor wafer 100. In one embodiment, the variable lateral width can be at least twice the width of the intersecting trenches 111.

[0108] Please refer to Figure 7C , can be carried out Figure 1E and 1F or Figure 5B and 5CThe process steps are performed to bond each donor wafer 100 to an acceptor wafer 200. When forming the bonded assembly of the acceptor wafer 200 and each donor wafer 100, a continuous gap may exist between the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) of the acceptor wafer 200 and the recessed surface of the carrier layer 108 of each donor wafer 100.

[0109] Please refer to Figures 7D and 7E to Figure 1G 、 1H , 2C or Figure 5D and 5E The composite wafer 300 is separated from the carrier layer 108 by a process step. The composite wafer 300 includes a handle substrate 208, a first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220), at least one optional two-dimensional array of dielectric oxide plates 120, and at least one optional two-dimensional array of transfer material plates 110. In one embodiment, a peripheral region of the transfer material plates 110 may be present above the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) surrounding the two-dimensional array of transfer material plates 110, free of any material. In one embodiment, the lateral width of this peripheral region may be greater than twice the width of each intersecting channel 111'.

[0110] Please refer to Figure 8 , the first flow chart illustrates a sequence of process steps that may be used to form a composite wafer 300 according to an embodiment of the present disclosure.

[0111] Please refer to step 810 and Figure 1A 、 1B , 2A, 3A, 3B, 4A, 5A, 6A and 6B and 7A and 7B, a film layer stack (120L (optional), 110L, 105, 108) can be formed by implanting ions into the donor wafer 100, which includes a carrier layer 108, an ion implantation layer 105 and a transfer material layer 110L.

[0112] Please refer to step 820 and Figure 1C 、 1D , 2A, 2B, 3C, 3D, 4A, 4B, 5A, 6A, 6B and Figure 7A and 7B , intersecting grooves 111 may be formed, passing through the transfer material layer 110L, the ion implantation layer 105 and the upper portion of the carrier layer 108 .

[0113] Please refer to step 830 and Figure 1E 、 1F, 2C, 3E, 3F, 4C, 5B, 5C, 6C and 7C, the film layer stack (120 (optional), 110, 105, 108) can be attached to the acceptor wafer 200 (including the stack of the handling substrate 208 and the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220)) by bonding the film layer stack (120 (optional), 110, 105, 108) to the first dielectric oxide layer.

[0114] Please refer to step 840 and Figure 1G 、 1H , 2C, 3G, 4C, 5D, 5E, 6D, 6E, 7D and 7E can separate the membrane layer stack (120 (optional), 110, 105, 108) at the ion implantation layer 105, thereby forming a composite wafer 300 (including a patterned portion of the acceptor wafer 200 and the transfer material layer 110L (for example, a two-dimensional array of transfer material plates 110).

[0115] In one embodiment, the method may further include the following steps: forming a patterned etch mask layer (including intersecting laterally extending openings) above the transferred material layer 110L; and transferring the pattern of the intersecting laterally extending openings into the transferred material layer 110L by performing an anisotropic etching process to form intersecting trenches 111. In one embodiment, the intersecting trenches 111 may be formed by mechanically cutting the upper portion of the transferred material layer 110L, the ion implantation layer 105, and the carrier layer 108. In one embodiment, the method may further include forming a lateral recess around the intersecting trenches 111 by laterally recessing the ion implantation layer 105 based on the material selectivity of the carrier layer 108 and the transferred material layer 110L. In one embodiment, the film layer stack (110L, 105, 108) may include a second dielectric oxide layer 120L formed on an upper surface of the transferred material layer 110L; and the method may include patterning the second dielectric oxide layer 120L into a plurality of dielectric oxide plates during the formation of the intersecting trenches 111. In one embodiment, the first dielectric oxide layer 220 may be bonded to the dielectric oxide plates 110 via dielectric-to-dielectric bonding. In one embodiment, the first dielectric oxide layer 220 may be bonded to the patterned portion of the transferred material layer 110L. In one embodiment, the method may also include the following steps: forming at least one additional film layer stack (including a corresponding additional carrier layer 108, a corresponding additional ion implantation layer 105, and a corresponding additional transfer material layer 110L); forming a plurality of additional intersecting trenches 111 through an upper portion of each of the at least one additional film layer stack; bonding each of the at least one additional film layer stack to the acceptor wafer 200 by bonding each of the at least one additional film layer stack to the first dielectric oxide layer 220; and separating each of the at least one additional film layer stack at the corresponding additional ion implantation layer 105. In one embodiment, the method may also include the following steps: removing a peripheral region of the film layer stack outside of the region of the patterned portion comprising the transfer material layer, wherein a width of the peripheral region is at least twice a width of the intersecting trenches 111. In one embodiment, the donor wafer 100 may include a single crystal lithium niobate wafer or a single crystal lithium tantalate wafer.

[0116] Please refer to Figure 9 , the second flow chart illustrates a sequence of process steps that may be used to form a composite wafer 300 according to an embodiment of the present disclosure.

[0117] Please refer to step 910 and Figure 1A 、 1B , 2A, 3A, 3B, 4A, 5A, 6A and 6B and 7A and 7B, ions can be implanted into the donor wafer 100 to form a film layer stack (120L (optional), 110L, 105, 108), which includes a carrier layer 108, an ion implantation layer 105 and a transfer material layer 110L.

[0118] Please refer to step 920 and Figure 1C 、 2A , 3C, 4A, 5A, 6A, 6B, 7A and 7B can form intersecting grooves 111 through the transfer material layer 110L, the ion implantation layer 105 and the upper portion of the carrier layer 108 to pattern the upper portion of the film layer stack (120L (optional), 110L, 105, 108).

[0119] Please refer to step 930 and Figure 1D 、 2B , 3D, 4B, 5A, 6A, 6B, 7A and 7B can laterally recess the ion implantation layer 105 to form lateral recesses 113 around the intersecting grooves 111 by selectivity of the material of the patterned portion consisting of the supporting layer 108 and the transfer material layer 110L (i.e., the two-dimensional array consisting of the transfer material plate 110).

[0120] Please refer to step 940 and Figure 1E 、 1F , 2C, 3E, 3F, 4C, 5B, 5C, 6C and 7C, can attach the acceptor wafer 200 (including the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220)) to the patterned portion of the transfer material layer 110L (e.g., a two-dimensional array of transfer material plates 110).

[0121] Please refer to step 950 and Figure 1G 、 1H , 2C, 3G, 4C, 5D, 5E, 6D, 6E, 7D and 7E can separate the membrane layer stack (120 (optional), 110, 105, 108) at the ion implantation layer 105, thereby forming a composite wafer 300 (including a patterned portion of the acceptor wafer 200 and the transfer material layer 110L (for example, a two-dimensional array of transfer material plates 110).

[0122] In one embodiment, a plurality of intersecting laterally extending channels 111' may be formed when the acceptor wafer 200 is attached to the patterned portion of the transferred material layer 110; and a plurality of surface sections of the first dielectric oxide layer 220 may be exposed in the intersecting laterally extending channels 111'. In one embodiment, the method may also include the steps of forming a second dielectric oxide layer 120 on an upper surface of the donor wafer 100; and patterning the second dielectric oxide layer 120 into a plurality of dielectric oxide plates during the formation of the intersecting trenches 111. In one embodiment, the second dielectric oxide layer 120 may be formed after ion implantation into the donor wafer 100; and the dielectric oxide plates may be bonded to the first dielectric oxide layer 220 via dielectric-to-dielectric bonding. In one embodiment, the sidewalls of the formed intersecting trenches 111 may have a tapered angle α relative to the vertical direction, such that the width of the intersecting trenches 111 decreases as the vertical distance from the horizontal plane including the upper surface of the patterned portion of the transferred material layer 110 increases.

[0123] Referring to all the accompanying drawings, according to various embodiments of the present disclosure, a composite wafer 300 is provided, which includes: a first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) located on the upper surface of a handling substrate 208; and a two-dimensional array consisting of a plurality of transfer material plates 110 attached to the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) and laterally spaced apart from each other by intersecting channels 111', which extend vertically from the plurality of flat upper surfaces of the transfer material plates 110 to the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220).

[0124] In one embodiment, each of the intersecting channels 111' has a variable lateral width, which decreases as the vertical distance from the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) increases. In one embodiment, the composite wafer 300 further includes a two-dimensional array of a plurality of dielectric oxide plates (e.g., dielectric oxide plates 120), which are sandwiched between the two-dimensional array of transfer material plates 110 and the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220).

[0125] In one embodiment, the two-dimensional array of transfer material plates 110 is in contact with the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220). In one embodiment, the composite wafer 300 further includes a peripheral region of the transfer material plates 110 that is free of any material and exists on the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220) surrounding the two-dimensional array of transfer material plates 110; and the lateral width of the peripheral region is greater than twice the width of each of the intersecting channels 111'.

[0126] In one embodiment, the first dielectric oxide layer (e.g., acceptor-side dielectric oxide layer 220) is bonded to the dielectric oxide plate 120 via dielectric-to-dielectric bonding. In one embodiment, the first dielectric oxide layer (e.g., acceptor-side dielectric oxide layer 220) is bonded to a patterned portion of the transfer material layer 110L (i.e., transfer material plate 110).

[0127] In one embodiment, the composite wafer 300 includes at least one additional array of transfer material plates 110 transferred from at least one additional donor wafer 100 .

[0128] In one embodiment, a peripheral region of the film stack (optional 120L, 110, 105, 108) (located outside the region of the patterned portion of the transfer material layer 110L (i.e., transfer material sheet 110)) may be removed prior to transferring the patterned portion of the transfer material layer 110L. The width of the peripheral region is at least twice the width of the intersecting trench 111.

[0129] In one embodiment, the donor wafer 100 includes a single crystal lithium niobate wafer or a single crystal lithium tantalate wafer, and the composite wafer 300 includes at least one two-dimensional array of single crystal lithium niobate material plates (having the same crystallographic orientation), or at least one two-dimensional array of single crystal lithium tantalate material plates (having the same crystallographic orientation).

[0130] In one embodiment, the sidewalls of the intersecting trenches 111 may be formed with a tapered angle α relative to the vertical direction, such that the width of the intersecting trenches 111 decreases as the vertical distance increases downward from a horizontal plane comprising the upper surface of the patterned portion of the transferred material layer 110L (i.e., the transferred material plate 110). In this embodiment, the intersecting channels 111' may be formed with reverse-tapered sidewalls having a tapered angle α, such that the width of each channel selected from the intersecting channels 111' has a variable width that decreases as the vertical distance increases from the upper surface of the first dielectric oxide layer (e.g., the acceptor-side dielectric oxide layer 220).

[0131] Various embodiments of the present disclosure may be used to provide a composite wafer 300 comprising at least one two-dimensional array of transfer material plates 110. The transfer material plates 110 may have a thermal expansion coefficient that is significantly mismatched with respect to the thermal expansion coefficient of the material of the handle substrate 208. In an illustrative example, the handle substrate 208 may comprise single crystal silicon, which has a thermal expansion coefficient of approximately 2.6×10-6 / °C at a temperature of 20°C, and the transfer material plates 110 may comprise lithium niobate (LiNbO3), which has a thermal expansion coefficient of approximately 4.0×10-6 / °C in a direction perpendicular to the axial direction (c-direction) at a temperature of 20°C and a thermal expansion coefficient of approximately 1.5×10-5 / °C in a direction perpendicular to the axial direction (c-direction) at a temperature of 20°C. In another illustrative example, handle substrate 208 may comprise single crystal silicon having a coefficient of thermal expansion of approximately 2.6 x 10-6 / °C at 20°C, and transfer material plate 110 may comprise single crystal indium gallium zinc oxide having a coefficient of thermal expansion of approximately 7.2 x 10-6 / °C at 20°C. The lateral dimensions of each transfer material plate 110 may be limited and range from 1% to 50% of the lateral dimensions of handle substrate 208. Thus, the limited lateral dimensions of transfer material plate 110 may limit thermal expansion of transfer material plate 110 during the bonding process, preventing cracking of composite wafer 300. Furthermore, by limiting the lateral dimensions of transfer material plate 110, intersecting grooves 111 may provide a degree of resilience to the bonded film layer stack, mitigating warping and cracking. Consequently, even when the transfer material has a large mismatch in thermal expansion coefficient relative to that of the material of handle substrate 208, a high-quality composite wafer 300 free of cracks or having a low density of crack defects may be provided.

[0132] The above briefly describes the characteristic components of several embodiments of the present invention, so that those skilled in the art can more easily understand the aspects of the present disclosure. Anyone skilled in the art should understand that this disclosure can be easily used as a basis for modification or design of other processes or structures to achieve the same purposes and / or obtain the same advantages as the embodiments described herein. Anyone skilled in the art will also understand that structures equivalent to the above do not depart from the concept and scope of protection of the present disclosure, and can be changed, replaced, and modified without departing from the concept and scope of the present disclosure.

Claims

1. A composite wafer, characterized in that: include: a first dielectric oxide layer disposed on an upper surface of a disposal substrate; as well as A two-dimensional array of transfer material plates is attached to the first dielectric oxide layer and laterally separated by intersecting channels extending vertically from planar upper surfaces of the transfer material plates to an upper surface of the first dielectric oxide layer.

2. The composite wafer according to claim 1, wherein: Each of the plurality of intersecting channels has a variable lateral width that decreases with increasing vertical distance from a top surface of the first dielectric oxide layer.

3. The composite wafer according to claim 2, wherein: The invention also includes a two-dimensional array composed of a plurality of dielectric oxide plates, which is sandwiched between the two-dimensional array composed of the plurality of transfer material plates and the first dielectric oxide layer.

4. The composite wafer according to claim 2, wherein: A two-dimensional array of the plurality of transfer material plates is in contact with the upper surface of the first dielectric oxide layer.

5. The composite wafer according to claim 1, wherein: a peripheral region existing on the upper surface of the first dielectric oxide layer surrounding the two-dimensional array of the plurality of transfer material plates, the peripheral region being free of any of the plurality of transfer material plates; as well as The peripheral region has a lateral width greater than twice the width of each of the plurality of intersecting channels.

6. A composite wafer, characterized in that: include: a dielectric oxide layer disposed on an upper surface of a disposal substrate; a plurality of dielectric oxide plates located on an upper surface of the dielectric oxide layer; as well as A plurality of transfer material plates are correspondingly located on the upper surfaces of the plurality of dielectric oxide plates, wherein the plurality of dielectric oxide plates are in direct contact with the dielectric oxide layer and the plurality of transfer material plates.

7. The composite wafer according to claim 6, wherein: The plurality of transfer material plates are laterally separated from one another by a plurality of intersecting channels, and the plurality of dielectric oxide plates are laterally separated from one another by the plurality of intersecting channels.

8. The composite wafer according to claim 7, wherein: Each of the plurality of intersecting channels extends from an upper surface of each of the plurality of transfer material plates to the upper surface of the dielectric oxide layer.

9. The composite wafer according to claim 7, wherein: Each of the plurality of intersecting channels has two opposing tapering sidewalls.

10. The composite wafer according to claim 9, wherein: The distance between the plurality of opposed tapered sidewalls decreases as the vertical distance from the upper surface of the dielectric oxide layer increases.

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