HJT laminated solar cell

Abstract

The utility model provides an HJT laminated solar cell, and relates to the solar cell field, the HJT laminated solar cell comprises a heterojunction substrate cell, a connecting layer, a first SiCx layer, an interface passivation layer, a second SiCx layer, a first TCO layer and a second TCO layer, the connecting layer is arranged on one side of the heterojunction substrate cell, and the connecting layer is a tunneling layer or a conductive layer; the first SiCx layer is arranged on one side, far away from the heterojunction substrate cell, of the connecting layer; the interface passivation layer is arranged on one side, far away from the heterojunction substrate cell, of the first SiCx layer; the second SiCx layer is arranged on one side, far away from the heterojunction substrate cell, of the interface passivation layer; the conduction types of the first SiCx layer and the second SiCx layer are different, compared with the prior art, the HJT laminated solar cell provided by the utility model can realize better and more comprehensive absorption of light through matching of different band gap cells, and meanwhile, the HJT laminated solar cell is stable in structure, compatible with the existing heterojunction equipment, low in manufacturing cost and high in reliability. And the problem of UV attenuation caused by high-energy photons can be avoided.

Description

Technical Field

[0001] The utility model relates to the field of solar cells, and in particular to an HJT stacked solar cell. Background Art

[0002] Solar energy is a highly anticipated new clean energy source, boasting the advantages of abundant resources and low costs. Currently, photovoltaic cells are one of the most efficient ways to convert solar energy into electricity, and monocrystalline and polycrystalline silicon solar cells have relatively mature industrial technologies. In recent years, crystalline silicon stacking technology has become a research hotspot in photovoltaic technology, garnering widespread attention. The basic principle of crystalline silicon stacking technology is to stack other materials (such as perovskites) with crystalline silicon to form a heterojunction. This technology leverages the wide bandgap and high absorption coefficient of the top material, along with the stability and excellent electron transport properties of crystalline silicon, to improve the photovoltaic conversion efficiency of solar cells. Conventional single-cell PERC cells have a bandgap of approximately 1.1 eV, which is smaller than the optimal bandgap of 1.4 eV. This makes them essentially unable to utilize high-energy photons within 400 nm, resulting in a loss of approximately 20% of the spectral energy. By matching cells with different bandgaps, stacked solar cells achieve better and more comprehensive light absorption. This technological advancement is crucial for improving the photovoltaic conversion efficiency of solar cells and reducing manufacturing costs, thereby promoting the further development and application of solar power generation technology.

[0003] In the field of tandem solar cells, crystalline silicon / perovskite tandem solar cells are the most promising and suitable technology, with theoretical effective photoelectric conversion efficiencies exceeding 40%. Numerous research institutions and companies have conducted in-depth research in this area. However, challenges such as the stability of perovskite cells, compatibility with crystalline silicon cells, and the development of mass-production equipment for perovskite cells have limited the transition from laboratory to mass production, making this technology virtually impossible to achieve in the near future. Other tandem cell approaches, such as copper indium gallium selenide / crystalline silicon tandem, cadmium telluride / crystalline silicon tandem, and others, also face challenges with equipment investment and process compatibility, and are far less promising and cost-effective than crystalline silicon / perovskite tandem solar cells.

[0004] HJT cells have the advantages of a short process flow and high conversion efficiency. HJT / perovskite tandem cells are also recognized as a promising development direction. However, as mentioned above, perovskite cells have poor stability and poor compatibility with HJT cells. The development cost of perovskite mass production equipment is also a problem that limits the technology route from laboratory to mass production. Utility Model Content

[0005] The purpose of the present utility model is to provide an HJT stacked solar cell, which can achieve better and more comprehensive absorption of light by matching cells with different band gaps, and at the same time has a stable structure, is compatible with existing heterojunction equipment, has a low manufacturing cost, and can avoid the UV attenuation problem caused by high-energy photons.

[0006] The embodiment of the present utility model is achieved as follows:

[0007] In a first aspect, the present invention provides a HJT stacked solar cell, comprising:

[0008] Heterojunction substrate cells;

[0009] A first TCO layer is provided on one side of the heterojunction substrate cell;

[0010] A connection layer is provided on a side of the heterojunction substrate cell away from the first TCO layer, and the connection layer is a tunneling layer or a conductive layer;

[0011] First SiC x A layer is provided on a side of the connecting layer away from the heterojunction substrate battery;

[0012] An interface passivation layer is provided on the first SiC x The layer is away from the side of the heterojunction substrate battery;

[0013] Second SiC x A layer is provided on a side of the interface passivation layer away from the heterojunction substrate battery;

[0014] The second TCO layer is provided on the second SiC x The layer is away from the side of the heterojunction substrate battery;

[0015] Wherein, the first SiC x layer and the second SiC x The layers are of different conductivity types.

[0016] In an optional embodiment, the first SiC x Layer includes 5-20nm thick SiC x layer.

[0017] In an optional embodiment, the second SiC x Layer includes 5-20nm thick SiC x or SiCO x O y layer.

[0018] In an optional embodiment, the first SiC x The second SiC layer is a p-type doped layer. xThe layer is an n-type doped layer.

[0019] In an optional embodiment, the interface passivation layer includes a silicon oxide layer with a thickness of 1-2 nm, an intrinsic amorphous silicon layer with a thickness of 1-3 nm, or an intrinsic SiC layer with a thickness of 1-3 nm. x layer.

[0020] In an optional embodiment, the connection layer is a tunneling layer, and the tunneling layer includes a silicon oxide layer with a thickness of 1-2 nm or an intrinsic amorphous silicon layer with a thickness of 1-3 nm.

[0021] In an optional embodiment, the connecting layer is a conductive layer, and the conductive layer includes an ITO layer with a thickness of 2-20 nm, a NIO x layer or AZO layer.

[0022] In an optional embodiment, the heterojunction substrate cell includes:

[0023] An n-type silicon substrate having a first surface and a second surface;

[0024] a first intrinsic layer, disposed on the first surface;

[0025] a second intrinsic layer, disposed on the second surface;

[0026] a first microcrystalline silicon layer, disposed on the first intrinsic layer;

[0027] a second microcrystalline silicon layer, disposed on the second intrinsic layer;

[0028] The first TCO layer is arranged on a side of the second microcrystalline silicon layer away from the n-type silicon substrate, the connecting layer is arranged on a side of the first microcrystalline silicon layer away from the n-type silicon substrate, and the first microcrystalline silicon layer and the second microcrystalline silicon layer have different conductivity types.

[0029] In an optional embodiment, the first microcrystalline silicon layer is an n-type microcrystalline silicon layer, and the second microcrystalline silicon layer is a p-type microcrystalline silicon layer.

[0030] In an optional embodiment, a first electrode layer is provided on a side of the first TCO layer away from the n-type silicon substrate, and a second electrode layer is provided on a side of the second TCO layer away from the n-type silicon substrate.

[0031] The beneficial effects of the embodiments of the present utility model include:

[0032] The HJT stacked solar cell provided by the embodiment of the utility model uses a heterojunction base cell as a base, and sequentially deposits a connection layer, a first SiC x layer, interface passivation layer and second SiC xlayer, thus forming a SiC x p / n junction cell structure, SiC x As a semiconductor material, the band gap is 2.4eV, making SiC x The p / n junction cell has the advantages of a wide bandgap and high carrier mobility, and can better utilize the high-energy spectrum, making it a very good top-level cell structure. Furthermore, due to the stable material and structural characteristics of the top-level cell structure, the problem of UV attenuation caused by high-energy photons is avoided. Furthermore, the stacked structure is compatible with existing heterojunction equipment, requiring no additional equipment expenditure, reducing production costs and facilitating industrialization. Compared to the prior art, the HJT stacked solar cell provided by the present invention can achieve better and more comprehensive light absorption by matching cells with different band gaps. At the same time, it has a stable structure, is compatible with existing heterojunction equipment, has a low manufacturing cost, and can avoid the problem of UV attenuation caused by high-energy photons. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 A schematic structural diagram of a HJT stacked solar cell provided in an embodiment of the present utility model;

[0035] Figure 2 A schematic structural diagram of another HJT stacked solar cell provided in an embodiment of the present utility model;

[0036] Figure 3 A flowchart of the steps of the method for preparing the HJT stacked solar cell provided in an embodiment of the present invention.

[0037] icon:

[0038] 100-HJT stacked solar cell; 110-heterojunction base cell; 111-n-type silicon substrate; 112-first intrinsic layer; 113-second intrinsic layer; 114-first microcrystalline silicon layer; 115-second microcrystalline silicon layer; 120-connecting layer; 130-first SiC x Layer; 140-interface passivation layer; 150-second SiC x layer; 160 - first TCO layer; 170 - second TCO layer; 180 - first electrode layer; 190 - second electrode layer. DETAILED DESCRIPTION

[0039] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are also within the scope of protection of the present invention.

[0041] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0042] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the utility model product is typically placed when in use. These terms are intended solely to facilitate the description of this utility model and to simplify the description, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this utility model. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0043] Furthermore, terms such as "horizontal" and "vertical" do not necessarily mean that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0044] It should also be noted that, in the description of this utility model, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0045] Please refer to Figure 1 The HJT stacked solar cell 100 provided in this embodiment can achieve better and more comprehensive absorption of light by matching cells with different band gaps. At the same time, it has a stable structure, is compatible with existing heterojunction equipment, has a low manufacturing cost, and can avoid the UV attenuation problem caused by high-energy photons.

[0046] The HJT stacked solar cell 100 provided in an embodiment of the present invention includes a heterojunction substrate cell 110, a connection layer 120, a first SiCx layer 130, an interface passivation layer 140, a second SiCx layer 150, a first TCO layer 160 and a second TCO layer 170. The first TCO layer 160 is arranged on one side of the heterojunction substrate cell 110, and the connection layer 120 is arranged on the side of the heterojunction substrate cell 110 away from the first TCO layer 160. The connection layer 120 is a tunneling layer or a conductive layer. The Cx layer 130 is arranged on the side of the connecting layer 120 away from the heterojunction substrate cell 110; the interface passivation layer 140 is arranged on the side of the first SiCx layer 130 away from the heterojunction substrate cell 110; the second SiCx layer 150 is arranged on the side of the interface passivation layer 140 away from the heterojunction substrate cell 110; the second TCO layer 170 is arranged on the side of the second SiCx layer 150 away from the heterojunction substrate cell 110; wherein the first SiCx layer 130 and the second SiCx layer 150 have different conductivity types.

[0047] It should be noted that, in this embodiment, the heterojunction substrate cell 110 is used as the substrate, and a connection layer 120, a first SiCx layer 130, an interface passivation layer 140 and a second SiCx layer 150 are sequentially deposited on the heterojunction substrate cell 110, thereby forming a SiC x p / n junction cell structure, SiC x As a semiconductor material, the band gap is 2.4eV, making SiC x The p / n junction cell has the advantages of a wide bandgap and high carrier mobility, making it an excellent top-cell structure for better utilization of the high-energy spectrum. Furthermore, due to its stable material and structural properties, this top-cell structure avoids the problem of UV attenuation caused by high-energy photons. Furthermore, the stacked structure is compatible with existing heterojunction equipment, eliminating the need for additional equipment expenditures, reducing production costs, and facilitating industrialization.

[0048] In some embodiments, the first SiCx layer 130 includes SiC with a thickness of 5-20 nm. x The layer can be prepared by silane, hydrogen, and methane according to a gas content of 1:100:0.5-1:10000:5, doped with 2%-200% gas content of borane or TMB and other gases, and the temperature is 120-200 degrees Celsius.

[0049] In some embodiments, the second SiCx layer 150 comprises a SiCx or SiCOxOy layer having a thickness of 5-20 nm. Preferably, the second SiCx layer 150 may be a SiCOxOy layer, which may be prepared from silane, hydrogen, methane, and carbon dioxide in a ratio of 1:100:0.5:0 to 1:10000:5:5, doped with phosphine gas at a gas content of 2% to 200%, at a temperature of 120-200 degrees Celsius.

[0050] In some embodiments, the first SiCx layer 130 is a p-type doped layer, and the second SiCx layer 150 is an n-type doped layer. Of course, in other preferred embodiments, the first SiCx layer 130 can be an n-type doped layer, and the second SiCx layer 150 can be a p-type doped layer, which can also form a SiCx layer. x p / n junction battery structure.

[0051] In some embodiments, the interface passivation layer 140 includes a silicon oxide layer with a thickness of 1-2 nm, an intrinsic amorphous silicon layer with a thickness of 1-3 nm, or an intrinsic SiC layer with a thickness of 1-3 nm. x Preferably, the interface passivation layer 140 may be an intrinsic amorphous silicon layer with a thickness of 1-3 nm to better adapt to the preparation process of the heterojunction battery.

[0052] In some embodiments, the connecting layer 120 is a tunneling layer comprising a 1-2 nm thick silicon oxide or a 1-3 nm thick intrinsic amorphous silicon layer. During fabrication, a 1-2 nm thick silicon oxide or 1-3 nm thick intrinsic amorphous silicon layer can be deposited on the front side of the heterojunction cell. This deposition method utilizes conventional PECVD equipment for low-temperature deposition at 160-220°C, using silane, carbon dioxide (silicon oxide layer), and hydrogen. For specific preparation details, refer to existing heterojunction fabrication protocols.

[0053] See also Figure 2 In other preferred embodiments of the present invention, the connecting layer 120 may also be a conventional conductive layer, including an ITO layer, a NIOx layer, or an AZO layer with a thickness of 2-20 nm. Specifically, the conductive layer may be prepared by PVD, RPD, or vapor deposition.

[0054] See Figure 1 and Figure 2In some embodiments, the heterojunction base cell 110 includes an n-type silicon substrate 111, a first intrinsic layer 112, a second intrinsic layer 113, a first microcrystalline silicon layer 114, and a second microcrystalline silicon layer 115. The n-type silicon substrate 111 has a first surface and a second surface; the first intrinsic layer 112 is arranged on the first surface; the second intrinsic layer 113 is arranged on the second surface; the first microcrystalline silicon layer 114 is arranged on the first intrinsic layer 112; and the second microcrystalline silicon layer 115 is arranged on the second intrinsic layer 113; wherein the first TCO layer 160 is arranged on a side of the second microcrystalline silicon layer 115 away from the n-type silicon substrate 111, and the connecting layer 120 is arranged on a side of the first microcrystalline silicon layer 114 away from the n-type silicon substrate 111, and the first microcrystalline silicon layer 114 and the second microcrystalline silicon layer 115 have different conductivity types. Specifically, the preparation process of the heterojunction substrate cell 110 is consistent with the conventional heterojunction preparation scheme, and is prepared through the following steps: n-type silicon wafer - texturing - deposition of intrinsic amorphous silicon on the back - deposition of intrinsic amorphous silicon on the front - deposition of boron-doped p-type microcrystalline silicon on the back - deposition of phosphorus-doped n-type microcrystalline silicon on the front (including silicon oxide and other schemes).

[0055] Furthermore, the first microcrystalline silicon layer 114 is an n-type microcrystalline silicon layer, and the second microcrystalline silicon layer 115 is a p-type microcrystalline silicon layer. In addition, the first intrinsic layer 112 and the second intrinsic layer 113 are both amorphous silicon layers.

[0056] In some embodiments, a first electrode layer 180 is provided on a side of the first TCO layer 160 away from the n-type silicon substrate 111, and a second electrode layer 190 is provided on a side of the second TCO layer 170 away from the n-type silicon substrate 111. Specifically, the first electrode layer 180 and the second electrode layer 190 are both metal electrodes that can be prepared by screen printing to achieve electrical connection with an external circuit.

[0057] See Figure 3 The present invention also provides a method for preparing a HJT stacked solar cell 100. The method comprises the following steps:

[0058] S1: preparing a heterojunction substrate cell 110 .

[0059] Specifically, a conventional heterojunction preparation scheme is first adopted, and an n-type silicon wafer is first provided. The first surface and the second surface of the n-type silicon wafer are textured, and then intrinsic amorphous silicon is deposited on the second surface to form a second intrinsic layer 113. Then, intrinsic amorphous silicon is deposited on the first surface to form a first intrinsic layer 112. Then, boron-doped p-type microcrystalline silicon is deposited on the second intrinsic layer 113 to form a second microcrystalline silicon layer 115. Finally, phosphorus-doped n-type microcrystalline silicon (including silicon oxide and other schemes) is deposited on the first intrinsic layer 112 to form a first microcrystalline silicon layer 114.

[0060] S2 : depositing a connection layer 120 on the heterojunction base cell 110 .

[0061] Specifically, after depositing the microcrystalline silicon layer on both sides, 1-2nm silicon oxide or 1-3nm intrinsic amorphous silicon can be deposited on the front side of the heterojunction base cell 110 as a tunneling layer; the above deposition scheme uses the original PECVD equipment for low-temperature deposition at 160-220 degrees Celsius, and is prepared by silane, carbon dioxide (silicon oxide layer) and hydrogen.

[0062] In other preferred embodiments of the present invention, when executing step S2, ITO\NIO with a thickness of 2-20 nm can also be prepared by PVD, RPD or evaporation. x \AZO and other conventional conductive layers.

[0063] S3 : depositing a first SiCx layer 130 on the connection layer 120 .

[0064] Specifically, a SiC layer with a thickness of 5-20 nm is deposited on the tunneling layer or the conductive layer. x It can be prepared by silane, hydrogen, and methane according to a gas content formula of 1:100:0.5-1:10000:5, doped with 2%-200% gas content of borane or TMB and other gases, and the temperature is 120-200 degrees Celsius.

[0065] S4 : depositing an interface passivation layer 140 on the first SiCx layer 130 .

[0066] Specifically, in the above-mentioned SiC x On this basis, a 1-2 nm silicon oxide layer, a 1-3 nm intrinsic amorphous silicon layer or a 1-3 nm intrinsic SiCx layer is continuously deposited as a subsequent interface passivation layer 140 .

[0067] S5 : depositing a second SiCx layer 150 on the interface passivation layer 140 .

[0068] Specifically, 5-20 nm SiC is deposited on the surface of the interface passivation layer 140. x or SiCO x O y The layer is prepared by mixing silane, hydrogen, methane and carbon dioxide in a ratio of 1:100:0.5:0 to 1:10000:5:5, doping 2% to 200% of phosphine gas, and heating at a temperature of 120 to 200 degrees Celsius.

[0069] S6: Depositing the first TCO layer 160 and the second TCO layer 170 .

[0070] Specifically, a second TCO layer 170 and a first TCO layer 160 are deposited on the surface of the second SiCx layer 150 and the surface of the second microcrystalline silicon layer 115, respectively, and screen printing is completed to form a first electrode layer 180 and a second electrode layer 190. The remaining steps can refer to the existing heterojunction steps.

[0071] In summary, the HJT stacked solar cell 100 provided by the embodiment of the present invention takes the heterojunction substrate cell 110 as the substrate, and sequentially deposits a connection layer 120, a first SiCx layer 130, an interface passivation layer 140, and a second SiCx layer 150 on the heterojunction substrate cell 110, thereby forming a SiC x p / n junction cell structure, SiC x As a semiconductor material, the band gap is 2.4eV, making SiC x The p / n junction cell has the advantages of a wide bandgap and high carrier mobility, and can better utilize the high-energy spectrum, making it a very good top-level cell structure. Furthermore, due to the stable material and structural characteristics of this top-level cell structure, the problem of UV attenuation caused by high-energy photons is avoided. Furthermore, the stacked structure is compatible with existing heterojunction equipment, requiring no additional equipment expenditure, reducing production costs and facilitating industrialization. Compared to the prior art, the HJT stacked solar cell 100 provided by the present invention can achieve better and more comprehensive light absorption by matching cells with different band gaps. At the same time, it has a stable structure, is compatible with existing heterojunction equipment, has a low manufacturing cost, and can avoid the problem of UV attenuation caused by high-energy photons.

[0072] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A HJT tandem solar cell, characterized in that: include: Heterojunction substrate cells; A first TCO layer (160) is provided on one side of the heterojunction substrate cell (110); A connection layer (120) is provided on a side of the heterojunction substrate cell (110) away from the first TCO layer (160), and the connection layer (120) is a tunneling layer or a conductive layer; A first SiCx layer (130) is provided on a side of the connection layer (120) away from the heterojunction substrate cell (110); An interface passivation layer (140) is provided on a side of the first SiCx layer (130) away from the heterojunction substrate battery (110); A second SiCx layer (150) is provided on a side of the interface passivation layer (140) away from the heterojunction substrate battery (110); A second TCO layer (170) is provided on a side of the second SiCx layer (150) away from the heterojunction substrate cell (110); The first SiCx layer (130) and the second SiCx layer (150) have different conductivity types.

2. The HJT tandem solar cell according to claim 1, characterized in that: The first SiCx layer (130) comprises SiC with a thickness of 5-20 nm. x layer.

3. The HJT tandem solar cell according to claim 1, characterized in that: The second SiCx layer (150) comprises SiC with a thickness of 5-20 nm. x or SiCO x O y layer.

4. The HJT tandem solar cell according to claim 1, characterized in that: The first SiCx layer (130) is a p-type doped layer, and the second SiCx layer (150) is an n-type doped layer.

5. The HJT tandem solar cell according to claim 1, characterized in that: The interface passivation layer (140) comprises a silicon oxide layer with a thickness of 1-2 nm, an intrinsic amorphous silicon layer with a thickness of 1-3 nm, or an intrinsic SiC layer with a thickness of 1-3 nm. x layer.

6. The HJT tandem solar cell according to claim 1, characterized in that: The connection layer (120) is a tunneling layer, and the tunneling layer includes a silicon oxide layer with a thickness of 1-2 nm or an intrinsic amorphous silicon layer with a thickness of 1-3 nm.

7. The HJT tandem solar cell according to claim 1, characterized in that: The connecting layer (120) is a conductive layer, which includes an ITO layer with a thickness of 2-20 nm, a NIO x layer or AZO layer.

8. The HJT tandem solar cell according to claim 1, characterized in that: The heterojunction substrate cell (110) comprises: An n-type silicon substrate (111), wherein the n-type silicon substrate (111) has a first surface and a second surface; a first intrinsic layer (112), disposed on the first surface; a second intrinsic layer (113), disposed on the second surface; A first microcrystalline silicon layer (114) is disposed on the first intrinsic layer (112); A second microcrystalline silicon layer (115) is disposed on the second intrinsic layer (113); The first TCO layer (160) is arranged on a side of the second microcrystalline silicon layer (115) away from the n-type silicon substrate (111), the connecting layer (120) is arranged on a side of the first microcrystalline silicon layer (114) away from the n-type silicon substrate (111), and the first microcrystalline silicon layer (114) and the second microcrystalline silicon layer (115) have different conductivity types.

9. The HJT tandem solar cell according to claim 8, characterized in that: The first microcrystalline silicon layer (114) is an n-type microcrystalline silicon layer, and the second microcrystalline silicon layer (115) is a p-type microcrystalline silicon layer.

10. The HJT tandem solar cell according to claim 8, characterized in that: A first electrode layer (180) is provided on a side of the first TCO layer (160) away from the n-type silicon substrate (111), and a second electrode layer (190) is provided on a side of the second TCO layer (170) away from the n-type silicon substrate (111).

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