Semiconductor packaging structure and ink box

Abstract

The utility model provides a semiconductor packaging structure and an ink box, the packaging structure comprises a first packaging substrate and a second packaging substrate, and the packaging substrate comprises a heat conduction layer; a first redistribution layer and a second redistribution layer; the upper surface of the chip set is connected to a first rewiring layer through solder, and the first rewiring layer is connected to the first packaging substrate; the lower surface of the chip set is connected to a second rewiring layer through a gasket, and the second rewiring layer is connected to the second packaging substrate; and the encapsulation layer is filled with an encapsulation adhesive, and the encapsulation adhesive wraps the first encapsulation substrate, the second encapsulation substrate and the chip set. According to the technical scheme of the invention, the composite packaging structure of the double diamond substrates, the heat conduction layers of the double diamond substrates and the aluminum silicon carbide gaskets is arranged, so that the heat dissipation efficiency of a chip product is greatly improved, the operation failure rate of a chip finished product is reduced, and the preset service life of the chip product is prolonged.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and an ink cartridge. Background Art

[0002] With the rapid development of printing consumable chip technology, related products are becoming increasingly diverse in functionality and miniaturized. Consequently, the density of consumable chips and functional components continues to increase, while critical device dimensions continue to shrink. This poses significant challenges to the semiconductor packaging industry. Despite the emergence of various packaging technologies, the heat dissipation problem of packaged devices has not been effectively addressed and is even showing a trend of worsening.

[0003] In order to solve the above problems, a technical solution of a semiconductor packaging structure and an ink cartridge is proposed. Utility Model Content

[0004] In order to overcome the existing problems, the present application provides a semiconductor packaging structure, comprising:

[0005] A first packaging substrate and a second packaging substrate, wherein the upper surface or the lower surface of the first or second packaging substrate is a heat-conducting layer, and the heat-conducting layer is made of a copper film or an aluminum film;

[0006] A chipset, wherein the upper layer of the chipset is a first redistribution layer, and the first redistribution layer is connected to the first package substrate; the lower layer of the chipset is a second redistribution layer, and the second redistribution layer is connected to the second package substrate via a gasket;

[0007] A potting layer is filled with potting glue, and the potting glue wraps the first packaging substrate, the second packaging substrate and the chipset.

[0008] Furthermore, the first redistribution layer is connected to the first package substrate via solder balls; the second redistribution layer is connected to the solder balls via gaskets and then connected to the second package substrate.

[0009] Furthermore, the power supply in the chipset is provided with a dedicated pin connected to the heat conducting layer. Preferably, the thickness of the first or second redistribution layer is 35 μm.

[0010] Preferably, the gasket is aluminum silicon carbide.

[0011] Preferably, the potting compound is a liquid polyurethane compound.

[0012] Preferably, the packaging substrate is a diamond substrate.

[0013] On the other hand, the present application provides an ink cartridge, which includes a circuit board and the above-mentioned semiconductor packaging structure, and the semiconductor packaging structure is mounted on the circuit board.

[0014] It can be seen from the above technical solutions that the present invention has at least the following advantages and positive effects compared with the prior art:

[0015] The packaging structure of the present application is a packaging structure of a double heat dissipation diamond substrate, a gasket and a thermal conductive layer, which greatly improves the thermal conductivity, prevents the heat of the chip power module from accumulating rapidly inside and causing damage to the components inside the chip, thereby increasing the service life of the chip; and because there are two thermal conductive layers, which are arranged on both sides of the packaging substrate, the thermal conductive layer on the packaging substrate away from the power module surface can be connected to an external heat sink when the ambient temperature is high, so that the chip can work under extreme conditions, thereby increasing the scope of application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0017] Figure 1 A schematic diagram of the overall structure of a semiconductor package structure provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of the connection structure between a power module and a package substrate of a semiconductor package structure provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the connection structure between a power module and a packaging substrate of another semiconductor packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] Example 1:

[0021] This embodiment provides a schematic diagram of the overall structure of a semiconductor packaging structure, such as Figure 1 As shown, it includes a chip body 10 , a first packaging substrate 20 , a second packaging substrate 30 , a potting layer 40 , a gasket 50 , solder balls 60 , a first redistribution layer 101 , and a second redistribution layer 102 .

[0022] The first packaging substrate 20 and the second transfer substrate 30 are diamond substrates. The thermal expansion coefficient of diamond is about 1.1×10 -6 / °C, a characteristic that closely matches the thermal expansion coefficient of semiconductor materials. This minimizes thermal stress between the chip and the diamond heat sink during temperature fluctuations. This significantly reduces the risk of packaging material deformation and cracking caused by differential thermal expansion, effectively safeguarding the stability and reliability of the package structure.

[0023] The upper and lower surfaces of the diamond substrate serve as thermally conductive layers. This layer can be made of aluminum or copper film. Combined with the inherent heat dissipation properties of the diamond substrate, it creates a double-strengthened heat dissipation foundation for the chip. Heat generated by the chip during operation is rapidly transferred through the thermally conductive layers to the substrate, and then to the external environment or a heat sink connected to the substrate.

[0024] Furthermore, the potting material within the potting layer 40 is a liquid polyurethane composite, and the gasket 50 is made of aluminum silicon carbide. The gasket 50 improves the conduction efficiency of heat generated by the chip body 10, preventing rapid heat accumulation within the chip body 10 and damaging internal components of the chip body 10. In addition to their inherent plastic encapsulation and electrical connection functions, the potting layer 40 and gasket 50 also improve thermal conductivity, thereby enhancing heat dissipation.

[0025] Preferably, the first or second redistribution layer is three layers with a total thickness of 20-45 um.

[0026] Furthermore, the power element of the chip body 10 is an IGBT module, and the IGBT module includes a freewheeling diode.

[0027] Example 2:

[0028] This embodiment provides a schematic diagram of the connection structure between the power module and the heat conducting layer of the semiconductor packaging structure. Figure 2 As shown, the power module 1000 includes a first P-type transistor 1001 , a second P-type transistor 1002 , a freewheeling diode 1003 , a first packaging substrate 201 , and a second packaging substrate 301 .

[0029] Furthermore, the first P-type transistor 1001 and the second P-type transistor 1002 are coupled to form the control electrode C, gate electrode g, emitter electrode e and drain electrode d of the power module 1000. The power module is connected to the first packaging substrate 201 and the second packaging substrate 301 after shunting the current through the drain electrode d. The first packaging substrate 201 or the second packaging substrate 301 is a diamond substrate, so it can have at least a double heat dissipation effect on the power module 1000.

[0030] Example 3:

[0031] This embodiment provides a schematic diagram of the connection structure between the power module and the heat conducting layer of the semiconductor packaging structure. Figure 3 As shown, the power module 1000 includes a first P-type transistor 1001 , a second P-type transistor 1002 , a freewheeling diode 1003 , a first packaging substrate 201 and a first heat conducting layer 2011 , a second packaging substrate 301 and a second heat conducting layer 3011 .

[0032] Furthermore, the first P-type transistor 1001 and the second P-type transistor 1002 are coupled to form the control electrode C, gate electrode g, emitter electrode e and drain electrode d of the power module 1000. The power module is connected to the first packaging substrate 201 and its first thermal conductive layer 2011, the second packaging substrate 301 and its second thermal conductive layer 3011 through the drain electrode d and after current is shunted. The first thermal conductive layer 2011 and the second thermal conductive layer 3011 can be made of aluminum film or copper film. The first packaging substrate 201 or the second packaging substrate 301 is a diamond substrate, and an external heat dissipation device can be connected to the thermal conductive layer on the side of the diamond substrate not connected to the power module as needed to enhance the heat dissipation effect.

[0033] Finally, it should be noted that the above embodiments are merely examples for the purpose of illustrating the present invention and are not intended to limit the embodiments. Those skilled in the art will readily appreciate that other variations or modifications based on the above description are possible. It is not necessary and impossible to provide an exhaustive list of all possible embodiments. However, any obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: A first packaging substrate and a second packaging substrate, wherein the upper surface or the lower surface of the first or second packaging substrate is a heat conducting layer; A chipset, wherein the upper layer of the chipset is a first redistribution layer, and the first redistribution layer is connected to the first package substrate; the lower layer of the chipset is a second redistribution layer, and the second redistribution layer is connected to the second package substrate via a gasket; A potting layer is filled with potting glue, and the potting glue wraps the first packaging substrate, the second packaging substrate and the chipset.

2. The semiconductor package structure according to claim 1, wherein: The first redistribution layer is connected to the first package substrate via solder balls; the second redistribution layer is connected to the solder balls via gaskets and then to the second package substrate.

3. The semiconductor package structure according to claim 1, wherein: The drain of the transistor group of the power module in the chipset is connected to the heat conduction layer of the packaging substrate.

4. The semiconductor package structure according to claim 1 or 2, wherein: The thickness of the first or second redistribution layer is 35 μm.

5. The semiconductor package structure according to claim 1 or 2, wherein: The gasket is aluminum silicon carbide.

6. The semiconductor package structure according to claim 1, wherein: The potting glue is a liquid polyurethane compound.

7. The semiconductor package structure according to claim 1, wherein: The packaging substrate is a diamond substrate.

8. The semiconductor package structure according to claim 1, wherein: The heat conducting layer is made of copper film or aluminum film.

9. An ink cartridge, characterized in that: The ink cartridge includes a circuit board and a semiconductor package structure according to any one of claims 1 to 6, wherein the semiconductor package structure is mounted on the circuit board.

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