Semiconductor structure

Abstract

A semiconductor structure may include a first substrate having a front surface and a back surface opposite the front surface. The semiconductor structure may include an element on the front surface. The semiconductor structure may include a first internal connection structure on the front surface and coupled to the element. The semiconductor structure may include a thermal distribution layer on the front surface and electrically insulated from the first interconnect structure. The heat distribution layer includes a thermally conductive material. The semiconductor structure may include a second substrate and be coupled to the first substrate on the front surface. The semiconductor structure may include a second internal connection structure on the backside and coupled to the element.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure. Background Art

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the density of integrated circuits containing various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, these improvements in integration density come from the continuous reduction of minimum feature sizes (e.g., shortening semiconductor process nodes to sub-nanometer nodes), which allows more components to be integrated into a given area. With the recent increase in demand for miniaturization, higher speeds, and greater bandwidth with lower power consumption and latency, the demand for packaging technologies that can shrink semiconductor dies and improve performance will also increase. Utility Model Content

[0003] According to at least one embodiment of the present disclosure, a semiconductor structure includes a first substrate having a front surface and a back surface opposite the front surface. A plurality of components are disposed on the front surface. A plurality of first interconnect structures are disposed on the front surface and coupled to the components. A heat distribution layer is disposed on the front surface and electrically insulated from the first interconnect structures. A second substrate is disposed on the front surface and coupled to the first substrate. A plurality of second interconnect structures are disposed on the back surface and coupled to the components.

[0004] According to at least one embodiment of the present disclosure, a semiconductor structure includes a first substrate having a front surface and a back surface opposite the front surface. A plurality of components are disposed on the front surface. A plurality of first interconnect structures are disposed on the front surface and coupled to the components. A plurality of second interconnect structures are disposed on the back surface and coupled to the components. A second substrate is coupled to the back surface such that the second interconnect structures are interposed between the first substrate and the second substrate. A via extends through the second substrate and is coupled to the second interconnect structures.

[0005] According to at least one embodiment of the present disclosure, a semiconductor structure includes a first substrate having a front surface and a back surface opposite the front surface; a plurality of components on the front surface; a plurality of first interconnect structures on the front surface and coupled to the plurality of components; a heat distribution layer on the front surface and electrically insulated from the plurality of first interconnect structures; a second substrate on the front surface and coupled to the first substrate, wherein the second substrate directly contacts the heat distribution layer; and a plurality of second interconnect structures on the back surface and coupled to the plurality of components. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 are cross-sectional views of respective portions of exemplary semiconductor packages according to some embodiments;

[0008] Figure 9 is a flow chart of an example method for manufacturing a semiconductor package according to some embodiments;

[0009] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 and Figure 20 According to some embodiments, Figure 9 Cross-sectional view of a portion of an example semiconductor package showing an intermediate step of a method.

[0010]

Explanation of symbols

[0011] 200-1: Grain

[0012] 200-2: Grain

[0013] 200-3: Grain

[0014] 200A:Package

[0015] 200B:Package

[0016] 200C:Packaging

[0017] 200D:Packaging

[0018] 200E: Encapsulation

[0019] 200F:Packaging

[0020] 200G: Packaging

[0021] 200H:Package

[0022] 202:Substrate

[0023] 202A: Front

[0024] 202B: Back

[0025] 205: Component Features

[0026] 206: Component Features

[0027] 207A: Internal connection structure

[0028] 208A: Internal connection structure

[0029] 208B: Internal connection structure

[0030] 209A: Internal connection structure

[0031] 210A: Metallization layer

[0032] 210B: Metallization layer

[0033] 211A: Metallization layer

[0034] 211B: Metallization layer

[0035] 212: Heat distribution layer

[0036] 214: bonding layer

[0037] 215: dielectric layer

[0038] 216: Through hole

[0039] 217: Through hole

[0040] 218: Wire

[0041] 219: Wire

[0042] 220: carrier substrate

[0043] 222: Bonding layer

[0044] 224: Heat distribution layer

[0045] 226: dummy via

[0046] 227: Through hole

[0047] 228:Dummy wire

[0048] 229: Wire

[0049] 230:Back substrate

[0050] 232: Peeling layer

[0051] 234:Carrier substrate

[0052] 240: Through hole

[0053] 250:Electrical connector

[0054] 260: Component substrate

[0055] 260A: Front

[0056] 260B: Back

[0057] 266: Component Features

[0058] 270: Metallization layer

[0059] 272: Inner connection structure

[0060] 300: Method

[0061] 302: Operation

[0062] 304: Operation

[0063] 306: Operation

[0064] 308: Operation

[0065] 310: Operation

[0066] 320: Operation

[0067] 322: Operation

[0068] 324: Operation

[0069] 330: Operation

[0070] 400: Encapsulation

[0071] BM 0: Metallization layer

[0072] M0: Metallization layer

[0073] M n :Metalization layer DETAILED DESCRIPTION

[0074] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. In addition, in various examples, the disclosure may repeat reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0075] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and likewise, the spatially relative descriptors used herein may be interpreted accordingly. As used herein, terms such as "about" and "approximately" or the like mean between plus or minus 10% of the stated value. For example, about 0.5 may include 0.45 and 0.55, about 10 may include 9 to 11, and about 1000 may include 900 to 1000.

[0076] Generally speaking, the fabrication of semiconductor devices is a combination of front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. The front-end process involves manufacturing semiconductor (e.g., silicon) dies, while the back-end process involves packaging one or more of these dies into a semiconductor device that interfaces with other components. For example, a package may contain multiple semiconductor dies and may be configured to be attached to a printed circuit board or other interconnect substrate, which in turn allows the multiple semiconductor dies of a semiconductor device to be connected to further semiconductor devices or other components, power supplies, communication channels, etc.

[0077] As used herein, a semiconductor die (or simply die) refers to a portion of a semiconductor wafer having one or more active circuits such as transistors, logic devices, analog devices such as RF devices or filters, diodes, other circuit components, or a combination thereof. Conductive features (e.g., vias and conductive lines) interposed between the active surfaces may be formed in one or more dielectric layers to form a plurality of metallization layers.

[0078] The physical demands of miniaturization, improved connectivity, and power efficiency are driving increases in semiconductor device density. In terms of density, some of these improvements can be attributed to improvements in front-end processes, including die miniaturization. Advanced packaging technologies, such as package on package (PoP), fan-out packaging (FO), and system-on-intergrated-chip (SoIC), are also driving miniaturization, intercommunication, power savings, and other improvements. One or more dies in these advanced packages can be interconnected or connected to package inputs and / or outputs (I / Os) by bonding wires, through-silicon (or through-substrate) vias (TSVs), interconnect structures (such as vias and wires disposed in various dielectric layers) coupled to the silicon die, hybrid bonding vias through bonding interface layers, solder balls, other bonding methods, or combinations thereof. Although these connections use complex technologies, further improvements are needed to stay ahead of the state-of-the-art.

[0079] For example, in conventional packages (including power trace structures formed on both the front and back sides of a device substrate), metallization layers are typically positioned along the heat dissipation path between the device substrate and the heat sink. In this regard, heat dissipation is blocked by the metallization layers (e.g., their dielectric materials), resulting in higher thermal resistance and higher temperatures compared to packages with metallization layers on only one side (e.g., the front side). This embodiment generally relates to a structure that can be integrated with conventional packages to achieve reduced thermal resistance on the front and / or back side metallization layers.

[0080] Figures 1 to 8 are cross-sectional views of at least a portion of a semiconductor package (or chip) 200A to 200H, respectively, according to various embodiments. It is to be understood that an exemplary semiconductor package is Figures 1 to 8 Packages 200A through 200H are merely illustrative examples and are not intended to limit the scope of the present disclosure. Thus, example semiconductor packages 200A through 200H may include various other components (e.g., an interposer, one or more through-silicon vias, an underfill material, an encapsulant material, etc.) while remaining within the scope of the present disclosure.

[0081] refer to Figure 1, a semiconductor package (or simply package), the package 200A includes a die 200-1 bonded to a carrier substrate 220 via a bonding layer 214. In this embodiment, the die 200-1 includes at least one device substrate 202 and a plurality of active and / or passive device features 206 (e.g., transistors, resistors, capacitors, etc.) formed along the front surface 202A of the device substrate 202 (or formed on the front surface 202A of the device substrate 202). The die 200-1 also includes a plurality of front metallization layers 210A (e.g., front metallization layer M0, front metallization layer M1, front metallization layer M2 to front metallization layer M3). n , where n is a positive integer) coupled to the device features 206 on the front side 202A, and some back metallization layers 210B (e.g., back metallization layer BM0, back metallization layer BM1, back metallization layer BM2 to back metallization layer BM n , where n is a positive integer) is coupled to device features 206 on the back side 202B of the device substrate 202, opposite the front side 202A. In this regard, the carrier substrate 220 is bonded to the front side 202A. As used herein, the term "coupled" includes physical, electrical, and / or other operational connections between two components as appropriate. Additionally, on the front side 202A of the device substrate 202, the die 200-1 may optionally include a redistribution layer (not depicted) configured to redirect or redistribute portions of the front side metallization layer 210A.

[0082] In some implementations, the device substrate 202 and the carrier substrate 220 each comprise a semiconductor material, such as silicon (doped or undoped) or an active layer of a semiconductor-on-insulator substrate. The device substrate 202 and the carrier substrate 220 may comprise other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide, or combinations thereof. Other substrates (such as multilayer or gradient substrates) may also be used. In this embodiment, the front side 202A of the device substrate 202 is configured as an active surface and is located above the location where the device features 206 are formed, while the back side 202B is configured as a non-active surface opposite the active surface. In this embodiment, the carrier substrate 220 does not include any device features and may be configured to support the die 200-1 during subsequent manufacturing steps.

[0083] Device features 206 can include any suitable active or passive devices formed along the front surface 202A of the device substrate 202. In some embodiments, device features 206 include a plurality of transistors, such as fin field-effect transistors (FinFETs), nanometer-layer transistors, gate-all-around transistors (GAA), forked-layer transistors, complementary field-effect transistors (CFETs), the like, or combinations thereof. In this embodiment, device features 206 are coupled to front metallization layer 210A and back metallization layer 210B. For example, device features 206 can be coupled to backside interconnect structures 208B via through-substrate vias (or through-silicon vias, not separately depicted).

[0084] Each of the front and back metallization layers 210A and 210B may include a plurality of conductive lines 218 and a plurality of vias 216 disposed in one or more dielectric layers (not depicted), and collectively referred to as front and back interconnect structures 208A and 208B, respectively. In some embodiments, the conductive lines 218 are each formed as a conductive (e.g., metal) structure extending in a lateral direction (e.g., the X direction or the Y direction), while the vias 216 are each formed as a conductive (e.g., metal) structure extending in a longitudinal direction (e.g., the Z direction). Some device features 206 may be operatively coupled to one another (e.g., via respective groups of front and back interconnect structures 208A and 208B) to provide respective functions (e.g., Boolean logic functions).

[0085] In some implementations, the interconnect structures 208A and 208B include a conductive material such as copper, tungsten, aluminum, silver, gold, the like, or combinations thereof. The one or more dielectric layers of the metallization layers 210A and 210B may include any suitable material, such as silicon oxide, a low-k material (e.g., having a lower k than silicon oxide (approximately 3.9)) such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS)-based oxides, the like, or combinations thereof.

[0086] In this embodiment, die 200-1 further includes a heat distribution layer 212 disposed between front surface interconnect structure 208A and carrier substrate 220. Heat distribution layer 212 comprises any suitable thermally conductive material, such as silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, aluminum, copper, gallium, germanium, gold, iron, magnesium, nickel, platinum, silver, titanium, tungsten, zinc, or combinations thereof. In some embodiments, heat distribution layer 212 is compositionally homogeneous and comprises a single material. In some embodiments, heat distribution layer 212 is compositionally heterogeneous and comprises at least two of the aforementioned materials. For example, heat distribution layer 212 may comprise a metal layer disposed on (or adjacent to) a non-metal layer.

[0087] In some embodiments, the heat distribution layer 212 is disposed in a dielectric layer 215 above the front interconnect structure 208A. In some embodiments, the heat distribution layer 212 and the dielectric layer 215 are together part of the front metallization layer 210A. The dielectric layer 215 can have a similar composition as the dielectric layers of the metallization layers 210A and 210B described above. In some embodiments, the thermal conductivity of the heat distribution layer 212 is higher than the thermal conductivity of the dielectric layer 215 and / or the thermal conductivity of the dielectric layers of the metallization layers 210A and 210B. In some embodiments, the thermal conductivity of the heat distribution layer 212 is higher than the thermal conductivity of the front interconnect structure 208A. In some embodiments, the thermally conductive material can also be an electrically conductive material, such as any of the metals described above. In some embodiments, the thermally conductive material of the heat distribution layer 212 has the same composition as the thermally conductive material of the interconnect structures 208A and 208B.

[0088] In some embodiments, the thermally conductive material of the heat distribution layer 212 can be an electrically insulating material or a semiconductor material, such as any of the semiconductor materials or dielectric materials described above. For embodiments in which the thermally conductive material is also an electrically conductive material, the heat distribution layer 212 is physically and / or electrically isolated from (e.g., not in physical or electrical contact with) the front surface interconnect structures 208A. For embodiments in which the thermally conductive material is also an electrically insulating material or a semiconductor material, the heat distribution layer 212 can be physically or electrically coupled to the front surface interconnect structures 208A. Alternatively, the heat distribution layer 212 can be physically and / or electrically isolated from the front surface interconnect structures 208A by including a thermally conductive material that is either an electrically insulating material or a semiconductor material. As described in more detail below, the heat distribution layer 212 improves the dissipation path for heat generated during operation of the device features 206.

[0089] In some embodiments, as depicted, the bonding layer 214 is disposed between the heat distribution layer 212 and the carrier substrate 220. In some embodiments, the bonding layer 214 is removed and the heat distribution layer 212 is directly in contact with a surface of the carrier substrate 220 (e.g., adjacent to the bottom surface of the device substrate 202). The bonding layer 214 can include any suitable material, such as an oxide material.

[0090] When the carrier substrate 220 comprises a semiconductor material (i.e., having a better thermal conductivity than the dielectric layer of the front metallization layer 210A), it typically acts as a heat sink for the device features 206. In this regard, the heat distribution layer 212 (a uniform layer configured as a thermal conductor integrated with the front metallization layer 210A) enables any heat blocked by the front metallization layer 210A to be more efficiently transferred to the carrier substrate 220, thereby reducing the thermal resistance of the front metallization layer 210A. In addition, when the bonding layer 214 typically comprises a thermally insulating material (such as an oxide), placing the heat distribution layer 212 adjacent to the bonding layer 214 can improve the removal of accumulated heat before it reaches the heat sink (the carrier substrate 220). This will be described in more detail below (e.g., Figure 4 ), depending on the structure of the package on the back side 202B, a heat distribution layer similar to the heat distribution layer 212 can be integrated with the back side metallization layer 210B to achieve a similar effect on the back side 202B.

[0091] refer to Figure 2 Package 200B is depicted as including a die 200-1 bonded (or joined) to a carrier substrate 220, similar to the package 200A described above. In some embodiments, die 200-1 is bonded to carrier substrate 220 via a bonding layer 214. However, unlike package 200A, package 200B also includes a backside substrate 230 bonded to backside metallization layer 210B. In other words, backside metallization layer 210B is disposed between component substrate 202 and backside substrate 230. In some embodiments, although not depicted, backside substrate 230 is bonded to backside metallization layer 210B via a bonding layer similar to bonding layer 214 described above.

[0092] In this embodiment, also refer to Figure 2 , package 200B includes a plurality of vias 240 (e.g., through-silicon vias) encapsulated within (i.e., extending through) a back substrate 230. The vias 240 physically and / or electrically couple the back surface interconnect structure 208B to a plurality of electrical connectors 250 configured to couple the die 200-1 to other dies or the package substrate. In some embodiments, the back substrate 230 is an intermediary configured to connect the die 200-1 to other dies similarly coupled to the back substrate 230. In some embodiments, each via 240 is coupled to a corresponding electrical connector 250, as depicted.

[0093] In this embodiment, back substrate 230 comprises one or more thermally conductive materials selected from silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, gallium, and germanium. In some embodiments, back substrate 230 can be any conductive material, such as a metal. In some embodiments, back substrate 230 comprises silicon, similar to device substrate 202 and carrier substrate 220. In this regard, back substrate 230 can be configured as an additional heat sink on back surface 202B, allowing heat to be dissipated from the back surface of device features 206. Vias 240 can comprise any suitable electrically conductive or thermally conductive material (such as copper, tungsten, aluminum, silver, gold, the like, or combinations thereof), and can have a similar composition to interconnect structures 208A and 208B. Thus, vias 240 electrically couple back interconnect structures 208B to electrical connector 250, and subsequently to additional chips or dies through back substrate 230. It is worth noting that in this embodiment, the back substrate 230 does not include any device features, active or passive devices, formed along any surface thereof, which makes it different from the device substrate 202 of the die 200 - 1 .

[0094] The electrical connector 250 may include a ball grid array (BGA) connector, solder bumps, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, the like, or a combination thereof. The electrical connector 250 may be coupled to the corresponding via 240 by suitable means, such as under-bump metallizations (UBM, not depicted). Additionally, on the front side 202A of the device substrate 202, the die 200-1 may optionally include a redistribution structure (not depicted) disposed on the redirected or redistributed portion of the front side metallization layer 210A.

[0095] Similar to the effect of the carrier substrate 220, the backside substrate 230 can act as a heat sink or intermediate thermal conductor for the device features 206 at the backside 202B. This improved heat dissipation at the backside 202B can additionally enhance the improved heat dissipation provided by the heat distribution layer 212 at the frontside 202A, as depicted in the package 200A.

[0096] Additionally, in existing embodiments, electrical connectors (such as those depicted herein) are laterally separated by dielectric materials (e.g., low-k dielectric materials, similar to those of metallization layers 210A and 210B) for electrical isolation purposes. These dielectric materials thermally insulate the interface between any backside metallization layers and the electrical connectors. Furthermore, heat generated by device features 206 has only a limited conduction path through the electrical connectors due to their small contact area with the backside metallization layer (compared to the metallization layer itself, e.g., compared to the diameter of a flip-chip interconnect bump, which can control the height of the collapsed solder joint).

[0097] In this embodiment, however, the back substrate 230 disposed between the back metallization layer 210B and the electrical connectors 250 comprises a semiconductor material (e.g., silicon). While still an electrical insulator, it generally has a higher thermal conductivity than the dielectric material used in prior art embodiments. In this regard, the back substrate 230 can provide horizontal heat dissipation (e.g., along the X or Y direction) without generating substantial electrical conduction (between adjacent electrical connectors 250), thereby improving heat dissipation at the back surface 202B.

[0098] In some embodiments, the back substrate 230 may be implemented on the front side 202A independently of the heat distribution layer 212. For example, referring to Figure 3 , package 200C is depicted as having a similar structure to package 200B, except that the heat distribution layer 212 is removed from the front side 202A. In this regard, thermal dissipation is primarily improved due to the presence of a backside substrate 230 disposed on the back side 202B, as described in detail above.

[0099] refer to Figure 4 Package 200D is depicted as having a similar structure to package 200B except for the addition of a heat distribution layer 224 disposed between back metallization layer 210B and back substrate 230. In this regard, vias 240 extend through heat distribution layer 224 as well as back substrate 230 to couple back interconnect structure 208B to electrical connector 250. Heat distribution layer 224 is similar to heat distribution layer 212 in composition and structure. For example, heat distribution layer 224 may include at least one thermally conductive material having a greater thermal conductivity than the dielectric material in the adjacent metallization layers 210A and 210B. Examples of thermally conductive materials are described in detail above. Heat distribution layer 224 may further facilitate heat dissipation near dielectric components, such as bonding layer 222, which couples back substrate 230 to device substrate 202. In some embodiments, the heat distribution layer 212 comprises an electrically insulating thermally conductive material, while the heat distribution layer 224 comprises an electrically conductive thermally conductive material to provide interconnection between the backside interconnect structure 208B and any other die or wafer bonded to the electrical connector 250 .

[0100] refer to Figure 5 , package 200E is depicted as a system integrated chip structure, which includes an embodiment in which die 200 - 1 is an upper die (considered as upper die 200 - 1 in package 200E) and is bonded to die 200 - 2 is a lower die (considered as lower die 200 - 2 in package 200E) via a bonding layer 222 .

[0101] The composition of the upper die 200-1 is as described above. For example, Figure 5 As depicted, the upper die 200 - 1 includes a device substrate 202 , a front side metallization layer 210A, a back side metallization layer 210B, a heat distribution layer 212 , and a carrier substrate 220 bonded to the front side 202A via a bonding layer 214 .

[0102] As depicted, the lower die 200-2 includes a device substrate 260 having a front side 260A (e.g., an active side) opposite a back side 260B. A plurality of device features 266 are formed along the front side 260A. The lower die 200-2 also includes a front side metallization layer 270 disposed on the front side 260A and coupled to the device features 266. The front side metallization layer 270 includes a plurality of front side interconnect structures 272. The depicted features of the lower die 200-2 are similar to those of the upper die 200-1 described above. For example, the device substrate 260, the device features 266, and the front side metallization layer 270 (and the resulting front side interconnect structures 272) may be similar to the device substrate 202, the device features 206, and the metallization layers 210A and 210B, respectively. In some embodiments, although not depicted, the lower die 200-2 includes additional features consistent with applications that desire system integration chip structures. For example, the lower die 200-2 may include vias (eg, through silicon vias or through substrate vias) extending through the device substrate 260 to electrically couple a portion (eg, backside interconnect structure 208B) of the upper die 200-1 to a portion (eg, device feature 266) of the lower die 200-2.

[0103] In this embodiment, the upper die 200-1 is bonded to the back surface 260B of the component substrate 260 via a bonding layer 222, which is similar to the bonding layer 214 described above. Therefore, the component substrate 260 can be configured as a heat sink for the back surface of the upper die 200-1 in a manner similar to the back surface substrate 230 of any of the packages 200B, 200C, and 200D described above.

[0104] refer to Figure 6, package 200F is depicted as having a similar structure to package 200A, except that the front side metallization layer 210A of package 200F includes dummy metal features in one or more of the front side metallization layers 210A, which enable additional heat conduction paths to be provided from the device substrate 202 to the heat sink, which may include a carrier substrate 220 and a heat distribution layer 212 (if included). For example, as in Figure 6 As depicted, die 200 - 1 includes dummy vias 226 and dummy conductive lines 228 , collectively referred to as dummy metal features.

[0105] In some embodiments, the dummy vias 226 and the dummy conductive lines 228 are configured to have larger dimensions than their functional counterparts (i.e., the vias 216 and the conductive lines 218). For example, each dummy via 226 may have a larger width (e.g., a lateral dimension along the X-direction and / or the Y-direction) than each via 216, and each dummy conductive line 228 may have a larger thickness (e.g., a vertical dimension along the Z-direction) than each conductive line 218. In some embodiments, the dimensions of the dummy metal features are from the front metallization layer M0 to the front metallization layer M1. n Increases (the closer to the heat sink, such as the carrier substrate 220, as provided herein).

[0106] In some embodiments, the dummy metal features increase the density of the total metal features in the front metallization layer 210A by approximately 40% to approximately 85%. In some embodiments, the presence of the dummy vias 226 increases the density of vertical interconnect structures (including vias 216 and dummy vias 226) in the front metallization layer 210A by, for example, approximately 1%, 3%, or 5%. It is noteworthy that the density of vertical interconnect structures (e.g., vias) in conventional embodiments (without dummy metal features) is typically less than approximately 1%. The increased number of dummy metal features (e.g., dummy vias 226) provides additional vertical heat exchange (or heat conduction) paths from the device features 206 (i.e., the device substrate 202), enabling more efficient heat dissipation toward the carrier substrate 220 and / or the heat distribution layer 212 (if included).

[0107] In some embodiments, dummy metal features can be placed in any suitable location on the front metallization layer 210A without affecting (or significantly affecting) the operation of the functional circuit or violating any design rules. In some examples, the dummy metal features can be electrically coupled to an electrical supply. Alternatively, the dummy metal features can be insulated from the electrical supply and treated as "floating" features. In some examples, the dummy metal features can be placed in (or adjacent to) locations where high heat energy is generated (treated as hot spots) in the die 200-1. Alternatively, or more preferably, the dummy metal features can be placed in the back metallization layer 210B to improve heat dissipation on the back side 202B.

[0108] refer to Figure 7 , package 200G is depicted as including a die 200-3 bonded to a carrier substrate 220. Die 200-3 includes a device substrate 202 having a front side 202A and a back side 202B, a plurality of device features 205 on front side 202A, a front side metallization layer 211A, and a back side metallization layer 211B. As depicted, each front side metallization layer 211A includes a plurality of front side interconnect structures 207A, which also include vias 217 and conductive lines 219. Die 200-3 differs from die 200-1 in any of packages 200A through 200F in that the device features 205 are part of various standard cell structures, some of which are configured for high clock frequency applications such as clock trees, clock gating, high-speed channels, memory read / write ports, and the like. Such a standard cell may become a hotspot during operation and may therefore benefit from additional metal features in the front metallization layer 211A, in a similar manner to how the device feature 206 benefits from dummy metal features (e.g., dummy via 226 and dummy conductive line 228).

[0109] In this embodiment, the front metallization layer 211A further includes a front-side interconnect structure 209A coupled to the front-side interconnect structure 207A. The front-side interconnect structure 209A includes a plurality of vias 227 and conductive lines 229. The front-side metallization layer 211A is configured to provide additional heat exchange (or heat conduction) paths for the standard cells on the device substrate 202. Therefore, the vias 227 and conductive lines 229 are collectively considered as heat-sensitive metal features in the front-side metallization layer 211A.

[0110] As in Figure 7 As depicted, the thermally-aware metal features can have larger dimensions (e.g., width or thickness) than the vias 217 and conductive lines 219, thereby increasing the overall metal feature density disposed on the front side 202A. In contrast to the dummy metal features of die 200-1, the thermally-aware metal features can be coupled to the front side interconnect structures 207A during the circuit design phase to ensure their placement complies with the design rules of the standard cells in die 200-3.

[0111] In some embodiments, although not depicted, package 200F and package 200G may each additionally include a heat distribution layer (similar to heat distribution layer 212 of package 200A) and be integrated with front metallization layer 210A and front metallization layer 211A, respectively. In some embodiments, package 200F and package 200G may each be coupled to a back substrate (similar to back substrate 230 of package 200B) or to another die (similar to bottom die 200-2 of package 200E).

[0112] refer to Figure 8, package 200H includes a heat distribution layer 212, a backside substrate 230 coupled to an electrical connector 250, and dummy metal features as depicted in package 200A, any of packages 200B through 200D, and 200F, respectively. In this regard, heat dissipation can be achieved through the front side 202A of the device feature 206 and the back side 202B of the device feature 206, thereby reducing the overall thermal envelope and the temperature of the die 200-1 during operation.

[0113] Figure 9 Figure 9 FIG. 4 is a flow chart of an exemplary method 300 for forming at least a portion of a package 400 according to some embodiments of the present disclosure. The package 400 may include packages 200A to 200H (as described above, respectively). Figures 1 to 9 Figure 9 ) similar features. Therefore, for the sake of brevity, reference numbers for features described in packages 200A to 200H will be repeated in the discussion of method 300. It is worth noting that method 300 is merely an example and is not intended to limit the present disclosure. Therefore, it is understood that the order of operations in method 300 may be changed, some operations may be deleted, and additional operations may be provided before (or during or after) method 300. According to some embodiments provided herein, the operations of method 300 will be discussed and compared. Figures 10 to 20 Make the connection.

[0114] refer to Figure 10 , the method 300 forms the device feature 206 on the device substrate 202 at operation 302 .

[0115] The device substrate 202 can be part of a substrate wafer (not depicted) that can include semiconductor material. The device features 206 can be first formed on the device wafer and then cut to form a die 200-1 that includes, among other things, the device substrate 202. In some embodiments, the device substrate 202 includes silicon (e.g., a silicon wafer). In some embodiments, the device substrate 202 can be doped with a suitable dopant, depending on the type of device features 206 formed thereon. The device substrate 202 includes a front side 202A opposite a back side 202B, wherein the device features 206 are formed along the front side. The device features 206 can be formed on the device substrate 202 by some process, including deposition, lithography, etching, other suitable processes, or a combination thereof.

[0116] refer to Figure 11 In operation 304 , the method 300 forms a front side metallization layer 210A (or a front side metallization layer 211A) including a front side interconnect structure 208A (or a front side interconnect structure 207A or a front side interconnect structure 209A) over the front side 202A of the device substrate 202 .

[0117] Each front-side metallization layer 210A (or front-side metallization layer 211A) includes a plurality of front-side interconnect structures 208A (or front-side interconnect structures 207A or front-side interconnect structures 209A) formed on one or more dielectric layers (e.g., inter-layer dielectric layers or inter-metal dielectric layers, not separately depicted) as described in detail above, and configured to electrically connect device features 206 to additional circuit components on die 200-1 or other dies. As described in detail above, front-side interconnect structures 208A and front-side interconnect structures 207A include a plurality of vias (e.g., via 216 and via 217) and conductive lines (e.g., conductive lines 218 and conductive lines 219). In some examples, the dielectric layers may include a low-k dielectric material that is configured to be a thermal and electrical insulator (i.e., having low thermal conductivity and low electrical conductivity).

[0118] The front metallization layer 210A (or front metallization layer 211A) can be formed by one or more damascene processes or a series of deposition and patterning processes. For example, the damascene process may include depositing a dielectric layer on the device substrate 202, patterning the dielectric layer by lithography to form one or more openings in the dielectric layer, depositing a conductive material as described above to fill the openings, and performing one or more planarization processes (such as chemical mechanical polishing / planarization (CMP) processes) to form each front metallization layer 210A (or metallization layer 211A). In some embodiments, the patterning of the dielectric layer can be adjusted so that the openings can be formed with different sizes, allowing the formation of front interconnect structures (such as dummy metal features and heat-sensitive metal features) of different sizes. Although not depicted, other features (such as a passivation layer and / or a redistribution structure) can be subsequently formed on the front metallization layer 210A.

[0119] In some embodiments, forming the front metallization layer 210A includes forming dummy metal features (i.e., dummy vias 226 and dummy conductive lines 228), such that the structure of package 400 is similar to that of package 200F described above. In some embodiments, forming the front metallization layer 211A includes forming thermally-aware metal features (i.e., vias 227 and conductive lines 229), such that the structure of package 400 is similar to that of package 200G described above.

[0120] refer to Figure 12 The method 300 then forms a heat distribution layer 212 on the front side interconnect structure 208A (or the front side interconnect structure 207A or the front side interconnect structure 209A) in operation 306 .

[0121] In some embodiments, forming the heat distribution layer 212 includes first forming a dielectric layer 215 on the front metallization layer 210A. The dielectric layer 215 can include any suitable material, such as silicon oxide, a low-k dielectric material as described above, or the like. In some embodiments, the dielectric layer 215 is similar to the dielectric layer of the front metallization layer 210A. Subsequently, one or more thermally conductive materials as described above are formed on the dielectric layer 215 using a suitable process, such as the damascene process described above. The thermally conductive materials can be deposited using a suitable method, such as chemical vapor deposition (CVD), spin coating, atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating (e.g., electrodeposited or electroless plating), the like, or a combination thereof. A chemical mechanical planarization process can be performed to planarize the heat distribution layer 212.

[0122] refer to Figure 13 The method 300 then bonds the carrier substrate 220 to the front side 202A of the component substrate 202 in operation 308 .

[0123] In some embodiments, a first bonding layer (not separately depicted) is formed on the front surface 202A, such as on the heat distribution layer 212 and the dielectric layer 215, and a second bonding layer (not separately depicted) is formed on the surface of the carrier substrate 220. The first bonding layer and the second bonding layer can each comprise any suitable material (such as an oxide) and can be formed by any method (such as chemical vapor deposition, spin coating, thermal oxidation, chemical oxidation, the like, or a combination thereof). The first bonding layer and the second bonding layer are then bonded together by any suitable method (such as a pre-bonding process and an annealing process) to form a bonding layer 214, which couples the carrier substrate 220 to the device substrate 202.

[0124] refer to Figure 14 The method 300 forms a backside metallization layer 210B in operation 310 and completes the formation of the die 200 - 1 .

[0125] The structure of the back metallization layer 210B and its method of formation may be similar to that of the front metallization layer 210A, and therefore will not be repeated here for the sake of brevity. Although not depicted, forming the back metallization layer 210B may include first flipping the package 400 so that it can be supported by the carrier substrate 220. Subsequently, a dielectric layer is disposed on the back side 202B and the back inner connection structure 208B is formed in the dielectric layer by the damascene process as described above, resulting in a plurality of back metallization layers 210B. Thereafter, a bonding layer 222 is formed on the back metallization layer 210B in preparation for bonding to other features of the package 400. It is worth noting that in Figure 14The structure of the package 400 depicted in FIG is similar to the structure of the package 200A described above. Although not depicted, other features (such as a passivation layer and / or redistribution structures) may be subsequently formed on the backside metallization layer 210B.

[0126] Method 300 may then proceed in one of two alternative paths. Regarding the first path, operations 320, 322, and 324 may be performed to produce a structure of package 400 similar to any of packages 200B through 200D as described above. Alternatively, regarding the second path, operation 330 may be performed to produce a structure of package 400 similar to package 200E as described above.

[0127] Regarding the first path, please refer to Figure 15 、 Figure 16 and Figure 17 The method 300 then bonds the back substrate 230 to the device substrate 202 in operation 320 .

[0128] In some embodiments, reference Figure 15 Bonding the back substrate 230 includes first bonding the back substrate 230 to a carrier substrate 234 via a de-bonding layer 232 (or thermal release). The carrier substrate 234 can be similar to the carrier substrate 220 described above. The de-bonding layer 232 can include a light-to-heat-conversion (LTHC) release material based on an adhesive (e.g., epoxy resin) that is configured to lose its adhesive ability when heat is applied.

[0129] refer to Figure 16 , bonding the back substrate 230 continues to couple the back substrate 230 (which is supported by the carrier substrate 234) to the back side 202B of the element substrate 202. Before performing the coupling process, a first bonding layer (not separately depicted) is applied to the back side 202B (for example, on the back metallization layer 210B), and a second bonding layer (not separately depicted) is applied to the surface of the back substrate 230 opposite the carrier substrate 234. The first bonding layer and the second bonding layer are then combined together to form a bonding layer 222, thereby coupling the back substrate 230 to the back side 202B. The bonding layer 222 can be similar to the bonding layer 214 described above. Subsequently, with reference to Figure 17 The carrier substrate 234 is removed from the back substrate 230 by applying heat to the release layer 232. Thus, the back metallization layer 210B is interposed between the element substrate 202 and the back substrate 230.

[0130] refer to Figure 18 , the method 300 forms a via 240 through the back substrate 230 in operation 322. The via 240 is coupled to the back metallization layer 210B.

[0131] The vias 240 can be formed in the back substrate 230 by first patterning the back substrate 230 to form a plurality of openings (not depicted). Subsequently, a suitable electrically and thermally conductive material as described above is deposited in the openings. The material is then planarized by a chemical mechanical planarization process.

[0132] refer to Figure 19 The method 300 then forms the electrical connectors 250 in operation 324 , each electrical connector 250 being coupled to a corresponding via 240 .

[0133] The electrical connector 250 can be formed. It is formed by first forming a solder layer on the surface of the back substrate 230 opposite the back metallization layer 210B. The solder layer can be formed by evaporation, electroplating, printing, solder transfer, ball placement, or similar methods. Once the solder layer is formed on the structure, reflow can be performed to shape the solder into the desired bump shape. In some embodiments, the electrical connector 250 includes metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or similar methods. It is solder-free and has substantially vertical sidewalls. A metal cap layer can be formed above the metal pillars. Before forming the electrical connector 250, a structure (such as bump undermetallization) can be formed on the surface of the back substrate 230, which is electrically coupled to the back metallization layer 210B through the via 240. The final structure of the package 400 may be similar to the structure of any of the packages 200B to 200D described above.

[0134] Regarding the second approach, the method 300 bonds the die 200 - 2 (ie, the lower die 200 - 2 ) to the die 200 - 1 (ie, the upper die 200 - 1 ) via the bonding layer 222 in operation 330 to form an integrated chip, such as a system integration chip.

[0135] In some embodiments, the lower die 200-2 includes a device substrate 260 having device features 266 formed along a front surface 260A, and a front metallization layer 270 coupled to the device features 266. In this regard, the back surface 202B of the upper die 200-1 is coupled to the back surface 260B of the device substrate 260. The process of forming the components of the lower die 200-2 and subsequently bonding the lower die 200-2 to the upper die 200-1 can be similar to that described above with respect to operations 302 through 310 and 320, and therefore, will not be repeated for the sake of brevity. The final structure of the package 400 can be similar to the structure of the package 200E described above.

[0136] Although not depicted, method 300 may include other operations. For example, multiple packages 400 may be integrated (or stacked) together in any suitable configuration and still be within the scope of the present disclosure.

[0137] According to at least one embodiment of the present disclosure, a semiconductor structure includes: a first substrate having a front surface and a back surface opposite the front surface; a plurality of components on the front surface; a plurality of first interconnect structures on the front surface and coupled to the plurality of components; a heat distribution layer on the front surface and electrically insulated from the plurality of first interconnect structures, the heat distribution layer comprising a thermally conductive material; a second substrate on the front surface and coupled to the first substrate; and a plurality of second interconnect structures on the back surface and coupled to the plurality of components.

[0138] In some embodiments, the device further includes: a third substrate on the back surface of the first substrate; and a plurality of vias extending through the third substrate and coupled to the plurality of second internal connection structures.

[0139] In some embodiments, the method further includes a plurality of conductive connectors each coupled to a corresponding one of the plurality of vias.

[0140] In some embodiments, the heat distribution layer is a first heat distribution layer, and further includes a second heat distribution layer interposed between the plurality of second interconnect structures and the third substrate.

[0141] In some embodiments, the third substrate comprises at least one thermally conductive material selected from the group consisting of silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, gallium, and germanium.

[0142] In some embodiments, the second substrate directly contacts the heat distribution layer.

[0143] In some embodiments, the present invention further comprises: a third substrate, wherein the plurality of second internal connection structures are interposed between the first substrate and the third substrate; a plurality of second elements on a front surface of the third substrate; and a plurality of third internal connection structures coupled to the plurality of second elements.

[0144] In some embodiments, the thermally conductive material comprises at least one material selected from a group consisting of silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, aluminum, copper, gallium, germanium, gold, iron, magnesium, nickel, platinum, silver, titanium, tungsten, and zinc.

[0145] According to at least one embodiment of the present disclosure, a semiconductor structure includes: a first substrate having a front surface and a back surface opposite to the front surface; a plurality of components on the front surface; a plurality of first internal connection structures on the front surface and coupled to the plurality of components; a plurality of second internal connection structures on the back surface and coupled to the plurality of components; a second substrate coupled to the back surface so that the plurality of second internal connection structures are interposed between the first substrate and the second substrate; and a via extending through the second substrate and coupled to the plurality of second internal connection structures.

[0146] In some embodiments, the device further includes: a heat distribution layer located on the front surface above the plurality of first interconnect structures; and a third substrate located on the heat distribution layer and coupled to the front surface.

[0147] In some embodiments, the heat distribution layer and the second substrate each comprise at least one material selected from the group consisting of silicon, carbon nanotubes, carbon fiber, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, gallium, and germanium.

[0148] In some embodiments, a conductive connector coupled to the via is further included.

[0149] In some embodiments, a bonding layer is further included between the plurality of second interconnect structures and the second substrate.

[0150] In some embodiments, the plurality of first interconnect structures include a plurality of conductive lines and a plurality of vias, and a density of the plurality of vias is about 1% to about 5%.

[0151] According to at least one embodiment of the present disclosure, a method includes: forming a plurality of components on a front surface of a first substrate; forming a plurality of first interconnect structures coupled to the plurality of components on the front surface of the first substrate; bonding a second substrate to the front surface of the first substrate so that the plurality of first interconnect structures are interposed between the first substrate and the second substrate; forming a plurality of second interconnect structures on a back surface of the first substrate opposite to the front surface to produce a semiconductor die; bonding a third substrate to the back surface of the first substrate; and forming a plurality of vias coupled to the plurality of second interconnect structures and extending through the third substrate.

[0152] In some embodiments, the method further includes forming a heat distribution layer between the plurality of first interconnect structures and the second substrate, wherein the heat distribution layer includes a thermally conductive material.

[0153] In some embodiments, the thermally conductive material comprises at least one material selected from a group consisting of silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, aluminum, copper, gallium, germanium, gold, iron, magnesium, nickel, platinum, silver, titanium, tungsten, and zinc.

[0154] In some embodiments, the third substrate comprises at least one thermally conductive material selected from the group consisting of silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, gallium, and germanium.

[0155] In some embodiments, bonding the third substrate includes: providing the third substrate to be bonded to a fourth substrate via a peeling layer; bonding the third substrate to the back surface of the first substrate; and releasing the peeling layer to remove the fourth substrate from the third substrate.

[0156] In some embodiments, the method further includes forming a plurality of conductive connectors respectively coupled to a corresponding one of the plurality of vias.

[0157] According to at least one embodiment of the present disclosure, a semiconductor structure includes a first substrate having a front surface and a back surface opposite the front surface; a plurality of components on the front surface; a plurality of first interconnect structures on the front surface and coupled to the plurality of components; a heat distribution layer on the front surface and electrically insulated from the plurality of first interconnect structures; a second substrate on the front surface and coupled to the first substrate, wherein the second substrate directly contacts the heat distribution layer; and a plurality of second interconnect structures on the back surface and coupled to the plurality of components.

[0158] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processing procedures and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that Include: a first substrate having a front surface and a back surface opposite to the front surface; a plurality of components on the front surface; a plurality of first inner connection structures on the front surface and coupled to the plurality of elements; a heat distribution layer overlying the front surface and electrically insulated from the plurality of first interconnect structures; a second substrate on the front surface and coupled to the first substrate; as well as A plurality of second inner connection structures are on the back surface and coupled to the plurality of components.

2. The semiconductor structure according to claim 1, wherein Also includes: a third substrate on the back surface of the first substrate; and A plurality of vias extend through the third substrate and are coupled to the plurality of second internal connection structures.

3. The semiconductor structure according to claim 2, wherein: The invention also includes a plurality of conductive connectors respectively coupled to a corresponding one of the plurality of conducting holes.

4. The semiconductor structure according to claim 2, wherein: The heat distribution layer is a first heat distribution layer and further includes a second heat distribution layer between the plurality of second interconnection structures and the third substrate.

5. The semiconductor structure according to claim 1, wherein The second substrate directly contacts the heat distribution layer.

6. The semiconductor structure according to claim 1, wherein Also includes: a third substrate, wherein the plurality of second interconnecting structures are interposed between the first substrate and the third substrate; A plurality of second components are disposed on a front surface of the third substrate; as well as A plurality of third internal connection structures are coupled to the plurality of second elements.

7. A semiconductor structure, characterized in that Include: a first substrate having a front surface and a back surface opposite to the front surface; a plurality of components on the front surface; a plurality of first internal connection structures on the front surface and coupled to the plurality of elements; a plurality of second internal connection structures on the back surface and coupled to the plurality of elements; a second substrate coupled to the back surface so that the plurality of second interconnect structures are interposed between the first substrate and the second substrate; as well as A via extends through the second substrate and is coupled to the plurality of second internal connection structures.

8. The semiconductor structure according to claim 7, wherein: Also includes: a heat distribution layer located on the front surface over the plurality of first interconnect structures; and A third substrate is on the heat distribution layer and coupled to the front surface.

9. The semiconductor structure according to claim 7, wherein: The invention also includes a bonding layer between the plurality of second inner connection structures and the second substrate.

10. A semiconductor structure, characterized in that Include: a first substrate having a front surface and a back surface opposite to the front surface; a plurality of components on the front surface; a plurality of first inner connection structures on the front surface and coupled to the plurality of elements; a heat distribution layer overlying the front surface and electrically insulated from the plurality of first interconnect structures; a second substrate on the front surface and coupled to the first substrate, wherein the second substrate directly contacts the heat distribution layer; as well as A plurality of second inner connection structures are on the back surface and coupled to the plurality of components.

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