Power supply voltage detection circuit

Abstract

The utility model discloses a power supply voltage detection circuit which comprises a power supply input circuit used for being connected with an external power supply. The power supply circuit is connected with the power supply input circuit and is used for converting an accessed power supply voltage into a voltage required by system work; the AI circuit is connected with the power supply input circuit and is used for detecting the accessed power supply voltage in real time; the level conversion circuit is connected with the AI circuit and is used for carrying out level conversion on a detection signal of the AI circuit, the CPU system is connected with the level conversion circuit and is used for carrying out data storage on the received signal according to setting, and the power supply circuit is respectively connected with the AI circuit, the level conversion circuit and the CPU system. And the power supply circuit is also connected with the AI circuit through a voltage stabilizing source for providing a stable voltage source for the AI circuit. According to the utility model, the detection stability can be improved, and data loss is avoided.

Description

Technical Field

[0001] The utility model belongs to the field of power supply detection circuits, and in particular relates to a power supply voltage detection circuit. Background Art

[0002] In control system circuits, a stable power supply is essential for stable and normal system operation. If the power supply is insufficient, the system may shut down due to undervoltage, resulting in data loss. To prevent data loss, real-time monitoring of the system's power supply voltage allows the system to prepare for power outages in advance and allows remote units to promptly obtain information about power anomalies in local devices so they can take appropriate measures. Existing systems often include power outage detection circuits, such as the DRAM data power-off protection circuit, electronic device, and method disclosed in patent CN109782888A on May 21, 2019. This circuit includes a system power module, a power-off detection module, a backup power module, and a DRAM. The power-off detection module is connected to the system power module and is used to obtain the actual voltage of the system power module. When the power-off detection module detects that the actual voltage is less than or equal to a preset voltage threshold, it sends an interrupt signal to the processor. However, these commercially available detection modules have poor real-time detection stability and cannot effectively ensure timely data processing in the system. Therefore, a power supply voltage detection circuit is needed to meet these requirements. Utility Model Content

[0003] The purpose of the utility model is to provide a power supply voltage detection circuit, which can improve the stability of detection and avoid data loss.

[0004] To achieve this objective, the present invention provides a power supply voltage detection circuit, comprising a power supply input circuit for accessing an external power supply, a power supply circuit connected to the power supply input circuit for converting the access power supply voltage into the voltage required for system operation, an AI circuit connected to the power supply input circuit for real-time detection of the access power supply voltage, a level conversion circuit connected to the AI circuit for level conversion of the detection signal of the AI circuit, and a CPU system connected to the level conversion circuit for storing data of the received signal according to a setting, wherein the power supply circuit is connected to the AI circuit, the level conversion circuit, and the CPU system, respectively, and the power supply circuit is also connected to the AI circuit via a voltage regulator for providing a stable voltage source for the AI circuit.

[0005] Preferably, the power supply circuit is provided with a DC-DC buck chip for stepping down the voltage of an external power supply connected thereto and an LDO voltage stabilizing chip for stabilizing the voltage of the power provided by the DC-DC buck chip.

[0006] Preferably, the DC-DC step-down chip outputs a DC 3.8V voltage, and the LDO voltage regulator chip outputs a DC 3.3V voltage.

[0007] Preferably, the AI circuit is provided with an operational amplifier chip and an ADC analog-to-digital conversion chip, the non-inverting input terminal of the operational amplifier chip is connected to the power input circuit through a sixty-hundred and fifty-first resistor, the non-inverting input terminal of the operational amplifier chip is also connected to the ground line through a sixty-fifth resistor and a seventy-fifth capacitor, the inverting input terminal of the operational amplifier chip is connected to the output terminal of the operational amplifier chip, the output terminal of the operational amplifier chip is connected to the Ain port of the ADC analog-to-digital conversion chip through a sixty-fifth resistor, the output terminal of the operational amplifier chip is also connected to the ground line through a sixty-fifth resistor and a sixty-eighth capacitor in sequence, the VDD port of the ADC analog-to-digital conversion chip is connected to the voltage regulator source, the VSS port of the ADC analog-to-digital conversion chip is connected to the VDD port of the ADC analog-to-digital conversion chip through a sixty-eighth capacitor and is also connected to the ground line, the SCL port of the ADC analog-to-digital conversion chip is connected to the level conversion circuit through a sixty-fifth resistor, and the SDA port of the ADC analog-to-digital conversion chip is connected to the level conversion circuit through a sixty-fifth resistor.

[0008] Preferably, the voltage stabilizing source is provided with a voltage stabilizing source chip, the positive terminal of the voltage stabilizing source chip is connected to the ground wire, the negative terminal of the voltage stabilizing source chip is connected to the AI circuit, the reference terminal of the voltage stabilizing source chip is connected to the ground wire through the six hundred and sixty resistor and is also connected to the negative terminal of the voltage stabilizing source chip through the six hundred and fifty-ninth resistor, the negative terminal of the voltage stabilizing source chip is connected to the power supply circuit through the six hundred and fifty-seventh resistor, and the connection end of the six hundred and fifty-seventh resistor and the power supply circuit is connected to the ground wire through the seven hundred and forty-sixth capacitor.

[0009] Preferably, the level conversion circuit is provided with a level conversion chip.

[0010] Preferably, the power input circuit is provided with a power access interface for connecting to an external power source, and a TVS diode is connected in parallel between the positive terminal of the power access interface and the negative terminal of the power access interface.

[0011] Compared with the prior art, the present invention has the following beneficial effects:

[0012] In the present invention, by providing an AI circuit to perform real-time detection of the connected power supply voltage and providing a stable voltage to the AI circuit via a voltage regulator, the stability of the detection can be effectively improved, providing the CPU system with an accurate real-time supply voltage change signal, thus preventing data loss. Furthermore, the CPU system can promptly report alarm information, allowing all levels of the system to prepare for power outages in advance. Furthermore, remote related units can promptly obtain information about local device power anomalies so that they can take appropriate measures. In the present invention, the non-inverting input terminal of the operational amplifier chip of the AI circuit is connected to the ground wire via the 654th resistor and the 751st capacitor, respectively, which can effectively eliminate false triggering and ensure the reliability of the collected data. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a circuit structure diagram of the utility model;

[0014] Figure 2 This is a schematic diagram of the circuit structure of the CPU system in the present utility model;

[0015] Figure 3 This is a schematic diagram of the circuit structure of the power input circuit in the utility model;

[0016] Figure 4 This is a schematic diagram of the circuit structure of the power supply circuit in the utility model;

[0017] Figure 5 Schematic diagram of the circuit structure of the AI circuit in this utility model;

[0018] Figure 6 This is a schematic diagram of the circuit structure of the voltage stabilizing source in the utility model;

[0019] Figure 7 This is a schematic diagram of the circuit structure of the level conversion circuit in the utility model. DETAILED DESCRIPTION

[0020] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0021] like Figure 1-7As shown, the present invention provides a power supply voltage detection circuit, comprising a power input circuit 2 for connecting to an external power source, a power supply circuit 3 connected to the power input circuit 2 for converting the incoming power voltage into the voltage required for system operation, an AI circuit 5 connected to the power input circuit 2 for real-time detection of the incoming power voltage, a level conversion circuit 6 connected to the AI circuit 5 for level conversion of the detection signal from the AI circuit 5, and a CPU system 1 connected to the level conversion circuit 6 for storing the received signal according to a preset data. The power supply circuit 3 is connected to the AI circuit 5, the level conversion circuit 6, and the CPU system 1, respectively. The power supply circuit 3 is further connected to the AI circuit 5 via a voltage regulator 4 for providing a stable voltage source to the AI circuit 5. The level conversion circuit 6 is provided with a level conversion chip U32. The power input circuit 2 is provided with a power supply connection interface J1 for connecting to an external power source. A TVS diode D1 is connected in parallel between the positive terminal and the negative terminal of the power supply connection interface J1.

[0022] The power supply circuit 3 is equipped with a DC-DC buck chip U1 for stepping down the voltage of an external power supply, and an LDO voltage regulator chip U2 for stabilizing the voltage of the power provided by the DC-DC buck chip U1. The DC-DC buck chip U1 outputs a DC 3.8V voltage, and the LDO voltage regulator chip U2 outputs a DC 3.3V voltage. In this embodiment, the power supply interface J1 is connected to an external DC 9V-36V power supply. The connection between the power supply circuit 3 and the positive terminal of the power supply interface J1 is sequentially provided with a ninth diode D9, a second inductor L2, and a first surface mount ferrite bead B1, which can effectively filter the incoming power supply.

[0023] The voltage regulator 4 includes a voltage regulator chip D12. The positive terminal of the voltage regulator chip D12 is connected to the ground line, the negative terminal of the voltage regulator chip D12 is connected to the AI circuit 5, the reference terminal of the voltage regulator chip D12 is connected to the ground line via the six-hundred-and-sixty-sixth resistor R660, and is also connected to the negative terminal of the voltage regulator chip D12 via the six-hundred-and-fifty-ninth resistor R659. The negative terminal of the voltage regulator chip D12 is connected to the power supply circuit 3 via the six-hundred-and-fifty-seventh resistor R657. The connection between the six-hundred-and-fifty-seventh resistor R657 and the power supply circuit 3 is connected to the ground line via the seven-hundred-and-forty-sixth capacitor C746. In this embodiment, the voltage regulator chip D12 generates a stable regulated output power supply VCC_ADC = 2.5*(R659+R660) / R660 = 2.98354V, thereby providing a stable voltage for the operational amplifier chip U14 and the ADC analog-to-digital conversion chip U15.

[0024] The AI circuit 5 is provided with an operational amplifier chip U14 and an ADC analog-to-digital conversion chip U15. The non-inverting input terminal of the operational amplifier chip U14 is connected to the power input circuit 2 through the six hundred and fifty-first resistor R651. The non-inverting input terminal of the operational amplifier chip U14 is also connected to the ground line through the six hundred and fifty-fourth resistor R654 and the seven hundred and fifty-first capacitor C751 respectively. The inverting input terminal of the operational amplifier chip U14 is connected to the output terminal of the operational amplifier chip U14. The output terminal of the operational amplifier chip U14 is connected to the Ain port of the ADC analog-to-digital conversion chip U15 through the six hundred and fifty-first resistor R650. The output terminal of the operational amplifier chip U14 is also connected to the Ain port of the ADC analog-to-digital conversion chip U15 in sequence. The VDD port of the ADC analog-to-digital conversion chip U15 is connected to the voltage regulator 4 via the six-hundred-and-fifty-second resistor R652 and the six-hundred-and-eighty-second capacitor C686. The VSS port of the ADC analog-to-digital conversion chip U15 is connected to the VDD port of the ADC analog-to-digital conversion chip U15 and to the ground via the six-hundred-and-eighty-fifth capacitor C685. The SCL port of the ADC analog-to-digital conversion chip U15 is connected to the level conversion circuit 6 via the six-hundred-and-fifty-third resistor R653. The SDA port of the ADC analog-to-digital conversion chip U15 is connected to the level conversion circuit 6 via the six-hundred-and-fifty-sixth resistor R656. In this embodiment, the operational amplifier chip U14 is a TP5531, and the ADC analog-to-digital conversion chip U15 is an MCP3221A5T. The seven-hundred-and-fifty-first capacitor C751 connected in parallel across the six-hundred-and-fifth resistor R654 can effectively eliminate false triggering and ensure the reliability of the collected data.

[0025] In this embodiment, during operation, the external DC power supply connected to the power supply interface J1 is divided by the six hundred and fifty-first resistor R651 and the six hundred and fifty-fourth resistor R654. The divided voltage is then input to the operational amplifier chip U14 for calculation. The output signal of the operational amplifier chip U14 is input to the Ain port of the ADC analog-to-digital converter chip U15. The ADC analog-to-digital converter chip U15 collects the input power supply value Vain. The voltage value of the external DC power supply is VIN. Therefore, Vain = VIN / (R651+R654)*R654, which is calculated as VIN / 19. The ADC analog-to-digital converter chip U15 has a resolution of 12 bits, and its least significant bit (LSB) = VCC_ADC / (2^12), which is calculated as 0.000728403. The analog power supply is converted into a digital power supply value Din = Vain / LSB. This Din is input to the level conversion circuit 6 via the IIC bus, converted to a low-level signal VDD by the level conversion chip U32, and transmitted to the CPU system 1 for processing. The low battery alarm voltage can be set in the CPU system 1 according to demand. When the low battery alarm voltage is set to 9V, then Din is calculated to be 650.305134. When the value obtained by the IIC interface of the CPU system 1 is lower than 650.305134, an alarm will be triggered. In this process, in order to ensure the effectiveness of the alarm information, ten samples are taken, the highest and lowest values are removed, and the remaining values are processed by taking the average value to avoid false alarms. The CPU system 1 saves the corresponding important communication data in advance according to the alarm information, thereby avoiding data loss. In addition, the CPU system 1 can also expand its functions, reminding the subsystem of low battery through downlink communication, or reporting abnormal information to the remote platform through wireless uplink communication. The utility model can improve the stability of detection and avoid data loss.

[0026] The above are merely preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. Rather, the present invention can be used in various other combinations, modifications, and environments and can be modified within the scope of the present invention through the above teachings or techniques or knowledge in related fields. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be protected by the claims appended hereto.

Claims

1. A power supply voltage detection circuit, comprising a power supply input circuit (2) for accessing an external power supply, characterized in that: The system further comprises a power supply circuit (3) connected to the power supply input circuit (2) for converting the input power supply voltage into a voltage required for system operation, an AI circuit (5) connected to the power supply input circuit (2) for real-time detection of the input power supply voltage, a level conversion circuit (6) connected to the AI circuit (5) for level conversion of the detection signal of the AI circuit (5), and a CPU system (1) connected to the level conversion circuit (6) for storing data of the received signal according to settings. The power supply circuit (3) is respectively connected to the AI circuit (5), the level conversion circuit (6), and the CPU system (1). The power supply circuit (3) is also connected to the AI circuit (5) via a voltage stabilizing source (4) for providing a stable voltage source for the AI circuit (5).

2. A power supply voltage detection circuit according to claim 1, characterized in that: The power supply circuit (3) is provided with a DC-DC step-down chip (U1) for reducing the voltage of an external power supply connected thereto and an LDO voltage stabilizing chip (U2) for stabilizing the voltage of the power provided by the DC-DC step-down chip (U1).

3. A power supply voltage detection circuit according to claim 2, characterized in that: The DC-DC step-down chip (U1) outputs a DC 3.8V voltage, and the LDO voltage stabilization chip (U2) outputs a DC 3.3V voltage.

4. The power supply voltage detection circuit according to claim 1, wherein: The AI circuit (5) is provided with an operational amplifier chip (U14) and an ADC analog-to-digital conversion chip (U15); the in-phase input terminal of the operational amplifier chip (U14) is connected to the power input circuit (2) via a six-hundred-and-fifty-first resistor (R651); the in-phase input terminal of the operational amplifier chip (U14) is also connected to the ground wire via a six-hundred-and-fifty-fourth resistor (R654) and a seven-hundred-and-fifty-first capacitor (C751); the inverting input terminal of the operational amplifier chip (U14) is connected to the output terminal of the operational amplifier chip (U14); the output terminal of the operational amplifier chip (U14) is connected to the Ain port of the ADC analog-to-digital conversion chip (U15) via a six-hundred-and-fifty resistor (R650); the output terminal of the operational amplifier chip (U14) is connected to the Ain port of the ADC analog-to-digital conversion chip (U15); The ADC analog-to-digital conversion chip (U15) is connected to the ground line through the six hundred and fifty-second resistor (R652) and the six hundred and eighty-sixth capacitor (C686) in sequence. The VDD port of the ADC analog-to-digital conversion chip (U15) is connected to the voltage regulator (4). The VSS port of the ADC analog-to-digital conversion chip (U15) is connected to the VDD port of the ADC analog-to-digital conversion chip (U15) through the six hundred and eighty-fifth capacitor (C685) and is also connected to the ground line. The SCL port of the ADC analog-to-digital conversion chip (U15) is connected to the level conversion circuit (6) through the six hundred and fifty-third resistor (R653). The SDA port of the ADC analog-to-digital conversion chip (U15) is connected to the level conversion circuit (6) through the six hundred and fifty-sixth resistor (R656).

5. A power supply voltage detection circuit according to claim 1 or 4, characterized in that: The voltage stabilizing source (4) is provided with a voltage stabilizing source chip (D12), the positive terminal of the voltage stabilizing source chip (D12) is connected to the ground line, the negative terminal of the voltage stabilizing source chip (D12) is connected to the AI circuit (5), the reference terminal of the voltage stabilizing source chip (D12) is connected to the ground line through the six hundred and sixty resistor (R660) and is also connected to the negative terminal of the voltage stabilizing source chip (D12) through the six hundred and fifty-ninth resistor (R659), the negative terminal of the voltage stabilizing source chip (D12) is connected to the power supply circuit (3) through the six hundred and fifty-seventh resistor (R657), and the connection terminal of the six hundred and fifty-seventh resistor (R657) and the power supply circuit (3) is connected to the ground line through the seven hundred and forty-sixth capacitor (C746).

6. The power supply voltage detection circuit according to claim 1, characterized in that: The level conversion circuit (6) is provided with a level conversion chip (U32).

7. The power supply voltage detection circuit according to claim 1, characterized in that: The power input circuit (2) is provided with a power access interface (J1) for connecting to an external power source, and a TVS diode (D1) is connected in parallel between the positive terminal of the power access interface (J1) and the negative terminal of the power access interface (J1).

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