High-integration multi-channel arbitrary waveform generation system for quantum computing

Abstract

The utility model provides an arbitrary waveform generating system which is high in integration level, multi-channel and low in noise, and is particularly suitable for superconducting quantum computing application. According to the utility model, a hardware architecture in which the base plate integrated with the medium-speed waveform generation circuit is combined with the high-speed daughter card is adopted, so that the system integration level, the multi-channel expansibility and the application range are improved. By applying radio frequency direct acquisition circuit design in the high-speed daughter card and introducing a unique power management module and innovative noise suppression technologies such as a system overall ground plane configuration scheme and the like into a bottom plate, system noise is remarkably reduced, and the signal-to-noise ratio and measurement precision of signals are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of signal generation, in particular to a highly integrated multi-channel arbitrary waveform generation system for quantum computing. Background Art

[0002] In fields such as electronic testing, communications, and scientific research, especially quantum computing, waveform generators are needed to accurately create various quantum states. Therefore, arbitrary waveform generation systems are one of the key devices in quantum computing.

[0003] Traditional quantum computing uses IQ mixing technology to generate the required waveforms. This technology splits the input signal into orthogonal I (in-phase) and Q (quadrature) signals for processing, enabling precise control of the signal's phase and amplitude. Adjusting the phase difference between the I and Q signals facilitates signal rotation, translation, and frequency conversion, providing a flexible approach to complex signal processing in quantum computing.

[0004] However, IQ mixing technology also has some defects, mainly as follows:

[0005] (1) The circuit structure is complex. In the implementation circuit based on IQ mixing technology, additional hardware devices such as mixers and local oscillators are required, which increases the complexity of the quantum computing system and makes it difficult to achieve high integration and multi-channel waveform output.

[0006] (2) Sideband leakage. Sideband leakage may occur during the IQ mixing process, that is, the unwanted sideband signal (upper sideband or lower sideband) is not fully suppressed and leaks into the output signal. Sideband leakage may lead to inaccurate manipulation of quantum bits and affect the results of quantum computing. For example, in the radio frequency manipulation of quantum bits, if there is sideband leakage, it may introduce additional noise or interfere with the state of the quantum bit.

[0007] (3) Local oscillator leakage. In an IQ mixer, the local oscillator signal will unexpectedly appear at the mixer's output. This output signal contains a strong local oscillator frequency component. In a quantum computing system, this local oscillator leakage may cause inaccurate manipulation of quantum bits, affecting the results of quantum computing. For example, in the radio frequency manipulation of quantum bits, if local oscillator leakage exists, it may introduce additional noise or interfere with the state of the quantum bit, causing signal distortion and misjudgment, affecting the results of quantum computing.

[0008] In recent years, quantum computing systems have rapidly developed, heading towards kilobit scale. This places higher demands on the integration and low noise of arbitrary waveform generation systems. Traditional IQ mixing technology, due to its complex circuit structure, low signal-to-noise ratio caused by sideband leakage and local oscillator leakage, is clearly unable to meet current requirements. Therefore, the development of arbitrary waveform generation systems with high integration, multi-channel output, ultra-low noise, and high-speed arbitrary waveform generation has become a critical task of great importance and practical value. Utility Model Content

[0009] To address the aforementioned issues in the existing technology, the present invention proposes a highly integrated, multi-channel, low-noise arbitrary waveform generation system, particularly suitable for superconducting quantum computing applications. This system utilizes a hardware architecture combining a baseboard with integrated medium-speed waveform generation circuits and a high-speed daughter card, improving system integration, multi-channel scalability, and application scope. Innovative noise suppression technologies, such as the application of RF direct sampling circuit design in the high-speed daughter card, a unique power management module in the baseboard, and an overall system ground plane configuration, significantly reduce system noise, improving the signal-to-noise ratio and measurement accuracy.

[0010] Specifically, the utility model discloses a highly integrated multi-channel arbitrary waveform generation system for quantum computing, which includes a baseboard on which a control module and a medium-speed arbitrary waveform generation circuit are integrated;

[0011] The system also includes a daughter card, and the baseboard is also integrated with a power filter circuit and a power management module;

[0012] The daughter card is integrated with a high-speed arbitrary waveform generating circuit;

[0013] The power supply filter circuit is configured to filter the external power supply signal before the external power supply signal enters the power supply management module;

[0014] The power management module is configured to generate an internal power signal based on the external power signal;

[0015] The control module is configured to control the medium-speed arbitrary waveform generating circuit and / or the high-speed arbitrary waveform generating circuit to generate waveform signals.

[0016] Furthermore, the control module includes a communication interface and an FPGA unit integrated on the baseboard, wherein the communication interface is configured to allow data communication between the outside and the FPGA unit, and the FPGA unit is configured to control the medium-speed arbitrary waveform generation circuit and / or the high-speed arbitrary waveform generation circuit to generate waveform signals according to control data;

[0017] And / or, the operating frequency of the medium-speed arbitrary waveform generating circuit is DC-700 MHz, and the operating frequency of the high-speed arbitrary waveform generating circuit is 4 GHz-8 GHz.

[0018] Furthermore, the high-speed arbitrary waveform generating circuit includes a high-speed digital-to-analog converter and a filtering and shaping circuit.

[0019] Furthermore, the power supply filter circuit is arranged at the power supply inlet of the base plate.

[0020] Furthermore, the power management module includes a DCDC switching power supply and a common mode filter;

[0021] The DCDC switching power supply is configured to generate an internal power signal based on the external power signal;

[0022] The common mode filter is configured to filter the internal power supply signal.

[0023] Furthermore, the daughter card is integrated with a low-voltage difference linear regulator, which is configured to provide an operating voltage for the high-speed arbitrary waveform generating circuit based on the internal power supply signal; and / or, the base plate is integrated with a low-voltage difference linear regulator, which is configured to provide an operating voltage for the medium-speed arbitrary waveform generating circuit based on the internal power supply signal.

[0024] Furthermore, the bottom plate is provided with a first ground plane for the DCDC switching power supply, a second ground plane for the common mode filter, and a third ground plane for the medium-speed arbitrary waveform generating circuit;

[0025] The daughter card is provided with a fourth ground plane for the high-speed arbitrary waveform generating circuit;

[0026] The first ground plane, the second ground plane, the third ground plane and the fourth ground plane are isolated from each other.

[0027] Preferably, the first ground plane is a PGND plane; the second ground plane is a PGND plane or a GND plane; and the third ground plane and the fourth ground plane are AGND planes.

[0028] Furthermore, the data frame for control data includes a frame header, a command portion, a waveform data portion, a check code and a frame trailer;

[0029] The frame header is used to identify the beginning of the data frame;

[0030] The instruction part includes control instructions for instructing the operation of the arbitrary waveform generating circuit and parameter settings for instructing waveform parameters;

[0031] The waveform data portion includes the waveform data itself;

[0032] The check code is used to check the integrity and / or accuracy of the data frame;

[0033] The frame tail is used to mark the end of the data frame.

[0034] Furthermore, the filtering and shaping circuit includes a high roll-off low-pass filtering circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The specific implementation of the present invention will be further described in detail below with reference to the accompanying drawings.

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 Schematically shows a preferred example of the arbitrary waveform generating system of the present invention;

[0038] Figure 2 The figure schematically shows a preferred example of the configuration of the power management module and the ground plane in the arbitrary waveform generation system of the present invention. DETAILED DESCRIPTION

[0039] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example to fully convey the spirit of the present invention to those skilled in the art to which the present invention belongs. Therefore, the present invention is not limited to the embodiments disclosed herein.

[0040] Figure 1 A preferred example of the arbitrary waveform generating system of the present invention is schematically shown.

[0041] like Figure 1 As shown, the arbitrary waveform generation system of the present invention may include a baseboard 11 and multiple daughter cards, such as a high-speed daughter card 1 and a high-speed daughter card 2. Those skilled in the art will appreciate that the high-speed daughter cards herein can be adapted for use with the baseboard 11.

[0042] A plurality of medium-speed arbitrary waveform generating circuits may be integrated on the base plate 11 , such as the arbitrary waveform generating circuit 16 and the arbitrary waveform generating circuit 17 .

[0043] A plurality of high-speed arbitrary waveform generating circuits may be integrated on the daughter card. For example, the high-speed daughter card 1 is integrated with high-speed arbitrary waveform generating circuits 12 and 13 , and the high-speed daughter card 2 is integrated with high-speed arbitrary waveform generating circuits 14 and 15 .

[0044] In the present invention, the high-speed arbitrary waveform generating circuit may have an operating frequency of 4 GHz to 8 GHz, and the medium-speed arbitrary waveform generating circuit may have an operating frequency of DC to 700 MHz.

[0045] In this utility model, the high-speed arbitrary waveform generation circuit adopts a radio frequency direct sampling circuit design, which includes a high-sampling rate digital-to-analog converter (DAC) and a low-insertion-loss, high-roll-off, low-pass filter circuit. Therefore, compared with traditional IQ mixing designs, the high-speed arbitrary waveform generation circuit of this utility model has the ability to directly filter out higher-order harmonics, capable of generating the high signal-to-noise ratio signals required for quantum bit control. It also has a simpler circuit structure and can solve the problems of local oscillator leakage and sideband leakage caused by IQ mixing signals.

[0046] In a preferred example of the present invention, only one high-speed output channel is provided for each high-speed arbitrary waveform generating circuit.

[0047] The medium-speed arbitrary waveform generation circuit is also realized with the help of DAC chip and necessary filtering and shaping circuit.

[0048] In a preferred example of the present invention, for a medium-speed arbitrary waveform generating circuit, multiple (for example, four) medium-speed output channels can be configured based on a single DAC chip, thereby improving resource utilization and reducing costs, and providing abundant output channels with less hardware configuration.

[0049] Continue to see Figure 1 A control module may also be integrated on the baseboard 11, which may control the medium-speed arbitrary waveform generating circuit and the high-speed arbitrary waveform generating circuit on the high-speed daughter card to generate and output the required waveform signal according to control data provided by the host computer, for example.

[0050] exist Figure 1 In an example, the control module may include a (eg, high-speed) communication interface and a field programmable gate array (FPGA) unit.

[0051] The (high-speed) communication interface can be used to implement data communication between the external device (e.g., a host computer) and the FPGA unit. For example, it can receive control data sent by the host computer and transmit it to the FPGA unit.

[0052] The FPGA unit can control the medium-speed and / or high-speed arbitrary waveform generation circuit to generate corresponding waveform signals according to the received control data.

[0053] In the present invention, the host computer can realize data communication between the arbitrary waveform generation system and the host computer by sending data frames of a specific format to the arbitrary waveform generation system.

[0054] In a preferred example, the data frame may include a frame header, an instruction portion, a waveform data portion, a check code, and a frame trailer.

[0055] The frame header may include information such as the start identifier of the data frame, frame length, and frame type, and is used to identify the start and type of the data frame.

[0056] The instruction part can contain control instructions and parameter settings.

[0057] Control instructions can be used to instruct the arbitrary waveform generation circuit to perform specific operations, such as waveform selection, frequency setting, amplitude adjustment, etc. As an example, the FPGA unit can determine whether to send waveform data to the high-speed output channel or the medium-speed output channel based on the channel address in the control instruction.

[0058] Parameter settings can be used to specify specific parameters of the waveform, such as frequency, amplitude, phase, etc.

[0059] The waveform data portion may include the waveform data itself. In the present invention, the waveform data may be pre-stored waveform samples or real-time generated waveform data. Depending on the complexity and accuracy requirements of the waveform, the waveform data portion may occupy most of the space in the data frame.

[0060] The checksum can be used to verify the integrity and accuracy of the data frame. During the data frame transmission process, data loss or errors may occur. The checksum can be used to detect and handle these problems in a timely manner.

[0061] The frame tail may include an end identifier of the data frame, which is used to identify the end of the data frame.

[0062] Therefore, when the FPGA unit receives the control data, it can parse and process the control data, generate corresponding waveform data according to the control instruction requirements, and distribute it to the corresponding high-speed or medium-speed output channel.

[0063] In the high-speed / medium-speed arbitrary waveform generation circuit, the DAC chip corresponding to the selected output channel converts the digital signal into an analog signal and performs signal conditioning through a filtering and shaping circuit.

[0064] In order to reduce the noise of the high-speed arbitrary waveform generation circuit and the medium-speed arbitrary waveform generation circuit, in addition to adopting the radio frequency direct sampling circuit design in the high-speed arbitrary waveform generation circuit, the utility model also adaptively introduces other noise suppression schemes into the arbitrary waveform generation system.

[0065] Figure 2The preferred example of the power management module and ground plane configuration in the arbitrary waveform generation system of the present invention is schematically shown, thereby allowing the occurrence of system noise to be further suppressed by means of a unique power management module and ground plane configuration solution.

[0066] The power management module can be integrated on the baseboard 11 to generate an internal power signal based on an external power signal (for example, a 12V power supply signal) to drive various chips / circuits in the arbitrary waveform generation system, such as the control module, high-speed daughter card and medium-speed arbitrary waveform generation circuit.

[0067] exist Figure 2 In the preferred example shown, a power filter circuit can also be set at the power inlet of the base plate 11 (which is used to receive an external power signal such as 12V) to filter the external power signal before it enters the power management module, thereby reducing noise from the source.

[0068] Continue to see Figure 2 The power management module of the present invention may include multiple DCDC switching power supplies and multiple common-mode filters.

[0069] Since the arbitrary waveform generation system of the present invention includes a variety of different chips, such as FPGA chips and DAC chips in high-speed / medium-speed arbitrary waveform generation circuits, different chips require different operating voltages, and the same chip may also require multiple voltages. Therefore, a DCDC switching power supply can be used to generate various internal power signals using external power signals, thereby providing the required operating voltages for the corresponding circuits / chips.

[0070] Considering the noise sensitivity of analog devices such as DAC chips and filter-shaping circuits, the internal power supply signals directly output by the DCDC switching power supply have large ripple and switching noise. Therefore, a common-mode filter can be placed after the DCDC switching power supply to filter the internal power supply signal before it is provided to these analog devices, thereby reducing the DCDC switching power supply's impact on, for example, medium-speed / high-speed arbitrary waveform generation circuits. Furthermore, when using the DCDC switching power supply to provide the internal power supply signal to the medium-speed / high-speed arbitrary waveform generation circuit, the DCDC switching power supply can be configured to reduce the voltage of the internal power supply signal to a voltage slightly higher than the target voltage.

[0071] For digital circuits that are not sensitive to noise, such as FPGA chips, they can be powered directly by a DCDC switching power supply.

[0072] Continue to see Figure 2To achieve noise suppression, a low-dropout linear regulator (LDO) can be integrated on the baseboard 11 to adjust the voltage of the internal power signal to the voltage required by each chip / circuit in the medium-speed arbitrary waveform generation circuit, generating the corresponding operating voltage. At the same time, a low-dropout linear regulator (LDO) can also be integrated on the high-speed daughter card to adjust the voltage of the internal power signal to the voltage required by each chip / circuit in the high-speed arbitrary waveform generation circuit, generating the corresponding operating voltage.

[0073] In addition to the power supply, the ground plane also constitutes a noise conduction path. To reduce the impact of noise on the arbitrary waveform generation circuit through the ground plane, the present invention also implements a noise suppression design in the ground plane configuration of the arbitrary waveform generation system. Specifically, a unique segmented and isolated design is implemented for the ground planes of the baseboard and the high-speed daughter card.

[0074] like Figure 2 As shown, in the ground plane configuration of the present invention, the ground plane of the base plate 11 is divided into a first ground plane for the DCDC switching power supply, a second ground plane for the common mode filter, and a third ground plane for the medium-speed arbitrary waveform generating circuit. At the same time, the ground plane of the high-speed daughter card is divided into a fourth ground plane for the high-speed arbitrary waveform generating circuit, so that the first ground plane, the second ground plane, the third ground plane, and the fourth ground plane are isolated from each other.

[0075] In addition, the first ground plane is specifically set to the PGND plane, the second ground plane is set to the PGND plane or the GND plane, and the third and fourth ground planes are set to the AGND plane. As a result, all DCDC switching power supplies after the external power signal passes through the power filter are on the PGND1 plane, the common-mode filter is on the PGND2 plane or the GND plane, and the LDO of the high-speed daughter card and the backplane LDO are on the relatively clean AGND plane, thereby effectively eliminating the noise conduction path in the ground plane and reducing the impact of noise on the arbitrary waveform generation circuit through the ground plane.

[0076] In summary, the arbitrary waveform generation system of the present invention adopts a hardware architecture that combines a baseboard with a high-speed daughter card, allowing for the convenient implementation of multiple high-speed (4-8GHz) arbitrary waveform generation circuits and multiple medium-speed (DC-700MHz) arbitrary waveform generation circuits on a single board. Through this high-speed, medium-speed combination, the system can cover a wider range of application scenarios, and is particularly well-suited for the needs of quantum technology regulation for high-speed and medium-speed arbitrary waveforms.

[0077] At the same time, the high-speed arbitrary waveform generation circuit (high-speed output channel) is designed separately as a daughter card, which not only reduces the interference of switching power supply noise on the high-speed arbitrary waveform generation circuit, but also allows for easy expansion of output channels to meet the needs of various multi-channel scenarios.

[0078] Furthermore, this utility model innovatively introduces noise suppression technologies such as a power management module combined with an LDO and a unique ground plane split configuration, significantly reducing system noise and improving the signal-to-noise ratio and measurement accuracy. The power management module is implemented using a DC-DC switching power supply and a common-mode filter, while the LDO distributes the operating voltage to each chip. This effectively improves power efficiency and suppresses common-mode noise in the power system, while maintaining output voltage stability.

[0079] By adopting RF direct sampling circuit design in high-speed arbitrary waveform generation circuits, high-order harmonics can be directly filtered out to generate the high signal-to-noise ratio signal required for quantum bit control. The circuit structure is simpler and can also solve the local oscillator leakage and sideband leakage problems caused by IQ mixing signals.

[0080] As a result, the arbitrary waveform generation system of the present invention can obtain the currently urgently needed performance of high integration, ultra-low noise, easy scalability, multi-channel output and high-speed arbitrary waveform generation capability, so that it can be extremely competent for scenarios such as quantum computing control that have high-speed and medium-speed arbitrary waveform requirements and multi-channel requirements.

[0081] At the same time, the highly integrated design of the arbitrary waveform generation system of the utility model can significantly reduce the system volume and weight, improve the system installation flexibility, and the modular design makes the system easy to maintain and upgrade, thereby extending the system service life and reducing long-term operating costs.

[0082] Although the present invention has been described above through specific embodiments in conjunction with the accompanying drawings, it is easy for those skilled in the art to recognize that the above embodiments are merely exemplary and are used to illustrate the principles of the present invention. They do not limit the scope of the present invention. Those skilled in the art can make various combinations, modifications and equivalent substitutions to the above embodiments without departing from the spirit and scope of the present invention.

Claims

1. A highly integrated multi-channel arbitrary waveform generation system for quantum computing, comprising a baseboard on which a control module and a medium-speed arbitrary waveform generation circuit are integrated; It is characterized by It also includes a daughter card, and the baseboard is also integrated with a power filter circuit and a power management module; The daughter card is integrated with a high-speed arbitrary waveform generating circuit; The power supply filter circuit is configured to filter the external power supply signal before the external power supply signal enters the power supply management module; The power management module is configured to generate an internal power signal based on the external power signal; The control module is configured to control the medium-speed arbitrary waveform generating circuit and / or the high-speed arbitrary waveform generating circuit to generate waveform signals.

2. The arbitrary waveform generation system according to claim 1, wherein: The control module includes a communication interface and an FPGA unit integrated on a baseboard, wherein the communication interface is configured to allow data communication between an external device and the FPGA unit, and the FPGA unit is configured to control the medium-speed arbitrary waveform generation circuit and / or the high-speed arbitrary waveform generation circuit to generate waveform signals according to control data; And / or, the operating frequency of the medium-speed arbitrary waveform generating circuit is DC-700 MHz, and the operating frequency of the high-speed arbitrary waveform generating circuit is 4 GHz-8 GHz.

3. The arbitrary waveform generation system according to claim 1, wherein: The high-speed arbitrary waveform generating circuit includes a high-speed digital-to-analog converter and a filtering and shaping circuit.

4. The arbitrary waveform generation system according to claim 1, wherein: The power supply filter circuit is arranged at the power supply inlet of the base plate.

5. The arbitrary waveform generation system according to claim 1, wherein: The power management module includes a DCDC switching power supply and a common mode filter; The DCDC switching power supply is configured to generate an internal power signal based on the external power signal; The common mode filter is configured to filter the internal power supply signal.

6. The arbitrary waveform generation system according to claim 5, wherein: The daughter card is integrated with a low-dropout linear regulator, which is configured to provide an operating voltage for the high-speed arbitrary waveform generation circuit based on the internal power supply signal; and / or, A low voltage dropout linear regulator is integrated on the bottom plate and is configured to provide an operating voltage for a medium-speed arbitrary waveform generating circuit based on the internal power supply signal.

7. The arbitrary waveform generation system according to claim 5, wherein: The bottom plate is provided with a first ground plane for the DCDC switching power supply, a second ground plane for the common mode filter, and a third ground plane for the medium-speed arbitrary waveform generating circuit; The daughter card is provided with a fourth ground plane for the high-speed arbitrary waveform generating circuit; The first ground plane, the second ground plane, the third ground plane and the fourth ground plane are isolated from each other.

8. The arbitrary waveform generation system according to claim 7, wherein: The first ground plane is a PGND plane; The second ground plane is a PGND plane or a GND plane; The third ground plane and the fourth ground plane are AGND planes.

9. The arbitrary waveform generation system according to claim 2, wherein: The data frame used for control data includes a frame header, a command part, a waveform data part, a check code and a frame tail; The frame header is used to identify the beginning of the data frame; The instruction part includes control instructions for instructing the operation of the arbitrary waveform generating circuit and parameter settings for instructing waveform parameters; The waveform data portion includes the waveform data itself; The check code is used to check the integrity and / or accuracy of the data frame; The frame tail is used to mark the end of the data frame.

10. The arbitrary waveform generation system according to claim 3, wherein: The filtering and shaping circuit includes a high roll-off low-pass filtering circuit.

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