Integrated device

Abstract

The utility model provides an integrated device. The integrated device comprises a substrate; an interconnect structure disposed on the substrate, the interconnect structure including a dielectric substance; a first bottom electrode structure disposed in the dielectric, the first bottom electrode structure having a first width measured between outer sidewalls of the first bottom electrode structure and a first depth measured from an upper surface of the dielectric; and a second bottom electrode structure disposed in the dielectric and spaced apart from the first bottom electrode structure, the second bottom electrode structure having a second width measured between outer sidewalls of the second bottom electrode structure and a second depth measured from an upper surface of the dielectric; wherein the first width is greater than the second width and the first depth is greater than the second depth.

Description

Technical Field

[0001] The utility model relates to an integrated device. Background Art

[0002] Many current electronic devices include capacitors. The capacitance of a capacitor depends on several factors, including the surface area of the first and second electrodes, the proximity of the first and second electrodes, and the permittivity of the dielectric between the first and second electrodes. Depending on the target capacitance and space availability in the electronic device, the surface area of the first and second electrodes can be formed horizontally across the electronic device, vertically, or both. Utility Model Content

[0003] The utility model provides an integrated device, comprising: a substrate; an internal connection structure arranged on the substrate, the internal connection structure including an interlayer dielectric; a first bottom electrode structure arranged in the interlayer dielectric, wherein the first bottom electrode structure has a first width measured between the outer side walls of the first bottom electrode structure and has a first depth measured from the upper surface of the interlayer dielectric; and a second bottom electrode structure arranged in the interlayer dielectric and spaced apart from the first bottom electrode structure, wherein the second bottom electrode structure has a second width measured between the outer side walls of the second bottom electrode structure and has a second depth measured from the upper surface of the interlayer dielectric; wherein the first width is greater than the second width, and the first depth is greater than the second depth.

[0004] The utility model provides an integrated device, comprising: a substrate; an internal connection structure, arranged on the substrate; and a capacitor array, comprising: a plurality of capacitors arranged in the internal connection structure, wherein the plurality of capacitors include a plurality of horizontal portions of a plurality of bottom electrodes arranged at a first height; and a plurality of bottom electrode structures of the plurality of capacitors extending from the plurality of horizontal portions of the plurality of bottom electrodes, the plurality of bottom electrode structures extending to a plurality of different depths measured from the first height, including a minimum depth and a maximum depth among the plurality of different depths, and having a plurality of different widths measured between outer sidewalls of the plurality of bottom electrode structures, including a minimum width and a maximum width among the plurality of different widths; wherein a first bottom electrode structure among the plurality of bottom electrode structures has the minimum depth and the minimum width, and wherein a plurality of bottom electrode structures among the plurality of bottom electrode structures having a gradually increasing width up to the maximum width have a gradually increasing depth up to the maximum depth. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1 Cross-sectional views of some embodiments of an integrated chip having multiple capacitors with bottom electrode structures of varying depths and widths are shown.

[0007] Figure 2 Cross-sectional views of some additional embodiments of an integrated chip are shown having multiple capacitors with bottom electrode structures of varying depths and widths coupled to multiple conductive lines underlying the capacitors.

[0008] Figures 3A to 3D Cross-sectional views of some additional embodiments of integrated chips with capacitors having multiple bottom electrode structures of varying depths and widths are shown.

[0009] Figures 4A to 4C Cross-sectional views and graphs illustrate some additional embodiments of integrated chips having capacitors with multiple bottom electrode structures of varying depths and widths.

[0010] Figures 5 to 11 Cross-sectional views illustrating some embodiments of methods of forming an integrated chip having multiple capacitors with bottom electrode structures having different depths and widths.

[0011] Figure 12 A flow chart illustrating some embodiments of a method of forming an integrated chip having multiple capacitors with bottom electrode structures of different depths and widths.

[0012] [Explanation of Figure Numbers]

[0013] 100, 200, 400a, 400b, 500, 600, 700, 800, 900, 1000, 1100: cross-sectional views;

[0014] 102: substrate;

[0015] 104a: a first capacitor;

[0016] 104b: a second capacitor;

[0017] 104c: a third capacitor;

[0018] 106a: first bottom electrode structure / bottom electrode structure;

[0019] 106b: second bottom electrode structure / bottom electrode structure;

[0020] 106c: third bottom electrode structure / bottom electrode structure;

[0021] 106d: fourth bottom electrode structure;

[0022] 106e: fifth bottom electrode structure;

[0023] 108: interlayer dielectric;

[0024] 110: etching stop layer;

[0025] 112a: first bottom electrode;

[0026] 112b: second bottom electrode;

[0027] 112c: third bottom electrode;

[0028] 114a: first dielectric;

[0029] 114b: second dielectric;

[0030] 114c: third dielectric;

[0031] 116a: first top electrode;

[0032] 116b: second top electrode;

[0033] 116c: third top electrode;

[0034] 118: Anti-reflective coating (ARC);

[0035] 120: passivation layer;

[0036] 122: First barrier layer;

[0037] 124: first conductor level;

[0038] 126: upper surface;

[0039] 128: additional dielectric layer;

[0040] 130a: first horizontal portion;

[0041] 130b: second horizontal portion;

[0042] 132: wire;

[0043] 134: through hole;

[0044] 202a, 202b, 202c: second conductor level;

[0045] 300a, 300b, 300c, 300d: cross-sectional views;

[0046] 302: hard mask;

[0047] 308a: first groove / groove;

[0048] 308b: second groove / groove;

[0049] 400c: curve graph;

[0050] 402: Gap;

[0051] 404: Spheroid;

[0052] 406: midline;

[0053] 408, 410: line;

[0054] 502: first mask layer;

[0055] 504a: first opening;

[0056] 504b: second opening;

[0057] 602: first etching process;

[0058] 702: first conformal electrode layer;

[0059] 704: Conformal dielectric;

[0060] 706: second conformal electrode layer;

[0061] 708: conformal ARC layer;

[0062] 1200: Method;

[0063] 1202, 1204, 1206, 1208, 1210: action;

[0064] d1: first depth / depth;

[0065] d2: second depth / depth;

[0066] d3: third depth;

[0067] d4: fourth depth;

[0068] R1: first maximum curvature radius / maximum curvature radius;

[0069] R2: second maximum curvature radius / maximum curvature radius;

[0070] R3: third maximum curvature radius / maximum curvature radius;

[0071] R4: maximum curvature radius;

[0072] t1: first thickness;

[0073] t2: second thickness;

[0074] t3: third thickness;

[0075] w1: first width / width;

[0076] w2: second width / width;

[0077] w3: third width / width;

[0078] w4: fourth width / width. DETAILED DESCRIPTION

[0079] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0080] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0081] Capacitors are used in integrated devices for a variety of purposes, including memory, image processing, and sensing devices. The capacitance of a capacitor depends on a number of factors, including the surface area of the first and second electrodes, the proximity of the first and second electrodes, and the dielectric constant of the dielectric between the first and second electrodes. When formed using a back-end-of-line (BEOL) process, the capacitor can be formed with a surface area extending across the dielectric, with a surface area confined to a trench etched into the dielectric, or a combination of the two distributions. A single etching process can be used to pattern capacitors that extend horizontally across the dielectric, and a variety of capacitances can be achieved without increasing the number of etchings used, although the capacitors use a larger surface area of the integrated chip than vertical capacitors. Vertical capacitors (e.g., capacitors formed in trenches) extend vertically across the integrated device and therefore use a smaller surface area of the integrated chip than horizontally extended capacitors, which can allow a higher density of capacitors to fit into a single layer of the integrated device. However, methods for forming vertical capacitors typically use separate multiple masks and multiple etching steps to form multiple trenches of varying depths to form the vertical capacitors, resulting in increased cost and limited flexibility. Capacitors utilizing a combination of horizontal and vertical structures increase the flexibility of capacitor arrays, but reduce the density of capacitors that can be fitted into a single layer of an integrated device. A capacitor array is desired that combines the high capacitor density achievable with an array of vertical capacitors with the reduced number of masking and etching steps and capacitance flexibility achievable with an array of horizontally extended capacitors.

[0082] The present disclosure provides an integrated device comprising capacitors having bottom electrode structures of different widths and different depths. The capacitors are formed by etching a plurality of trenches of various depths in a dielectric layer. The plurality of trenches are etched using a single etching process and a masking layer having a plurality of openings of varying widths. Due to an etch-loading effect, the width of the openings in the masking layer causes the etch rate of the plurality of trenches to vary. The difference in etching rate causes the plurality of trenches to have different depths. Capacitors are then formed in the plurality of trenches. The capacitors formed in the trenches having a greater depth and width have a greater surface area. The difference in the surface area of the capacitors allows the capacitors to have different capacitances without having large variations in the horizontal surface area used for each capacitor or in the multiple etching steps used for different depths. Therefore, the proposed method is more cost-effective and flexible than related methods for capacitor production.

[0083] Figure 1A cross-sectional view 100 of some embodiments of an integrated chip having multiple capacitors with bottom electrode structures of different depths and different widths is shown.

[0084] An interconnect structure including an interlayer dielectric 108 is formed on the substrate 102. A first bottom electrode 112a and a second bottom electrode 112b are formed on the upper surface 126 of the interlayer dielectric 108. In some embodiments, the first bottom electrode 112a and the second bottom electrode 112b are separated by a passivation layer 120 and are part of the first capacitor 104a and the second capacitor 104b, respectively.

[0085] A first dielectric 114a and a first top electrode 116a overlie the first bottom electrode 112a. The first dielectric 114a separates the first bottom electrode 112a from the first top electrode 116a. A second dielectric 114b and a second top electrode 116b overlie the second bottom electrode 112b. The second dielectric 114b separates the second bottom electrode 112b from the second top electrode 116b.

[0086] The first bottom electrode 112a has a first width (also referred to as width) w1 measured between the outer sidewalls of the first bottom electrode 112a. The first bottom electrode 112a further has a first depth (also referred to as depth) d1 measured from the upper surface 126 of the interlayer dielectric 108. The second bottom electrode 112a has a second width (also referred to as width) w2 measured between the outer sidewalls of the second bottom electrode 112b. The second bottom electrode 112b further has a second depth (also referred to as depth) d2 measured from the upper surface 126 of the interlayer dielectric 108. The first width w1 is greater than the second width w2, and the first depth d1 is greater than the second depth d2. The difference between the first depth d1 and the second depth d2 can be attributed to a dimensional difference in the etch loading effect that occurs during the etching process before forming the first and second bottom electrodes 112a, 112b. The dimensional difference in the etch loading effect is the result of the difference between the first width w1 and the second width w2, where the larger width results in a greater etch depth.

[0087] In some embodiments, a first width w1 is measured between outer sidewalls of a first bottom electrode structure (also referred to as bottom electrode structure) 106a of the first bottom electrode 112a. Similarly, a second width w2 is measured between outer sidewalls of a second bottom electrode structure (also referred to as bottom electrode structure) 106b of the second bottom electrode 112b. In other embodiments, a first depth d1 is measured from the upper surface 126 of the interlayer dielectric 108 to the bottom surface of the first bottom electrode structure 106a, and a second depth d2 is measured from the upper surface 126 of the interlayer dielectric 108 to the bottom surface of the second bottom electrode structure 106b. The first bottom electrode structure 106a extends from a first horizontal portion 130a of the first bottom electrode 112a that overlies the upper surface 126 of the interlayer dielectric 108. The second bottom electrode structure 106b extends from a second horizontal portion 130b of the second bottom electrode 112b that overlies the upper surface 126 of the interlayer dielectric 108. In some embodiments, the first horizontal portion 130a has a first area, and the second horizontal portion 130b has a second area different from the first area. In some embodiments, the first bottom electrode structure 106a extends through the one or more etch stop layers 110. In other embodiments, the second bottom electrode structure 106b does not extend through the one or more etch stop layers 110. In some embodiments, the first bottom electrode structure 106a and the second bottom electrode structure 106b are part of a single capacitor and are electrically coupled by a metal line (not shown) running continuously between the first bottom electrode structure 106a and the second bottom electrode structure 106b.

[0088] An anti-reflective coating (ARC) 118 overlies the first and second top electrodes 116a, 116b. A passivation layer 120 conformally overlies the ARC 118, the first and second top electrodes 116a, 116b, and an upper surface 126 of the interlayer dielectric 108. Disposed above the passivation layer 120 is an additional dielectric layer 128 of the interlayer dielectric 108. Disposed within the additional dielectric layer 128 is a first wire level 124. The first wire level 124 includes a plurality of wires 132 and a plurality of vias 134 electrically coupled to the first and second capacitors 104a, 104b. In some embodiments, the first wire level 124 is separated from the additional dielectric layer 128 of the interlayer dielectric 108 by a first barrier layer 122. In some embodiments, the first barrier layer 122 may include a metal nitride such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or similar materials, or a combination thereof. In some embodiments, the top surfaces of the first bottom electrode 112a and the second bottom electrode 112b are electrically coupled to the conductive line 132 in the first conductive line level 124. In some embodiments, the top surfaces of the first bottom electrode 112a and the second bottom electrode 112b contact the via 134 or the first barrier layer 122 surrounding the via 134, thereby contacting the first conductive line level 124.

[0089] Figure 2 A cross-sectional view 200 illustrates some additional embodiments of an integrated chip having multiple capacitors with bottom electrode structures of varying depths and widths coupled to multiple conductive lines located beneath the capacitors.

[0090] In some embodiments, the bottom surfaces of the first and second bottom electrode structures 106a, 106b contact second wire levels 202a, 202b, and 202c located below the bottom surfaces. By using the first wire level 124 to contact the first top electrode 116a and the second wire levels 202a, 202b, and 202c to contact the first bottom electrode structure 106a, this embodiment reduces the horizontal area of the first capacitor 104a used to connect the two electrodes to the first wire level 124. Reducing the horizontal area used by individual capacitors can increase the density of capacitors in an integrated chip.

[0091] In some embodiments, the third capacitor 104c may include a third bottom electrode structure (also referred to as bottom electrode structure) 106c and a fourth bottom electrode structure 106d extending to the second conductive levels 202a, 202b, and 202c. A third dielectric 114c separates the third and fourth bottom electrode structures 106c, 106d from a third top electrode 116c. Both the third and fourth bottom electrode structures 106c, 106d increase the capacitance of the third capacitor 104c. Varying the number of bottom electrode structures extending from the first, second, and third bottom electrodes 112a, 112b, and 112c expands the variety of different profiles that can achieve similar capacitance and extends the range of capacitances that can be provided using this approach.

[0092] In some embodiments, the first bottom electrode structure 106a may have a first width w1 and a first depth d1, the second bottom electrode structure 106b may have a second width w2 and a second depth d2, and the third and fourth bottom electrode structures 106c and 106d may have a third width (also referred to as width) w3 and a third depth d3. The difference in depth of the bottom electrode structures is related to the difference in width of the bottom electrode structures. That is, the first bottom electrode structure 106a has a first width w1 that is greater than the second width w2 of the second bottom electrode structure 106b, and also has a first depth d1 that is greater than the second depth d2 of the second bottom electrode structure 106b. The difference in widths w1 and w2 causes a dimensional difference in the etch loading effect during the formation of the first and second capacitors 104a and 104b, resulting in different etch rates and different depths d1 and d2 for the first and second capacitors 104a and 104b. Therefore, the difference between the first depth d1 and the second depth d2 is a result of the difference between the first width w1 and the second width w2. The third bottom electrode structure 106c and the fourth bottom electrode structure 106d have a third width w3 that is smaller than the second width w2, and thus have a third depth d3 that is smaller than the second depth d2.

[0093] Figures 3A to 3D Some additional embodiments of integrated chips with capacitors having multiple bottom electrode structures of different depths and different widths are shown (cross-sectional views 300a to 300d).

[0094] like Figure 3AAs shown in cross-sectional view 300a of FIG, in some embodiments, the first capacitor 104a may include a first bottom electrode structure 106a, a second bottom electrode structure 106b, and a third bottom electrode structure 106c. The first, second, and third bottom electrode structures 106a, 106b, and 106c may have a first depth d1, a second depth d2, and a third depth d3, respectively, and a first width w1, a second width w2, and a third width w3. During the etching process used before forming the first bottom electrode 112a, variations in the etching loading effect cause the bottom electrode structure with the smallest width to have the smallest depth, and the bottom electrode structure with the largest width to have the largest depth. For example, the first width w1 is smaller than the second width w2 and the third width w3. The second width w2 is larger than the third width w3. Therefore, the first bottom electrode structure 106a has the smallest width, such that the first depth d1 is the smallest depth (e.g., smaller than the second depth d2 and the third depth d3). Furthermore, the second bottom electrode structure 106 b has a maximum width, such that the second depth d2 is a maximum depth (eg, greater than the first depth d1 and the third depth d3 ).

[0095] In other embodiments, the second capacitor 104b may include a fourth bottom electrode structure 106d and a fifth bottom electrode structure 106e. The fourth and fifth bottom electrode structures 106d and 106e may have a fourth width (also referred to as width) w4. That is, the fourth bottom electrode structure 106d may have a fourth width w4 that is substantially equal to the width of the fifth bottom electrode structure. The width of the fourth and fifth bottom electrode structures 106d and 106e is substantially equal, such that the depth of the fourth and fifth bottom electrode structures 106d and 106e is substantially equal. The fourth and fifth bottom electrode structures 106d and 106e have a fourth depth d4.

[0096] The first capacitor 104a and the second capacitor 104b may be part of a plurality of capacitors, each of which may have a plurality of bottom electrode structures having depths different from a first depth d1, a second depth d2, a third depth d3, and a fourth depth d4. In some embodiments, the first bottom electrode structure 106a of the plurality of bottom electrode structures has a minimum width and a minimum depth. In other embodiments, the bottom electrode structures of the plurality of bottom electrode structures having a gradually increasing width to a maximum width have a gradually increasing depth to a maximum depth. In other embodiments, the second bottom electrode structure of the plurality of bottom electrode structures (e.g., the second bottom electrode structure 106b) has a median depth of the plurality of different depths and a median width of the plurality of different widths. A plurality of top electrodes extend between the inner sidewalls of the plurality of bottom electrode structures.

[0097] In some embodiments, the first width w1 is between 80 nanometers and 120 nanometers, between 95 nanometers and 105 nanometers, or similar dimensions. In some embodiments, the first depth d1 is between 500 nanometers and 800 nanometers, between 625 nanometers and 675 nanometers, or similar dimensions. In some embodiments, the second width w2 is between 130 nanometers and 170 nanometers, between 145 nanometers and 155 nanometers, or similar dimensions. In some embodiments, the second depth d2 is between 1000 nanometers and 1300 nanometers, between 1100 nanometers and 1150 nanometers, or similar dimensions. In some embodiments, the third width w3 is between 90 nanometers and 130 nanometers, between 105 nanometers and 115 nanometers, or similar dimensions. In some embodiments, the third depth d3 is between 750 nanometers and 1050 nanometers, between 900 nanometers and 950 nanometers, or similar dimensions. In other embodiments, different ranges of widths and depths are used in one or more bottom electrode structures to produce capacitors with different capacitances and cross-sectional profiles.

[0098] like Figure 3B As shown in the cross-sectional view 300b of FIG, a hard mask 302 may be present above the upper surface 126 of the interlayer dielectric 108. In some embodiments, the hard mask 302 is or includes silicon nitride (Si3N4) or a similar material. The hard mask 302 surrounds the multiple bottom electrode structures of the first bottom electrode 112a and the second bottom electrode 112b. In some embodiments, the hard mask 302 extends between the multiple bottom electrode structures (including between the first bottom electrode structure 106a and the second bottom electrode structure 106b). In some embodiments, a first trench (also referred to as a trench) 308a and a second trench (also referred to as a trench) 308b (see FIG. 3 ) are formed in which the first bottom electrode structure 106a and the second bottom electrode structure 106b are subsequently formed. Figure 3D ), the hard mask 302 remains unchanged and has inner sidewalls that correspond one-to-one with the bottom electrode. If the hard mask 302 is present, this one-to-one correspondence allows multiple trenches in which the bottom electrode is formed to be formed by a single etch using the hard mask 302. The different depths of the multiple trenches can demonstrate an etch loading effect, thus demonstrating a very efficient manufacturing process.

[0099] like Figure 3CAs shown in cross-sectional view 300c of FIG, in some embodiments, the outer sidewalls of the first bottom electrode 112a in the first, second, and third bottom electrode structures 106a, 106b, and 106c may have different curvatures near the upper surface 126 of the interlayer dielectric 108. For example, the first maximum radius of curvature (also known as the maximum radius of curvature) R1 of the first bottom electrode structure 106a may be smaller than the second maximum radius of curvature (also known as the maximum radius of curvature) R2 of the second bottom electrode structure 106b. Furthermore, the third maximum radius of curvature (also known as the maximum radius of curvature) R3 of the third bottom electrode structure 106c may be smaller than the second maximum radius of curvature R2 of the second bottom electrode structure 106b but larger than the first maximum radius of curvature R1 of the first bottom electrode structure 106a. In some embodiments, the radius of curvature may vary at the corners of the bottom electrode structures. That is, the first bottom electrode structure 106a may have a radius of curvature that is smaller than the first maximum radius of curvature R1 at a location near the upper surface 126 of the interlayer dielectric 108.

[0100] In some embodiments, the maximum radii of curvature R1, R2, R3 are related to the widths w1, w2, w3 of the plurality of bottom electrode structures 106a, 106b, 106c such that the bottom electrode structure with the smallest width (e.g., the first bottom electrode structure 106a) has the smallest maximum radius of curvature (e.g., the first maximum radius of curvature R1). Furthermore, the bottom electrode structure with the largest width (e.g., the second bottom electrode structure 106b) has the largest maximum radius of curvature (e.g., the second maximum radius of curvature R2). The fourth and fifth bottom electrode structures 106d, 106e of the second capacitor 104b have substantially equal widths w4 and, therefore, substantially equal maximum radii of curvature R4. The difference in the maximum radii of curvature R1, R2, R3, R4 between the plurality of bottom electrode structures may be due to the fact that the trenches 308a, 308b formed prior to forming the bottom electrode structures (see Figure 3D ) results of different etching rates between .

[0101] like Figure 3DAs shown in the cross-sectional view 300d of FIG, in some embodiments, the thickness of the hard mask 302 directly located between the first bottom electrode structure 106a, the second bottom electrode structure 106b, and the third bottom electrode structure 106c is less than the thickness of the hard mask 302 located between the first capacitor 104a and the second capacitor 104b. For example, a first thickness t1 of the hard mask 302 measured between the first bottom electrode structure 106a and the second bottom electrode structure 106b is less than a third thickness t3 of the hard mask 302 measured between the first capacitor 104a and the second capacitor 104b. Furthermore, a second thickness t2 of the hard mask 302 measured between the second bottom electrode structure 106b and the third bottom electrode structure 106c is less than both the first thickness t1 and the third thickness t3.

[0102] The difference in thickness between the first thickness t1, the second thickness t2, and the third thickness t3 is due to the etch loading effect present when etching the first trench 308a and the second trench 308b surrounding the first and second thicknesses t1 and t2. The etch rate of the interlayer dielectric 108 and the hard mask 302 is lower for the first trench 308a filled with the first bottom electrode structure 106a than for the second trench 308b filled with the second bottom electrode structure 106b. This difference in etch rate is due to the first trench 308a having a first width w1 being smaller than the second width w2 of the second trench 308b. The smaller width w1 than w2 allows a smaller amount of etchant to react with the hard mask and interlayer dielectric in the first trench 308a, which in turn results in less material being removed near the opening of the first trench 308a compared to the second trench 308b. The greater amount of material removed at the opening of the second trench 308b may result in the removal of an upper portion of the hard mask. Portions of the hard mask 302 directly between the bottom electrode structures (e.g., between the first bottom electrode structure 106a and the second bottom electrode structure 106b) may be etched from multiple directions, which may result in a greater amount of hard mask etching and a reduced thickness of the hard mask 302 at those locations.

[0103] Figures 4A to 4C Cross-sectional views 400a, 400b and graph 400c illustrate some additional embodiments of integrated chips having capacitors with multiple bottom electrode structures of different depths and different widths.

[0104] like Figure 4AAs shown, in some embodiments, a plurality of gaps 402 may exist within the plurality of bottom electrode structures. In some embodiments, the plurality of bottom electrode structures may have bulbs 404 where the widths of the plurality of bottom electrode structures are at a local maximum. The bulbs 404 are sections of the plurality of bottom electrode structures where the width of the bottom electrode structure increases to a middle line 406 at a local maximum in width. The width then decreases back to the width of the bottom electrode structure before the width began to increase at the bulbs 404. The bulbs 404 in the plurality of bottom electrode structures are located near the upper surface 126 of the interlayer dielectric 108. In other embodiments, the middle lines 406 of the bulbs 404 are located at a depth below the upper surface 126 of the interlayer dielectric 108 that is independent of the depth of the plurality of bottom electrode structures. That is, the center line 406 extends through the maximum width of the balls 404 in the first, second, and third bottom electrode structures 106 a, 106 b, and 106 c and is substantially parallel to the upper surface 126 of the interlayer dielectric 108 .

[0105] like Figure 4B As shown, in some embodiments, the second capacitor 104b may have a second bottom electrode structure 106b and a third bottom electrode structure 106c extending below the first conductive line level 124. Varying the number of bottom electrode structures extending from the first bottom electrode 112a, the second bottom electrode 112b, and the third bottom electrode 112c expands the variety of different profiles that can achieve similar capacitance and expands the range of capacitances that can be provided using this fabrication method.

[0106] like Figure 4C As shown, during the etching process, there is a positive correlation between the etch depth and the opening width. That is, for a certain range of opening widths, a trench with a larger opening width will have a larger etch depth for the same etching process. Line 408 shows Figure 4A The etch depth and opening width are shown in FIG. 4 , and line 410 shows the trend line of the data shown in line 408 .

[0107] Figures 5 to 11 Cross-sectional views 500 to 1100 illustrate some embodiments of a method of forming an integrated chip having a plurality of capacitors with bottom electrode structures of varying depths and widths. Figures 5 to 11 , however, it should be understood that Figures 5 to 11 The structure disclosed in the invention is not limited to such a method, but can exist independently as a structure independent of the method.

[0108] like Figure 5As shown in the cross-sectional view 500 of FIG, a substrate 102 is provided. An interlayer dielectric 108 is provided on the substrate 102, and in some embodiments, the interlayer dielectric 108 is periodically interleaved with an etch stop layer 110. A first mask layer 502 is formed on the interlayer dielectric 108. In some embodiments, the first mask layer 502 is a photoresist formed using a spin-on process. In other embodiments, the first mask layer 502 is a hard mask 302 formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other suitable deposition process, or a combination of the foregoing processes. The first mask layer 502 is then patterned to produce a first opening 504a and a second opening 504b. In some embodiments, the first mask layer 502 is patterned using photolithography. The first opening 504 a has a first width w1 , and the second opening 504 b has a second width w2 smaller than the first width w1 .

[0109] like Figure 6 As shown in cross-sectional view 600 of FIG, a first etching process 602 is performed. During the first etching process 602, the interlayer dielectric 108 is etched in the areas exposed by the first opening 504a and the second opening 504b in the first mask layer 502. In some embodiments, the first etching process 602 may be a dry etch, such as a plasma etch or the like. The first etching process 602 produces a first trench 308a formed below the first opening 504a and a second trench 308b formed below the second opening 504b. The first trench 308a has a first width w1 and is etched to a first depth d1, and the second trench 308b has a second width w2 and is etched to a second depth d2. Due to the difference in etch rates between the first trench 308a and the second trench 308b, the second depth d2 is less than the first depth d1. The difference in etch rate is due to the second width w2 being less than the first width w1. During the etching process, the smaller width of the second trench 308b causes less etchant to reach the bottom of the second trench 308b than the amount of etchant that may reach the bottom of the first trench 308a. Since the etching rates of the first trench 308a and the second trench 308b depend on the widths of the first opening 504a and the second opening 504b, respectively, the first trench 308a and the second trench 308b can be formed to different depths using the same mask during a single etching process.

[0110] like Figure 7As shown in the cross-sectional view 700 of FIG, a first conformal electrode layer 702, a conformal dielectric layer 704, a second conformal electrode layer 706, and a conformal ARC layer 708 are deposited on the upper surface 126 of the interlayer dielectric 108. In some embodiments, the first conformal electrode layer 702, the conformal dielectric layer 704, the second conformal electrode layer 706, and the conformal ARC layer 708 can be deposited using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing processes. In some embodiments, before forming the first conformal electrode layer 702, the first mask layer 502 (see FIG. 5 ) is removed. Figure 6 ). In other embodiments, the first mask layer 502 is a hard mask and is not removed prior to forming the first conformal electrode layer 702. The first conformal electrode layer 702, the conformal dielectric 704, and the second conformal electrode layer 706 extend into the first trench 308a and the second trench 308b. The conformal dielectric 704 overlies the first conformal electrode layer 702 and separates the first conformal electrode layer 702 from the second conformal electrode layer 706. In some embodiments, the first conformal electrode layer 702 and the second conformal electrode layer 706 are or include copper (Cu), titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), tantalum nitride (TaN), or similar materials, or any combination thereof. In some embodiments, the conformal dielectric 704 is or includes silicon oxide (SiO2), silicon nitride (Si3N4), a high-k dielectric, or similar materials, or some combination thereof.

[0111] like Figure 8 As shown in the cross-sectional view 800, the first conformal electrode layer 702 and the conformal dielectric 704 (see Figure 7 ), second conformal electrode layer 706 (see Figure 7 ) and conformal ARC layer 708 (see Figure 7 ) is etched to produce a first bottom electrode 112a, a second bottom electrode 112b, a first dielectric 114a, a second dielectric 114b, a first top electrode 116a, and a second top electrode 116b. In some embodiments, the etching may be plasma etching or the like. In some embodiments, a portion of the upper surface of the first bottom electrode 112a and the second bottom electrode 112b is exposed and will be coupled to the first conductive line level 124 above the first bottom electrode 112a (see Figure 1 ), as shown in a later step (see Figure 11 In other embodiments, the upper surfaces of the first bottom electrode 112a and the second bottom electrode 112b are completely covered by the first dielectric 114a and the second dielectric 114b. In addition, the bottom surfaces of the first bottom electrode 112a and the second bottom electrode 112b are formed such that they contact the second conductive line level 202a, 202b, 202c below the bottom electrode (see Figure 2 ).

[0112] like Figure 9 As shown in cross-sectional view 900 of FIG, a passivation layer 120 is deposited over the upper surface 126 of the interlayer dielectric 108. The passivation layer 120 can be deposited using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing processes. The passivation layer 120 conformally overlies the antireflective coating 118, the first and second bottom electrodes 112 a and 112 b, the first and second dielectrics 114 a and 114 b, the first and second top electrodes 116 a and 116 b, and the upper surface 126 of the interlayer dielectric 108.

[0113] like Figure 10 As shown in cross-sectional view 1000 of FIG, an additional dielectric layer 128 is formed over the upper surface of the interlayer dielectric 108. In some embodiments, the additional dielectric layer 128 comprises the same material as the interlayer dielectric 108. In some embodiments, the additional dielectric layer 128 is formed using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing processes.

[0114] like Figure 11 As shown in cross-sectional view 1100 of FIG, a first barrier layer 122 and a first conductive level 124 are formed in the additional dielectric layer 128. In some embodiments, multiple etching processes are used to form multiple openings to form the first barrier layer 122 and the first conductive level 124. The openings are then filled with a conformal barrier layer (not shown) and a conformal conductive layer (not shown). A planarization process (e.g., a chemical mechanical planarization (CMP) process) is then performed to remove portions of the conformal barrier layer and the conformal conductive layer located above the upper surface of the additional dielectric layer 128.

[0115] Figure 12 A flow chart illustrating some embodiments of a method of forming an integrated chip having multiple capacitors with bottom electrodes of different depths and different widths.

[0116] Although method 1200 is shown and described below as a series of actions or events, it should be understood that the order in which such actions or events are shown should not be construed as having a limiting meaning. For example, some actions may occur in a different order and / or simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown may be required when implementing one or more aspects or embodiments described herein. In addition, one or more of the actions illustrated herein may be performed in one or more separate actions and / or stages.

[0117] At 1202, an interlayer dielectric is formed over a substrate. Figure 5 Cross-sectional view 500 is shown corresponding to some embodiments of act 1202 .

[0118] At 1204, a photoresist is deposited over the upper surface of the interlayer dielectric. Figure 5 Cross-sectional view 500 is shown corresponding to some embodiments of act 1204 .

[0119] At 1206 , the photoresist is patterned to create a first opening and a second opening in the photoresist, the first opening having a first width and the second opening having a second width smaller than the first width. Figure 5 Cross-sectional view 500 is shown corresponding to some embodiments of act 1206 .

[0120] At 1208 , the dielectric is etched using a single etch process to create a first trench directly beneath the first opening and a second trench directly beneath the second opening. Figure 6 A cross-sectional view 600 corresponding to some embodiments of act 1208 is shown.

[0121] At 1210 , a first capacitor is formed in a first trench and a second capacitor is formed in a second trench, the first trench having a first depth and the second trench having a second depth less than the first depth. Figures 7 to 11 Cross-sectional views 700 through 1100 are shown corresponding to some embodiments of act 1210 .

[0122] Therefore, the present disclosure is directed to a novel method of forming an integrated chip having multiple capacitors with bottom electrode structures of different depths and different widths.

[0123] Therefore, in some embodiments, the present disclosure relates to an integrated device, comprising: a substrate; an interconnect structure disposed above the substrate, the interconnect structure comprising an interlayer dielectric; a first bottom electrode structure disposed in the interlayer dielectric, the first bottom electrode structure having a first width measured between outer sidewalls of the first bottom electrode structure and a first depth measured from an upper surface of the interlayer dielectric; and a second bottom electrode structure disposed in the interlayer dielectric and spaced apart from the first bottom electrode structure, the second bottom electrode structure having a second width measured between outer sidewalls of the second bottom electrode structure and a second depth measured from the upper surface of the interlayer dielectric; wherein the first width is greater than the second width, and the first depth is greater than the second depth.

[0124] In one embodiment, in the integrated device, the first bottom electrode structure is electrically coupled to the second bottom electrode structure via a metal line, the metal line extending from the first bottom electrode structure across the upper surface of the interlayer dielectric to the second bottom electrode structure. In one embodiment, the integrated device further includes: a third bottom electrode structure disposed in the interlayer dielectric and electrically coupled to the first bottom electrode structure via the metal line, wherein the third bottom electrode structure has a third width measured between outer sidewalls of the third bottom electrode structure and a third depth measured from the upper surface of the interlayer dielectric; wherein the third width is substantially equal to the first width, and the third depth is substantially equal to the first depth. In one embodiment, the integrated device further includes: a first via electrically coupled to the first bottom electrode structure and extending above the first bottom electrode structure. In one embodiment, the integrated device further includes: a first via electrically coupled to the first bottom electrode structure and extending below the first bottom electrode structure. In one embodiment, the integrated device further includes: a hard mask surrounding the outer sidewalls of the first bottom electrode structure.

[0125] In other embodiments, the present disclosure relates to a capacitor array, comprising: a plurality of capacitors arranged in an interconnect structure, the plurality of capacitors comprising a plurality of horizontal portions of a plurality of bottom electrodes arranged at a first height; a plurality of bottom electrode structures of the plurality of capacitors extending from the plurality of horizontal portions of the plurality of bottom electrodes, the plurality of bottom electrode structures extending to a plurality of different depths measured from the first height, including a minimum depth and a maximum depth among the plurality of different depths, and having a plurality of different widths measured between outer sidewalls of the plurality of bottom electrode structures, including a minimum width and a maximum width among the plurality of different widths; wherein a first bottom electrode structure among the plurality of bottom electrode structures has the minimum depth and the minimum width, and wherein a plurality of bottom electrode structures among the plurality of bottom electrode structures having gradually increasing depths up to the maximum depth have gradually increasing widths up to the maximum width.

[0126] In one embodiment, in the capacitor array, the plurality of capacitors further include a plurality of top electrodes extending into the plurality of bottom electrode structures. In one embodiment, the capacitor array further includes: a hard mask in contact with the plurality of horizontal portions of the plurality of capacitors and the plurality of bottom electrode structures. In one embodiment, in the capacitor array, one of the plurality of capacitors has a plurality of bottom electrode structures among the plurality of bottom electrode structures. In one embodiment, in the capacitor array, a first portion of the plurality of bottom electrode structures extends through one or more etch stop layers, and a second portion of the plurality of bottom electrode structures has a plurality of bottom surfaces located above the one or more etch stop layers. In one embodiment, in the capacitor array, a second bottom electrode structure among the plurality of bottom electrode structures has a depth intermediate to the plurality of different depths and a width intermediate to the plurality of different widths.

[0127] In yet other embodiments, the present disclosure relates to a method of forming multiple capacitors in an integrated device, the method comprising: forming a dielectric over a substrate; depositing a photoresist over an upper surface of the dielectric; patterning the photoresist to create a first opening and a second opening in the photoresist, the first opening having a first width and the second opening having a second width less than the first width; etching the dielectric using a single etch process to create a first trench directly beneath the first opening and a second trench directly beneath the second opening; and forming a first capacitor in the first trench and a second capacitor in the second trench, the first trench having a first depth and the second trench having a second depth less than the first depth.

[0128] In one embodiment, the method further includes: depositing a hard mask over the interlayer dielectric; and patterning the hard mask to create the first opening and the second opening in the hard mask, the first opening having the first width and the second opening having the second width. In one embodiment, in the method, the single etching process etches the first trench and the second trench. In one embodiment, the method further includes: forming a third opening having a third width when patterning the first mask layer; and forming a third trench during the single etching process, the third trench being directly below the third opening in the first mask layer, wherein the first capacitor is formed in the third trench in addition to the first trench. In one embodiment, in the method, the first trench extends through one or more etch stop layers in the interlayer dielectric, and the second trench does not extend through the one or more etch stop layers in the interlayer dielectric. In one embodiment, the method further includes: forming a first plurality of conductive lines within the interlayer dielectric before depositing the first mask layer; and forming a second plurality of conductive lines after forming the first and second capacitors, wherein a bottom electrode of the first and second capacitors is coupled to the first plurality of conductive lines, and a top electrode of the first and second capacitors is coupled to the second plurality of conductive lines. In one embodiment, the method further includes: forming a first plurality of vias after forming the first and second capacitors; and forming the first plurality of conductive lines, wherein the bottom electrode of the first and second capacitors is coupled to the first plurality of conductive lines via the first plurality of vias, and the top electrode of the first and second capacitors is coupled to the first plurality of conductive lines via the first plurality of vias. In one embodiment, forming the first and second capacitors further includes forming a first horizontal portion of the first capacitor and a second horizontal portion of the second capacitor, wherein the first horizontal portion has a first area and the second horizontal portion has a second area different from the first area.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated device comprising: substrate; An internal connection structure is disposed on the substrate, wherein the internal connection structure includes an interlayer dielectric; a first bottom electrode structure disposed in the interlayer dielectric, wherein the first bottom electrode structure has a first width measured between outer sidewalls of the first bottom electrode structure and has a first depth measured from a top surface of the interlayer dielectric; as well as a second bottom electrode structure disposed in the interlayer dielectric and spaced apart from the first bottom electrode structure, wherein the second bottom electrode structure has a second width measured between outer sidewalls of the second bottom electrode structure and has a second depth measured from the upper surface of the interlayer dielectric; The first width is greater than the second width, and the first depth is greater than the second depth.

2. The integrated device according to claim 1, further comprising: a third bottom electrode structure disposed in the interlayer dielectric and electrically coupled to the first bottom electrode structure by a metal line, wherein the third bottom electrode structure has a third width measured between outer sidewalls of the third bottom electrode structure and has a third depth measured from the upper surface of the interlayer dielectric; The third width is substantially equal to the first width, and the third depth is substantially equal to the first depth.

3. The integrated device according to claim 1, further comprising: A first through-hole is electrically coupled to the first bottom electrode structure and extends above the first bottom electrode structure.

4. The integrated device according to claim 1, further comprising: A first through-hole is electrically coupled to the first bottom electrode structure and extends below the first bottom electrode structure.

5. The integrated device according to claim 1, further comprising: A hard mask surrounds the outer sidewalls of the first bottom electrode structure.

6. An integrated device comprising: substrate; An internal connection structure is provided on the substrate; as well as A capacitor array is disposed in the interconnect structure and includes: a plurality of capacitors arranged in the interconnect structure, wherein the plurality of capacitors comprises a plurality of horizontal portions of a plurality of bottom electrodes arranged at a first height; and a plurality of bottom electrode structures of the plurality of capacitors extending from the plurality of horizontal portions of the plurality of bottom electrodes, the plurality of bottom electrode structures extending to a plurality of different depths measured from the first height, including a minimum depth and a maximum depth of the plurality of different depths, and having a plurality of different widths measured between outer sidewalls of the plurality of bottom electrode structures, including a minimum width and a maximum width of the plurality of different widths; wherein a first bottom electrode structure among the plurality of bottom electrode structures has the minimum depth and the minimum width, and wherein a plurality of bottom electrode structures among the plurality of bottom electrode structures having gradually increasing widths up to the maximum width have gradually increasing depths up to the maximum depth.

7. The integrated device of claim 6, wherein the plurality of capacitors further comprises a plurality of top electrodes extending into the plurality of bottom electrode structures.

8. The integrated device of claim 6, wherein the capacitor array further comprises a hard mask in contact with the plurality of horizontal portions of the plurality of capacitors and the plurality of bottom electrode structures.

9. The integrated device of claim 6, wherein a capacitor in the plurality of capacitors has a plurality of bottom electrode structures in the plurality of bottom electrode structures.

10. The integrated device of claim 6, wherein a first portion of the plurality of bottom electrode structures extends through one or more etch stop layers, and a second portion of the plurality of bottom electrode structures has bottom surfaces located above the one or more etch stop layers.

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