Semiconductor device

Abstract

The utility model discloses a semiconductor device. The semiconductor device comprises a substrate; the semiconductor epitaxial layer is positioned on one side of the substrate; wherein the semiconductor epitaxial layer is internally provided with a heterojunction of two-dimensional electron gas; the semiconductor epitaxial layer comprises a gate region and drift regions located on two opposite sides of the gate region; the gate structure is positioned on one side, far away from the substrate, of the semiconductor epitaxial layer and is positioned in the gate region of the semiconductor epitaxial layer; the strain layer is positioned in the drift region of the semiconductor epitaxial layer and the side wall of the gate structure; wherein at least one of the surface, close to one side of the substrate, of the strain layer, the interior of the strain layer and the surface, away from one side of the substrate, of the strain layer comprises a parasitic negative charge layer; the parasitic negative charge layer is used for supplementing electrons to the two-dimensional electron gas. According to the technical scheme provided by the utility model, the dynamic resistance value of the device is reduced, and the working efficiency of the device is improved.

Description

Technical Field

[0001] The embodiments of the utility model relate to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] Nitride-based semiconductor devices utilize a heterojunction interface between two materials with different band gaps to form a quantum well-like structure that accommodates a two-dimensional electron gas region, thereby meeting the requirements of high power / frequency devices.

[0003] Despite this, there are still some reliability issues that deserve attention. In related technologies, after forming a strain layer (Strain layer) above the gate structure, oxide is directly deposited to form a passivation layer; now the solution of adding a strain layer above the gate is generally adopted. The strain layer can repair the damage to the surface of the AlGaN layer after P-GaN etching, thereby reducing the surface defect state density of the AlGaN layer, reducing the dynamic on-resistance, and improving the conversion efficiency of the device; however, the effect of the stress layer on the surface repair of the AlGaN layer is not ideal, so that the device still has the problem of large dynamic on-resistance. Therefore, how to reduce the dynamic resistance value of the device and improve the working efficiency of the device has become a technical problem that needs to be solved urgently. Utility Model Content

[0004] The embodiment of the present utility model provides a semiconductor device to reduce the dynamic resistance value of the device and improve the working efficiency of the device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0006] substrate;

[0007] a semiconductor epitaxial layer located on one side of the substrate; wherein the semiconductor epitaxial layer has a heterojunction of a two-dimensional electron gas; the semiconductor epitaxial layer includes a gate region and drift regions located on opposite sides of the gate region;

[0008] a gate structure, located on a side of the semiconductor epitaxial layer away from the substrate and located in a gate region of the semiconductor epitaxial layer;

[0009] a strained layer, located in the drift region of the semiconductor epitaxial layer and on the sidewalls of the gate structure;

[0010] At least one of the surface of the strained layer close to the substrate, the interior of the strained layer, and the surface of the strained layer away from the substrate comprises a parasitic negative charge layer; the parasitic negative charge layer is used to supplement electrons to the two-dimensional electron gas.

[0011] Optionally, the parasitic negative charge layer includes a silicon doped layer;

[0012] The doping concentration of silicon in the silicon doping layer is in the range of 1×10 15 cm -3 ~5×10 19 cm -3 .

[0013] Optionally, the gate structure includes: a gate electrode and a P-type cap layer located between the gate electrode and the semiconductor epitaxial layer;

[0014] The strained layer located on the surface of the gate structure is located on the sidewall of the P-type cap layer and extends from the sidewall of the P-type cap layer to the bottom of the gate electrode.

[0015] Optionally, the strained layer located in the drift region contacts a surface of the semiconductor epitaxial layer on a side away from the substrate.

[0016] Optionally, the material of the strained layer includes AlN or Al2O3.

[0017] Optionally, the semiconductor device further includes:

[0018] a source electrode and a drain electrode; the source electrode and the drain electrode are located on opposite sides of the gate structure; the drift region is located between the source electrode and the gate structure, and between the drain electrode and the gate structure;

[0019] A passivation layer is located on a side of the strained layer away from the substrate and covers the strained layer, the gate electrode, the drain electrode and a surface of the gate structure not covered by the strained layer.

[0020] Optionally, the passivation layer includes:

[0021] a first passivation sublayer, located on a side of the strained layer away from the substrate, and covering a surface of the strained layer and a surface of the gate structure not covered by the strained layer;

[0022] a second passivation sublayer, located on a side of the first passivation sublayer away from the substrate, and covering a surface of the first passivation sublayer, a surface of the source electrode, and a surface of the drain electrode;

[0023] Among them, the second passivation sublayer includes a first opening, a second opening and a third opening, the first opening is provided with a first external electrode in contact with the gate structure, the second opening is provided with a second external electrode in contact with the source electrode, and the third opening is provided with a third external electrode in contact with the drain electrode.

[0024] Optionally, the thickness of the first passivation sublayer is less than the thickness of the second passivation sublayer;

[0025] The sum of the thickness of the first passivation sublayer and the thickness of the strained layer is smaller than the thickness of the source electrode and smaller than the thickness of the drain electrode.

[0026] Optionally, the first passivation sublayer located between the gate electrode and the drain electrode is in a “X” shape;

[0027] A surface of the second passivation sublayer away from the substrate is a flat surface.

[0028] Beneficial Effects: The present invention provides a semiconductor device comprising: a substrate; a semiconductor epitaxial layer located on one side of the substrate; wherein the semiconductor epitaxial layer comprises a heterojunction with a two-dimensional electron gas; the semiconductor epitaxial layer comprises a gate region and drift regions located on opposite sides of the gate region; a gate structure located on a side of the semiconductor epitaxial layer away from the substrate and located in the gate region of the semiconductor epitaxial layer; a strained layer located in the drift region of the semiconductor epitaxial layer and on the sidewalls of the gate structure; wherein at least one of the surface of the strained layer close to the substrate, the interior of the strained layer, and the surface of the strained layer away from the substrate comprises a parasitic negative charge layer. The technical solution provided by the present invention provides a parasitic negative charge layer to replenish electrons captured by surface defects of the semiconductor epitaxial layer and not yet released during the switching process of the device, thereby reducing the dynamic resistance of the device and improving the operating efficiency of the device.

[0029] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 This is a schematic structural diagram of a semiconductor device provided by an embodiment of the present utility model;

[0032] Figure 2 This is a schematic structural diagram of another semiconductor device provided by an embodiment of the present utility model;

[0033] Figure 3 This is a schematic structural diagram of another semiconductor device provided by an embodiment of the present utility model;

[0034] Figure 4This is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present utility model;

[0035] Figure 5 This is a structural schematic diagram corresponding to step S120 in a method for preparing a semiconductor device provided by an embodiment of the present utility model;

[0036] Figures 6 to 8 This is a structural schematic diagram corresponding to step S130 in a method for manufacturing a semiconductor device provided by an embodiment of the present utility model;

[0037] Figure 9 This is a structural schematic diagram corresponding to step S140 in a method for manufacturing a semiconductor device provided by an embodiment of the present utility model;

[0038] Figure 10 This is a structural schematic diagram corresponding to step S150 in a method for preparing a semiconductor device provided by an embodiment of the present utility model;

[0039] Figure 11 This is a structural schematic diagram corresponding to step S160 in a method for manufacturing a semiconductor device provided by an embodiment of the present utility model;

[0040] Figure 12 This is a structural schematic diagram corresponding to step S170 in a method for preparing a semiconductor device provided by an embodiment of the present utility model;

[0041] Figure 13 This is a structural schematic diagram corresponding to step S180 in a method for manufacturing a semiconductor device provided by an embodiment of the present utility model;

[0042] Figure 14 This is a structural schematic diagram corresponding to step S190 in a method for manufacturing a semiconductor device provided by an embodiment of the present utility model;

[0043] Figure 15 It is a structural schematic diagram corresponding to step S1100 in a method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to help those skilled in the art better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0046] The embodiment of the utility model provides a semiconductor device, Figure 1 This is a schematic structural diagram of a semiconductor device provided by an embodiment of the present utility model. Figure 2 This is a schematic structural diagram of another semiconductor device provided by an embodiment of the present utility model. Figure 3 This is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, referring to Figures 1 to 3 , semiconductor devices include:

[0047] substrate 10;

[0048] A semiconductor epitaxial layer 20 is located on one side of the substrate 10; wherein the semiconductor epitaxial layer 20 has a heterojunction of a two-dimensional electron gas; the semiconductor epitaxial layer 20 includes a gate region Q1 and drift regions Q2 located on opposite sides of the gate region Q1;

[0049] The gate structure 30 is located on a side of the semiconductor epitaxial layer 20 away from the substrate 10 and is located in the gate region Q1 of the semiconductor epitaxial layer 20 ;

[0050] The strained layer 40 is located on the drift region Q2 of the semiconductor epitaxial layer 20 and the sidewalls of the gate structure 30 ;

[0051] The strained layer 40 comprises a parasitic negative charge layer 401 on at least one of the surface of the strained layer 40 close to the substrate 10, the interior of the strained layer 40, and the surface of the strained layer 40 away from the substrate 10. The parasitic negative charge layer 401 is used to replenish electrons to the two-dimensional electron gas. Figure 1 The surface of the strained layer 40 away from the substrate 10 is shown as an example, including a layer of parasitic negative charges; Figure 2 The strained layer 40 is shown as an example, including a layer of parasitic negative charges inside; Figure 3 It is exemplarily shown that the surface of the strained layer 40 close to the substrate 10 includes a layer of parasitic negative charges.

[0052] Specifically, the substrate 10 may be a semiconductor substrate. The material of the substrate 10 may include, but is not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator (such as silicon on insulator (SOI)), or other suitable substrate 10 materials. In some embodiments, the substrate 10 may include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, the material of the substrate 10 may include, for example, but is not limited to, <111> Oriented silicon substrate.

[0053] In some embodiments, a buffer layer may be provided between the substrate 10 and the semiconductor epitaxial layer 20. The buffer layer may be in contact with the semiconductor epitaxial layer 20. The buffer layer is used to reduce the lattice and thermal mismatch between the substrate 10 and the semiconductor epitaxial layer 20, thereby resolving defects due to mismatch / difference. The buffer layer may comprise a III-V compound. The III-V compound may include, but is not limited to, aluminum, gallium, indium, nitrogen, or a combination thereof. Therefore, exemplary materials for the buffer layer may further include, for example, but are not limited to, GaN, AlN, AlGaN, InAlGaN, or a combination thereof. In some embodiments, a nucleation layer may be further included between the substrate 10 and the semiconductor epitaxial layer 20. The nucleation layer may be formed below the buffer layer. The nucleation layer is used to provide a transition to accommodate the mismatch / difference between the substrate 10 and the III-nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, but are not limited to, AlN.

[0054] The semiconductor epitaxial layer 20 includes a first nitride semiconductor layer 21 and a second nitride semiconductor layer 22. The first nitride semiconductor layer 21 is located on one side of the substrate 10, and the second nitride semiconductor layer 22 is located on the side of the first nitride semiconductor layer 21 away from the substrate 10 and has a band gap different from that of the first nitride semiconductor layer 21. A heterojunction with a two-dimensional electron gas is formed between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22. The material of the first nitride semiconductor layer 21 may include, but is not limited to, nitrides or III-V compounds, such as GaN, AlN, InN, InO, etc. x Al y Ga (1-x-y) N (where x+y≤1), Al y Ga (1-y) N (where y≤1). The material of the second nitride semiconductor layer 22 may include, but is not limited to, a III-V nitride semiconductor material, such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or a combination thereof. The band gap (i.e., bandgap) of the material of the first nitride semiconductor layer 21 and the band gap of the material of the second nitride semiconductor layer 22 are selected to be different so that the electron affinities of the two are different and a heterojunction is formed therebetween.

[0055] The band gap of the material of the first nitride semiconductor layer 21 is set to be smaller than the band gap of the material of the second nitride semiconductor layer 22. For example, the first nitride semiconductor layer 21 can be selected as a GaN layer with a band gap of approximately 3.4 eV, and the second nitride semiconductor layer 22 can be selected as an AlGaN layer with a band gap of approximately 4.0 eV. Thus, the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the junction interface between the channel layer and the barrier layer, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Therefore, the semiconductor device can include at least one GaN-based high resistance mobility transistor (HEMT). It should be noted that the formation of the 2DEG region is positively correlated with the degree of polarization effect between the channel and the barrier layer.

[0056] The gate structure 30 is arranged on the side of the semiconductor epitaxial layer 20 away from the substrate 10. The operation of the semiconductor device is controlled by the gate voltage applied to the gate structure 30. The gate voltage controls the on and off of the channel. The voltage applied between the source and the drain can drive the 2DEG to flow. The semiconductor device in the present invention can be a depletion-mode HEMT device (i.e., a D-mode depletion-mode HEMT) or an enhancement-mode HEMT device (i.e., an E-mode enhancement-mode HEMT). The D-mode depletion-mode HEMT allows the 2DEG channel to form naturally in the absence of a gate bias voltage, and is therefore usually in an on state (i.e., a normally-on state); the gate structure 30 of the E-mode enhancement-mode HEMT includes a P-type cap layer 31 and a gate electrode 32, and utilizes the holes in the P-type cap layer 31 to deplete the 2DEG in the channel below to achieve a normally-off state. Figures 1 to 3 The structures shown are all E-mode enhancement mode HEMTs.

[0057] To further increase the 2DEG concentration, a strain layer 40 can be added above the semiconductor epitaxial layer 20. Optionally, the strain layer 40 located in the drift region contacts the surface of the semiconductor epitaxial layer 20 away from the substrate 10. The material of the strain layer 40 may include AlN or Al2O3. The strain layer 40 modulates the stress state of the AlGaN / GaN heterojunction to reduce the on-resistance and increase the 2DEG concentration, thereby improving the saturation current density and device FOM (Factor of Merit) of the HEMT device. In addition, the strain layer 40 can also repair damage caused to the surface of the semiconductor epitaxial layer 20 (the surface of the barrier layer) by the patterning process of the gate structure 30, thereby reducing the defect state density on the surface of the semiconductor epitaxial layer 20, reducing the dynamic on-resistance, and improving the device conversion efficiency. However, the strain layer 40 is not ideal for repairing the surface of the semiconductor epitaxial layer 20, resulting in poor effectiveness of the strain layer 40 in reducing the dynamic on-resistance value.

[0058] After forming the strained layer 40, a parasitic negative charge layer 401 is formed on at least one of the surface of the strained layer 40 close to the substrate 10, the interior of the strained layer 40, and the surface of the strained layer 40 away from the substrate 10. The parasitic negative charge layer 401 is used to replenish electrons captured by surface defects in the semiconductor epitaxial layer 20 and not yet released during the device switching process, thereby further reducing the dynamic resistance of the device and improving its operating efficiency. The vertical projection of the parasitic negative charge layer 401 on the semiconductor epitaxial layer 20 can be located in the entire drift region Q2, in a portion of the drift region Q2, or in the entire drift region Q2 and a portion of the gate region Q1.

[0059] The semiconductor device provided by the present embodiment includes: a substrate 10; a semiconductor epitaxial layer 20 located on one side of the substrate 10; wherein the semiconductor epitaxial layer 20 has a heterojunction with a two-dimensional electron gas; the semiconductor epitaxial layer 20 includes a gate region Q1 and a drift region Q2 located on opposite sides of the gate region Q1; a gate structure 30 located on the side of the semiconductor epitaxial layer 20 away from the substrate 10 and located in the gate region Q1 of the semiconductor epitaxial layer 20; and a strained layer 40 located in the drift region Q2 of the semiconductor epitaxial layer 20 and on the sidewalls of the gate structure 30; wherein at least one of the surface of the strained layer 40 near the substrate 10, the interior of the strained layer 40, and the surface of the strained layer 40 away from the substrate 10 includes a parasitic negative charge layer 401. The technical solution provided by the present embodiment replenishes electrons captured by surface defects of the semiconductor epitaxial layer 20 but not yet released during the switching process of the device, thereby reducing the dynamic resistance of the device and improving the device's operating efficiency.

[0060] Based on the above embodiments, optionally, the parasitic negative charge layer 401 is formed by doping impurities at at least one of the surface of the strained layer 40 away from the substrate 10, the interior of the strained layer 40, and the surface of the strained layer 40 away from the substrate 10. The doped impurities include silicon, that is, the parasitic negative charge layer 401 includes a silicon-doped layer, and the doping concentration of silicon in the silicon-doped layer is in the range of 1×10 15 cm -3 ~5×10 19 cm -3 .

[0061] Specifically, after forming the strained layer 40, the strained layer 40 is subjected to a silicon-enrichment treatment. By controlling the depth of silicon impurity doping, a parasitic negative charge layer 401 is formed on at least one of the surface of the strained layer 40 close to the substrate 10, the interior of the strained layer 40, and the surface of the strained layer 40 away from the substrate 10. Silicon-enrichment treatments for the strained layer 40 include, but are not limited to, plasma treatment, thermal decomposition, and implantation diffusion. Silicon-enrichment treatments for the strained layer 40 may include bombarding the surface of the strained layer 40 with a silicon-containing plasma, thereby doping the strained layer 40 with silicon. Alternatively, silicon-enrichment treatments for the strained layer 40 may include decomposing silicon-containing materials through a thermal decomposition process, thereby forming a silicon-rich environment on the side of the strained layer 40 away from the substrate 10, causing silicon to adhere to and diffuse onto the surface of the strained layer 40, thereby doping the strained layer 40 with silicon. Alternatively, silicon-enrichment treatments for the strained layer 40 may include implanting silicon ions into the strained layer 40 using a silicon ion beam, thereby doping the strained layer 40 with silicon.

[0062] In the semiconductor device provided by the present invention, after Si-enriching the strained layer 40, oxide is deposited to form the passivation layer 50. This allows a layer of parasitic negative charge to form at least one of the following locations: the interface between the strained layer 40 and the passivation layer 50, within the strained layer 40, and at the interface between the strained layer 40 and the barrier layer. During the device switching process, this layer can replenish electrons trapped by surface defects in the barrier layer but not yet released, thereby reducing the dynamic resistance and improving device operating efficiency. This ensures that the strained layer 40 repairs the surface while further improving the device's dynamic characteristics.

[0063] In other embodiments of the present invention, the parasitic negative charge layer 401 is formed by doping germanium at least one of the surface of the strained layer 40 away from the substrate 10, the interior of the strained layer 40, and the surface of the strained layer 40 away from the substrate 10. The parasitic negative charge layer 401 includes a germanium doped layer; the doping concentration of germanium is in the range of 1×10 15 cm -3 ~5×10 19 cm -3 .

[0064] Based on the above embodiments, Figures 1 to 3 Optionally, the gate structure 30 includes: a gate electrode 32 and a P-type cap layer 31 located between the gate electrode 32 and the semiconductor epitaxial layer 20;

[0065] The strained layer 40 located on the surface of the gate structure 30 is located on the sidewall of the P-type cap layer 31 and extends from the sidewall of the P-type cap layer 31 to the bottom of the gate electrode 32 .

[0066] Specifically, the P-type cap layer 31 is disposed on and in contact with the semiconductor epitaxial layer 20. The P-type cap layer 31 is disposed between the semiconductor epitaxial layer 20 and the gate electrode 32. The gate electrode 32 is disposed on and in contact with the P-type cap layer 31. The P-type cap layer 31 may be a P-type doped III-V semiconductor layer. Exemplary materials of the P-type cap layer 31 may include P-doped III-V nitride semiconductor materials, such as p-type gallium nitride, p-type aluminum gallium nitride, p-type indium nitride, p-type aluminum indium nitride, p-type indium gallium nitride, p-type aluminum indium gallium nitride, or a combination thereof. In some embodiments, the P-type doped material is achieved by using P-type impurities such as beryllium (Be), zinc (Zn), cadmium (Cd), and magnesium (Mg). Exemplary materials of the gate electrode 32 may include metals or metal compounds. The gate electrode 32 may be formed as a single layer or multiple layers having the same or different compositions. Exemplary materials of the metal or metal compound may include, for example, but not limited to, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), metal alloys or compounds thereof, or other metal compounds.

[0067] Based on the above embodiments, please continue to refer to Figures 1 to 3 Optionally, the semiconductor device further comprises:

[0068] The source electrode S and the drain electrode D are located on opposite sides of the gate structure 30 ; the drift region Q2 is located between the source electrode S and the gate structure 30 , and between the drain electrode D and the gate structure 30 .

[0069] Specifically, the source electrode S is located on a side of the second nitride semiconductor layer 22 away from the substrate 10 and contacts the second nitride semiconductor layer 22. The drain electrode D is located on a side of the second nitride semiconductor layer 22 away from the substrate 10 and contacts the second nitride semiconductor layer 22. The source electrode S and the drain electrode D are located on opposite sides of the gate structure 30. The source electrode S and the drain electrode D may include but are not limited to metals, alloys, doped semiconductor materials (such as doped crystalline silicon), compounds such as silicides and nitrides, other conductive materials, or combinations thereof. The source electrode S and the drain electrode D may be a single layer, or multiple layers having the same or different compositions. In some embodiments, the source electrode S and the drain electrode D form an ohmic contact with the second nitride semiconductor layer 22. Ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the source electrode S and the drain electrode D.

[0070] Based on the above embodiments, please continue to refer to Figures 1 to 3 Optionally, the semiconductor device further includes: a passivation layer 50 located on a side of the strained layer 40 away from the substrate 10 and covering the strained layer 40, the gate electrode 32, the drain electrode D and the surface of the gate structure 30 not covered by the strained layer 40.

[0071] Specifically, the material of the passivation layer 50 includes a dielectric material such as oxide, for example, SiO2. The passivation layer 50 is used to protect and electrically insulate the semiconductor device. The passivation layer 50 may include a first passivation sublayer 51 and a second passivation sublayer 52; the first passivation sublayer 51 is located on the side of the strained layer 40 away from the substrate 10, and covers the surface of the strained layer 40 and the surface of the gate structure 30 not covered by the strained layer 40; the second passivation sublayer 52 is located on the side of the first passivation sublayer 51 away from the substrate 10, and covers the surface of the first passivation sublayer 51, the surface of the source electrode S, and the surface of the drain electrode D. The first passivation sublayer 51 is formed before the source electrode S and the drain electrode D are formed, and the second passivation sublayer 52 is formed after the source electrode S and the drain electrode D are formed. The material of the first passivation sublayer 51 and the material of the second passivation sublayer 52 may be the same or different. The first passivation sublayer 51 is used to protect the strained layer 40 and the gate electrode 32 when forming the source electrode S and the drain electrode D, and prevent metal materials from being formed on the surfaces of the gate electrode 32 and the strained layer 40 .

[0072] The formation of the second passivation sublayer 52 can increase the thickness of the passivation layer 50 located on the side of the strained layer 40 away from the substrate 10, thereby enhancing the protection provided by the passivation layer 50 to the semiconductor device and the reliability of the electrical insulation. In addition, the surface of the second passivation sublayer 52 on the side away from the substrate 10 is planar, which is used to achieve flattening of the surface of the semiconductor device. In addition, the second passivation sublayer 52 includes a first opening, a second opening, and a third opening. The first opening is provided with a first external lead electrode 61 in contact with the gate structure 30, the second opening is provided with a second external lead electrode 62 in contact with the source electrode S, and the third opening is provided with a third external lead electrode 63 in contact with the drain electrode D. The second passivation sublayer 52 is also used to achieve electrical isolation between the first external lead electrode 61 in contact with the gate structure 30, the second external lead electrode 62 in contact with the source electrode S, and the third external lead electrode 63 in contact with the drain electrode D. It should be noted that, since the first passivation sublayer 51 covers the top of the gate structure, the first passivation sublayer 51 includes a fourth opening penetrating the first opening. The first external electrode 61 contacts the gate electrode 31 through the first opening and the fourth opening in sequence.

[0073] Optionally, the thickness of the first passivation sublayer 51 is less than the thickness of the second passivation sublayer 52; the sum of the thickness of the first passivation sublayer 51 and the thickness of the strained layer 40 is less than the thickness of the source electrode S and less than the thickness of the drain electrode D. Setting the sum of the thickness of the first passivation sublayer 51 and the thickness of the strained layer 40 to be less than the thickness of the source electrode S and less than the thickness of the drain electrode D can reduce the thickness of etching the first passivation sublayer 51 and the strained layer 40, thereby reducing the difficulty of exposing the surface of the semiconductor epitaxial layer 20 in contact with the drain electrode D and the surface of the semiconductor epitaxial layer 20 free from the source electrode S.

[0074] Optionally, the first passivation sublayer 51 between the gate electrode S and the drain electrode D is in a “X” shape, and the surface of the second passivation sublayer 52 away from the substrate 10 is a flat surface.

[0075] Specifically, the thickness of the first passivation sublayer 51 is sufficient to protect the strained layer 40 and the gate electrode 32 during the formation of the source electrode S and the drain electrode D, and to prevent metal material from forming on the surfaces of the gate electrode 32 and the strained layer 40. Therefore, the thickness of the first passivation sublayer 51 can be set relatively thin, and the formed first passivation sublayer 51 is arranged along the outer contours of the gate structure and the surface of the semiconductor epitaxial layer, thereby reducing the time required to prepare the first passivation sublayer 51. The thickness of the second passivation sublayer 52 is set relatively thick to protect the device. The surface of the second passivation sublayer 52 away from the substrate 10 is set to a flat surface, which allows the first external lead electrode 61, the second external lead electrode 62, and the third external lead electrode 63 to be drawn out from the same horizontal plane height, facilitating subsequent electrical connection.

[0076] The present invention also provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device described in any of the above embodiments. Figure 4 This is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Figure 4 , a method for preparing a semiconductor device includes:

[0077] S110 , providing a substrate.

[0078] Specifically, the substrate 10 may be a semiconductor substrate 10. The material of the substrate 10 may include, but is not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator (such as silicon on insulator (SOI)), or other suitable substrate 10 materials. In some embodiments, the substrate 10 may include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, the material of the substrate 10 may include, for example, but is not limited to, <111> Oriented silicon substrate.

[0079] S120, forming a semiconductor epitaxial layer on one side of the substrate; wherein the semiconductor epitaxial layer has a heterojunction of a two-dimensional electron gas; the semiconductor epitaxial layer includes a gate region and drift regions located on opposite sides of the gate region.

[0080] Specifically, participate Figure 5 , forming a semiconductor epitaxial layer 20 on one side of the substrate 10 includes: sequentially forming a first nitride semiconductor layer 21 and a second nitride semiconductor layer 22 on one side of the substrate 10. The second nitride semiconductor layer 22 has a band gap different from that of the first nitride semiconductor layer 21, so that a two-dimensional electron gas heterojunction can be formed between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22. The material of the first nitride semiconductor layer 21 may include, but is not limited to, nitrides or III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1-x-y) N (where x+y≤1), Al y Ga (1-y) N (where y≤1). The material of the second nitride semiconductor layer 22 may include, but is not limited to, a III-V nitride semiconductor material, such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or a combination thereof.

[0081] Optionally, before forming the semiconductor epitaxial layer 20 on one side of the substrate 10, the process further includes forming a buffer layer on one side of the substrate 10. The buffer layer is located between the substrate 10 and the semiconductor epitaxial layer 20 and may be in contact with the semiconductor epitaxial layer 20. The buffer layer is used to reduce the lattice and thermal mismatch between the substrate 10 and the semiconductor epitaxial layer 20, thereby resolving defects due to mismatch / difference. The buffer layer may comprise a III-V compound. The III-V compound may include, but is not limited to, aluminum, gallium, indium, nitrogen, or a combination thereof. Therefore, exemplary materials for the buffer layer may further include, for example, but are not limited to, GaN, AlN, AlGaN, InAlGaN, or a combination thereof. Furthermore, in some embodiments, before forming the buffer layer on one side of the substrate 10, the process further includes forming a nucleation layer on one side of the substrate 10. The nucleation layer is used to provide a transition to accommodate the mismatch / difference between the substrate 10 and the III-nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, but are not limited to, AlN or any alloy thereof.

[0082] S130 , forming a gate structure on a side of the semiconductor epitaxial layer away from the substrate; the gate structure is located in a gate region of the semiconductor epitaxial layer.

[0083] Specifically, the semiconductor device can be a depletion-mode HEMT device (i.e., a D-mode depletion-mode HEMT) or an enhancement-mode HEMT device (i.e., an E-mode enhancement-mode HEMT). The D-mode depletion-mode HEMT allows a 2DEG channel to form naturally in the absence of a gate bias voltage, and is therefore usually in an on state (i.e., a normally-on state). The gate structure 30 of the E-mode enhancement-mode HEMT includes a P-type cap layer and a gate electrode, and utilizes holes in the P-type cap layer to deplete the 2DEG in the underlying channel, thereby achieving a normally-off state.

[0084] refer to Figures 6 to 8 If the gate structure 30 includes a gate electrode 32 and a P-type cap layer 31 located between the gate electrode 32 and the semiconductor epitaxial layer 20, then forming the gate structure 30 on the side of the semiconductor epitaxial layer 20 away from the substrate 10 includes: sequentially forming a P-type cap material layer 301 and a gate electrode material layer 302 on the side of the semiconductor epitaxial layer 20 away from the substrate 10; and sequentially patterning the electrode material layer 302 and the P-type cap material layer 302 to form the gate electrode 32 and the P-type cap layer 31. The electrode material layer 302 and the P-type cap material layer 302 can be patterned using an etching process. The width of the P-type cap layer 31 can be greater than or equal to the width of the gate electrode 32.

[0085] S140 , forming a strained layer on the sidewalls of the gate structure and the surface of the semiconductor epitaxial layer not covered by the gate structure.

[0086] Specifically, refer to Figure 9, AlN material or Al 2 O 3 material is deposited on the sidewalls of the gate structure 30 and the surface of the semiconductor epitaxial layer 20 not covered by the gate structure 30 to form a strained layer 40 .

[0087] S150, forming a parasitic negative charge layer on at least one of a surface of the strained layer close to the substrate, an interior of the strained layer, and a surface of the strained layer away from the substrate; wherein the parasitic negative charge layer is used to compensate electrons for the two-dimensional electron gas.

[0088] Specifically, refer to Figure 10 After forming the strained layer 40, the strained layer 40 is subjected to a silicon-enrichment treatment. By controlling the depth of silicon impurity doping, a parasitic negative charge layer 401 is formed on at least one of the surface of the strained layer 40 close to the substrate 10, the interior of the strained layer 40, and the surface of the strained layer 40 away from the substrate 10. The silicon-enrichment treatment of the strained layer 40 includes, but is not limited to, plasma, thermal decomposition, and implantation diffusion. The silicon-enrichment treatment of the strained layer 40 can be performed by bombarding the surface of the strained layer 40 with a silicon-containing plasma, thereby doping silicon in the strained layer 40. Alternatively, the silicon-enrichment treatment of the strained layer 40 can be performed by decomposing the silicon-containing material through a thermal decomposition process, forming a silicon-rich environment on the side of the strained layer 40 away from the substrate 10, causing silicon to adhere to the surface of the strained layer 40 and diffuse, thereby doping silicon in the strained layer 40. Alternatively, the silicon-enrichment treatment of the strained layer 40 can be performed by implanting a silicon ion beam into the strained layer 40, thereby doping silicon in the strained layer 40.

[0089] The semiconductor device fabrication method provided by the present invention utilizes a silicon-enriched treatment on the strained layer 40 after forming it. This creates a layer of parasitic negative charge at the interface between the strained layer 40 and the adjacent film layer and at least one location within the strained layer 40. During the device switching process, this layer replenishes electrons trapped by surface defects that have yet to be released, thereby reducing dynamic resistance and improving device operating efficiency. This ensures that the strained layer 40 repairs the surface of the semiconductor epitaxial layer 20 while further improving the device's dynamic characteristics.

[0090] Optionally, the semiconductor device further includes:

[0091] A source electrode and a drain electrode; the source electrode and the drain electrode are located on opposite sides of the gate structure; the drift region is located between the source electrode and the gate structure, and between the drain electrode and the gate structure;

[0092] The passivation layer is located on a side of the strained layer away from the substrate and covers the strained layer, the gate electrode, the drain electrode and the surface of the gate structure not covered by the strained layer.

[0093] The passivation layer includes: a first passivation sublayer, located on the side of the strained layer away from the substrate, covering the surface of the strained layer and the surface of the gate structure not covered by the strained layer; a second passivation sublayer, located on the side of the first passivation sublayer away from the substrate, covering the surface of the first passivation sublayer, the surface of the source electrode, and the surface of the drain electrode. The second passivation sublayer includes a first opening, a second opening, and a third opening. The first opening is provided with a first external lead electrode in contact with the gate structure, the second opening is provided with a second external lead electrode in contact with the source electrode, and the third opening is provided with a third external lead electrode in contact with the drain electrode.

[0094] After forming the parasitic negative charge layer, it also includes:

[0095] S160 , forming a first passivation sublayer on a side of the strained layer away from the substrate; wherein the first passivation sublayer covers a surface of the strained layer and a surface of the gate structure not covered by the strained layer.

[0096] Specifically, refer to Figure 11 An oxide material is deposited on the side of the strained layer 40 away from the substrate 10 to form a first passivation sublayer 51. The first passivation sublayer 51 covers the surface of the strained layer 40 and the surface of the gate structure 30 not covered by the strained layer 40.

[0097] S170 , removing the first passivation sublayer and the strained layer at the preset position of the source electrode, and removing the first passivation sublayer and the strained layer at the preset position of the drain electrode.

[0098] Specifically, refer to Figure 12 The first passivation sublayer 51 and the strained layer 40 at the predetermined location of the source electrode are removed to expose the source electrode region in the surface of the semiconductor epitaxial layer 20. The first passivation sublayer 51 and the strained layer 40 at the predetermined location of the drain electrode are removed to expose the drain electrode region in the surface of the semiconductor epitaxial layer 20.

[0099] S180. Form a source electrode at a preset position of the source electrode, and form a drain electrode at a preset position of the drain electrode; wherein the source electrode and the drain electrode are located on opposite sides of the gate structure; and the drift region is located between the source electrode and the gate structure, and between the drain electrode and the gate structure 3.

[0100] Specifically, refer to Figure 13 , forming a source electrode S at a predetermined location of the source electrode S, and forming a drain electrode D at a predetermined location of the drain electrode D. The source electrode S and the drain electrode D may include, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon, silicide, and nitride compounds), other conductive materials, or combinations thereof. The source electrode S and the drain electrode D may be a single layer, or multiple layers having the same or different compositions.

[0101] S190, forming a second passivation sublayer on a side of the first passivation sublayer away from the substrate; wherein the second passivation sublayer covers a surface of the first passivation sublayer, a surface of the source electrode, and a surface of the drain electrode.

[0102] refer to Figure 14 An oxide material is deposited on a side of the first passivation sublayer 51 away from the substrate 10 to form a second passivation sublayer 52. The material of the first passivation sublayer 51 and the material of the second passivation sublayer 52 may be the same or different.

[0103] S1100. A first opening, a second opening, and a third opening are formed in the second passivation sublayer, and a first external electrode in contact with the gate structure is formed in the first opening, a second external electrode 62 in contact with the source electrode S is formed in the second opening, and a third external electrode 63 in contact with the drain electrode D is formed in the third opening.

[0104] Specifically, refer to Figure 15 , the second passivation sublayer 52 is etched to form a first opening 01, a second opening 02 and a third opening 03 in the second passivation sublayer 52. Figure 1 A first external lead electrode 61 in contact with the gate structure 30 is formed in the first opening 01, a second external lead electrode 62 in contact with the source electrode S is formed in the second opening 02, and a third external lead electrode 63 in contact with the drain electrode D is formed in the third opening 03. It should be noted that since the first passivation sublayer 51 covers the top of the gate structure, the first passivation sublayer 51 can be further etched after the first opening 01 is formed, forming a fourth opening in the first passivation sublayer 51 that passes through the first opening 01. The first external lead electrode 61 contacts the gate electrode 31 through the first opening 01 and the fourth opening in sequence.

[0105] Note that the above are merely preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions are possible for those skilled in the art without departing from the scope of protection of the present invention. Therefore, while the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a semiconductor epitaxial layer located on one side of the substrate; wherein the semiconductor epitaxial layer has a heterojunction of a two-dimensional electron gas; the semiconductor epitaxial layer includes a gate region and drift regions located on opposite sides of the gate region; a gate structure, located on a side of the semiconductor epitaxial layer away from the substrate and located in a gate region of the semiconductor epitaxial layer; a strained layer, located in the drift region of the semiconductor epitaxial layer and on the sidewalls of the gate structure; At least one of the surface of the strained layer close to the substrate, the interior of the strained layer, and the surface of the strained layer away from the substrate comprises a parasitic negative charge layer; the parasitic negative charge layer is used to supplement electrons to the two-dimensional electron gas.

2. The semiconductor device according to claim 1, wherein The parasitic negative charge layer includes a silicon doped layer; The doping concentration of silicon in the silicon doping layer is in the range of 1×10 15 cm -3 ~5×10 19 cm -3 .

3. The semiconductor device according to claim 1, wherein The parasitic negative charge layer includes a germanium doped layer; The doping concentration of germanium in the germanium doped layer is in the range of 1×10 15 cm -3 ~5×10 19 cm -3 .

4. The semiconductor device according to claim 1, wherein The gate structure includes: a gate electrode and a P-type cap layer located between the gate electrode and the semiconductor epitaxial layer; The strained layer located on the surface of the gate structure is located on the sidewall of the P-type cap layer and extends from the sidewall of the P-type cap layer to the bottom of the gate electrode.

5. The semiconductor device according to claim 4, wherein The strained layer located in the drift region contacts a surface of the semiconductor epitaxial layer away from the substrate; The material of the strained layer includes AlN or Al2O3. The semiconductor device according to claim 1 , wherein: Also includes: A source electrode and a drain electrode; the source electrode and the drain electrode are located on opposite sides of the gate structure; The drift region is located between the source electrode and the gate structure, and between the drain electrode and the gate structure.

7. The semiconductor device according to claim 6, wherein: Also includes: A passivation layer is located on a side of the strained layer away from the substrate and covers the strained layer, the gate electrode, the drain electrode and a surface of the gate structure not covered by the strained layer.

8. The semiconductor device according to claim 7, wherein: The passivation layer comprises: a first passivation sublayer, located on a side of the strained layer away from the substrate, and covering a surface of the strained layer and a surface of the gate structure not covered by the strained layer; a second passivation sublayer, located on a side of the first passivation sublayer away from the substrate, and covering a surface of the first passivation sublayer, a surface of the source electrode, and a surface of the drain electrode; Among them, the second passivation sublayer includes a first opening, a second opening and a third opening, the first opening is provided with a first external electrode in contact with the gate structure, the second opening is provided with a second external electrode in contact with the source electrode, and the third opening is provided with a third external electrode in contact with the drain electrode.

9. The semiconductor device according to claim 8, wherein The thickness of the first passivation sublayer is less than the thickness of the second passivation sublayer; The sum of the thickness of the first passivation sublayer and the thickness of the strained layer is smaller than the thickness of the source electrode and smaller than the thickness of the drain electrode.

10. The semiconductor device according to claim 9, wherein The first passivation sublayer located between the gate electrode and the drain electrode is in a "X" shape; A surface of the second passivation sublayer away from the substrate is a flat surface.

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