Semiconductor device structure

Abstract

A semiconductor device structure includes a first region including a gate electrode disposed over a semiconductor fin, a second region, and a boundary region disposed between the first region and the second region. The boundary region includes a metal-insulator-metal (MIM) structure, and the MIM structure includes a first conductive layer disposed over the semiconductor fin, a first dielectric layer in contact with the first conductive layer, and a second conductive layer in contact with the first dielectric layer. A top surface of the second conductive layer may be substantially coplanar with a top surface of the gate electrode.

Description

Technical Field

[0001] The present disclosure relates to semiconductor device structures. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density is due to repeated reductions in minimum feature size, which allows more components to be integrated into a given area. However, this reduction also increases the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies. Utility Model Content

[0003] In some embodiments disclosed herein, a semiconductor device structure includes: a first region including a gate electrode disposed above a semiconductor fin; a second region; and a boundary region disposed between the first region and the second region, wherein the boundary region includes a metal-insulator-metal structure, and the metal-insulator-metal structure includes: a first conductive layer disposed above the semiconductor fin; a first dielectric layer contacting the first conductive layer; and a second conductive layer contacting the first dielectric layer, wherein a top surface of the second conductive layer is coplanar with a top surface of the gate electrode.

[0004] In some embodiments disclosed herein, a semiconductor device structure includes: a first region including a gate electrode; a second region; and a boundary region disposed between the first region and the second region, wherein the boundary region includes a metal-insulator-metal structure, and the metal-insulator-metal structure includes: a first conductive layer; a first dielectric layer contacting the first conductive layer; and a second conductive layer contacting the first dielectric layer, wherein a top surface of the second conductive layer is coplanar with a top surface of the first conductive layer.

[0005] In some embodiments disclosed herein, a semiconductor device structure includes: a first region including a gate electrode; a second region; and a boundary region disposed between the first region and the second region, wherein the boundary region includes a metal-insulator-metal structure, and the metal-insulator-metal structure includes: a first conductive layer; a first dielectric layer in contact with the first conductive layer; and a second conductive layer in contact with the first dielectric layer; and a dielectric region disposed on the first conductive layer and surrounding multiple vertical sides of the second conductive layer, wherein a top surface of the second conductive layer is coplanar with a top surface of the first conductive layer, and a top surface of the dielectric region is coplanar with the top surface of the second conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A to 1C 、 Figures 2A to 2B 、 Figures 3A to 3B 、 Figures 4A to 4B 、 Figures 5A to 5B and Figures 6A to 6B are various views of respective intermediate structures at intermediate stages in an example process of forming a semiconductor device structure according to some embodiments;

[0008] 7A to 7B is an example process for forming a semiconductor device structure according to some embodiments Figure 6A and Figure 6B Various views of the respective intermediate structures of the intermediate stages;

[0009] Figure 8 and Figure 9 is a cross-sectional view of an intermediate structure at an intermediate stage in an example process of forming a semiconductor device structure according to some embodiments;

[0010] FIG. 10A to FIG. 10B According to some embodiments Figure 9 Various views of the metal-insulator-metal (MIM) structure;

[0011] Figures 11A to 11B According to an alternative embodiment Figure 9 Various views of the MIM structure;

[0012] FIG. 12A to FIG. 12B According to an alternative embodiment Figure 9 Various views of the MIM structure;

[0013] 13A to 13C According to some embodiments FIG. 12A to FIG. 12B A cross-sectional side view of an intermediate structure of a MIM structure;

[0014] 14A to 14C are various views of MIM structures according to some embodiments;

[0015] 15A to 15D 、 16A to 16B 、 17A to 17B 、 18A to 18B and Figures 19A to 19B According to some embodiments, the formation includes 14A to 14C Various views of respective intermediate structures at intermediate stages in an example process of a semiconductor device structure having a MIM structure;

[0016] FIG. 20A to FIG. 20B According to an alternative embodiment Figures 11A to 11B MIM structure or Figures 19A to 19B A top view of the MIM structure;

[0017] Figures 21A to 21C is a cross-sectional view of an intermediate structure at an intermediate stage in an example process of forming a semiconductor device structure according to some embodiments;

[0018] Figures 22A to 22C is a cross-sectional view of an intermediate structure at an intermediate stage in an example process of forming a semiconductor device structure according to some embodiments;

[0019] FIG. 23A to FIG. 23B are various views of MIM structures according to alternative embodiments.

[0020]

Explanation of symbols

[0021] 40:Semiconductor device structure

[0022] 52a-52f, 92: source / drain regions

[0023] 70, 302: semiconductor substrate

[0024] 74: Fins

[0025] 78: Quarantine

[0026] 80, 112, 212, 306, 312: dielectric layer

[0027] 82: Gate layer

[0028] 84:Mask

[0029] 86: Gate spacer layer

[0030] 88: Gate spacer layer

[0031] 96:CESL

[0032] 100: First ILD

[0033] 102-1: IP Block

[0034] 102-2: IP Block

[0035] 104: Border Area

[0036] 106, 201: Opening

[0037] 108, 208, 308: MIM structure

[0038] 110, 202, 304: conductive layer

[0039] 110S: Side surface

[0040] 114, 210, 310: conductive layer

[0041] 116: Conductive contact

[0042] 120: conformal layer

[0043] 122: Gate electrode

[0044] 130: Second ILD

[0045] 134: Conductive characteristics

[0046] 136: Silicide region

[0047] 140, 204: Dielectric materials

[0048] 214, 314: conductive layer

[0049] AA, BB, CC, DD: cross section

[0050] L: Length

[0051] S: distance

[0052] W: width DETAILED DESCRIPTION

[0053] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The specific examples of components and configurations described below are intended to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0054] Additionally, for ease of description, spatially relative terms such as "below," "lower," "above," "over," "on," "top," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0055] Figures 1A to 22B FIG. 4 shows a process for manufacturing a semiconductor device structure 40 according to an embodiment of the present disclosure. It should be understood that Figures 1A to 22B Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the methods. The order of the operations / processes is not limiting and may be interchanged.

[0056] Figure 1A 、 Figure 1B and Figure 1C Different views of intermediate structures illustrating stages in an example process of forming a semiconductor device structure 40 in accordance with some embodiments. Figure 1A and Figure 1B are different cross-sectional views of the intermediate structure, and Figure 1C It is a perspective view of the intermediate structure.

[0057] like Figures 1A to 1C As shown in FIG, fins 74 are formed from a semiconductor substrate 70. Fins 74 are semiconductor fins. Isolation regions 78 are disposed on semiconductor substrate 70 and between adjacent fins 74. Each fin 74 protrudes above and from between adjacent isolation regions 78. Sacrificial gate stacks (or more generally, sacrificial gate structures), each including a dielectric layer 80, a sacrificial gate layer 82, and a mask 84, are formed along the sidewalls of fins 74 and above the top surface of fins 74. Source / drain regions 52a-f are located in respective regions of fins 74.

[0058] Figure 1C The reference cross sections used in the other figures are further described. Cross section AA is in a plane along fin 74. Cross section BB is in a plane perpendicular to cross section AA and spans source / drain regions 52a and 52d adjacent to fin 74. For clarity, the various figures refer to these reference cross sections. Figures 1A to 6B The figures ending with "A" in the figure illustrate cross-sectional views corresponding to various treatment cases of cross-sectional view AA, while Figures 1A to 6B The figures ending with a "B" mark in FIG. 1 illustrate cross-sectional views of various processing cases corresponding to cross-section BB.

[0059] The semiconductor substrate 70 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, and may be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate may include an elemental semiconductor such as silicon (Si) or germanium (Ge); a compound semiconductor; an alloy semiconductor; or a combination thereof.

[0060] Fins 74 may be formed from semiconductor substrate 70, such as by etching trenches between fins 74. Isolation regions 78 may be formed in the trenches between fins 74. Isolation regions 78 may include or be an insulating material such as an oxide (e.g., silicon oxide), a nitride, the like, or a combination thereof. Fins 74 protrude between adjacent isolation regions 78, thereby at least partially identifying fins 74 as active regions on semiconductor substrate 70. Fins 74 and isolation regions 78 may be formed by any acceptable process and may include any acceptable material. In some examples, fins 74 may include heteroepitaxial structures (e.g., a material that is lattice mismatched to the semiconductor material of semiconductor substrate 70) or other structures.

[0061] The sacrificial gate stacks are formed above the fins 74 and extend laterally perpendicular to the fins 74. Each sacrificial gate stack includes a dielectric layer 80, a sacrificial gate layer 82, and a mask 84. The dielectric layer 80 may include or be silicon oxide, silicon nitride, the like, or multiple layers thereof. The sacrificial gate layer 82 may include or be silicon (e.g., polysilicon) or another material. The mask 84 may include or be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof. The layers for the mask 84, the sacrificial gate layer 82, and the dielectric layer 80 may be deposited and patterned into the sacrificial gate stacks using any acceptable process to form the mask 84, sacrificial gate layer 82, and dielectric layer 80 for each sacrificial gate stack.

[0062] Figure 2A and Figure 2B A first gate spacer layer 86 is shown formed along the sidewalls and top surfaces of the sacrificial gate stack and fin 74. The first gate spacer layer 86 is conformally deposited along the sidewalls and top surfaces of the fin 74 and sacrificial gate stack (e.g., along the sidewalls of the dielectric layer 80, sacrificial gate layer 82, and mask 84, and on the top surface of mask 84), as well as on the top surface of the isolation region 78. The first gate spacer layer 86 may be or include silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), or another material. In some examples, the first gate spacer layer 86 may be deposited using an atomic layer deposition (ALD) process, although other deposition techniques may be used. In some embodiments, the first gate spacer layer 86 may be omitted.

[0063] Figure 3A and Figure 3B The formation of the second gate spacer layer 88 is described. The second gate spacer layer 88 is conformally deposited on the first gate spacer layer 86. The second gate spacer layer 88 is a dielectric layer comprising silicon, oxygen, nitrogen, and carbon. In some embodiments, the second gate spacer layer 88 may be or include silicon oxycarbonitride (SiOCN). The second gate spacer layer 88 may be deposited using an ALD process.

[0064] Figure 4A and Figure 4B The formation of a gate spacer including respective portions of a first gate spacer layer 86 and a second gate spacer layer 88 is illustrated. Gate spacers are formed along the sidewalls of the gate stack (e.g., the sidewalls of the dielectric layer 80, the sacrificial gate layer 82, and the mask 84) and above the fin 74 (e.g., a double-layer gate spacer as illustrated). For example, depending on the height of the fin 74 above the isolation region 78, residual gate spacers may also remain along the sidewalls of the fin 74. The gate spacers may be formed by anisotropically etching the second gate spacer layer 88 and the first gate spacer layer 86. The etching process may include RIE, NBE, or another etching process. In other embodiments, the multi-layer gate spacer may include additional and / or different layers and / or materials.

[0065] Figure 5A and Figure 5B The formation of the source / drain region 92 is illustrated. Recesses are formed in the fin 74 on the opposite side of the sacrificial gate stack, and the source / drain region 92 is formed in the recesses. The recesses can be achieved by an etching process. The etching process can be isotropic or anisotropic, or in addition, can be selective with respect to one or more crystallographic planes of the semiconductor substrate 70. Figure 5A and Figure 5B As shown in FIG, epitaxial source / drain regions 92 may be formed in the recesses. Epitaxial source / drain regions 92 may include or be silicon germanium, silicon carbide, silicon phosphorus, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. Epitaxial source / drain regions 92 may be formed in the recesses by epitaxially growing a material in the recesses, such as by metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. Epitaxial source / drain regions 92 may extend beyond the sidewalls and top surface of fin 74 (e.g., a protrusion) and may have facets that may correspond to crystallographic planes of semiconductor substrate 70. In some examples, different materials are used for the epitaxial source / drain regions 92 for p-type and n-type devices. Proper masking during recess or epitaxial growth can allow different materials to be used in different devices. In this disclosure, the terms source and drain regions are used interchangeably, and their structures are substantially the same. Furthermore, the source / drain regions may be referred to as either source or drain, individually or collectively, depending on the context.

[0066] like Figure 6Aand Figure 6B As shown in FIG, after forming source / drain regions 92, a contact etch stop layer (CESL) 96 is conformally deposited on the surfaces of epitaxial source / drain regions 92, the sidewalls and top surfaces of the multi-layer gate spacers, the top surface of mask 84, and the top surface of isolation region 78 by any acceptable process. Generally speaking, an etch stop layer can provide a mechanism to stop the etching process when forming, for example, a contact or via. The etch stop layer can be formed of a dielectric material having a different etch selectivity than adjacent layers or components. CESL 96 can include silicon nitride, silicon carbonitride, the like, or a combination thereof.

[0067] A first interlayer dielectric (ILD) 100 may be formed over the CESL 96. The first ILD 100 may include or may be silicon dioxide, a low-k dielectric material (such as silicon oxynitride), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glass (OSG), SiO x C y , spin-on glass, spin-on polymer, silicon carbide material, compounds thereof, composites thereof, the like, or combinations thereof. The first ILD 100 may be deposited by any acceptable process.

[0068] The first ILD 100 and the CESL 96 are formed with top surfaces that are coplanar with the top surface of the sacrificial gate layer 82. A planarization process such as chemical mechanical polishing (CMP) may be performed to make the top surfaces of the first ILD 100 and the CESL 96 flush with the top surface of the sacrificial gate layer 82. The CMP may also remove the mask 84 on the sacrificial gate layer 82 (and in some cases, remove the upper portion of the multi-layer gate spacer). Thus, the top surface of the sacrificial gate layer 82 is exposed through the first ILD 100 and the CESL 96, as shown in FIG. Figure 6A and Figure 6B. In some embodiments, after the CMP process, the first ILD 100 may be recessed and a dielectric material (not shown) may be formed on the first ILD 100. The dielectric material may be a nitride, such as silicon nitride. Another planarization process may be performed so that the top surface of the dielectric material and the top surface of the sacrificial gate layer 82 are substantially coplanar. The dielectric material may protect the first ILD 100 during subsequent processes.

[0069] 7A to 7B is an example process for forming semiconductor device structure 40 according to some embodiments. Figure 6A and Figure 6B Cross-sectional views of the intermediate structures of the intermediate stages. Figure 7A As shown in , the semiconductor device structure 40 includes a first IP block 102-1 and a second IP block 102-2. An IP block is a reusable unit of logic, cell, or IC layout design, which is the intellectual property of one party or one supplier. IC designers can use these IP blocks as building blocks. The first IP block 102-1 is a reusable unit of logic, cell, or IC layout design; the second IP block 102-2 is another reusable unit of logic, cell, or IC layout design. In one example, the first IP block 102-1 is a static random access memory (SRAM) IP block, and the second IP block 102-2 is another SRAM IP block. The density of the gate structures (or sacrificial gate structures) in these SRAM IP blocks is relatively high. It should be understood that Figure 7A The example shown in is illustrative and not limiting, and in other embodiments, the semiconductor device structure 40 may include more than two IP blocks.

[0070] like Figure 7A As shown in , the boundary region 104 is located between the first IP block 102-1 and the second IP block 102-2 in a first horizontal direction (i.e., the X direction). In some embodiments, the fin 74 extends continuously from the first IP block 102-1 through the boundary region 104 and extends into the second IP block 102-2. In some embodiments, the continuous fin 74 can be patterned to form discrete fins 74 in the first IP block 102-1, the boundary region 104, and the second IP block 102-2. Regardless of whether the fin 74 is continuous or discrete, the fins 74 in the first IP block 102-1 and the second IP block 102-2 can be the same fins 74 in the boundary region 104 because the first IP block 102-1 and the second IP block 102-2 and the fins 74 in the boundary region 104 are formed at the same time. Figure 7B (It is Figure 7AAs shown in FIG. 4 (a top view of the semiconductor device structure 40), the boundary region 104 has a width in a first horizontal direction (i.e., the X direction) and a length in a second horizontal direction (i.e., the Y direction). In one example, the width of the boundary region 104 is between 0.1 μm and 3.0 μm. The density of gate structures (or sacrificial gate structures) in the boundary region 104 is relatively low compared to the density of gate structures in the IP block. Figure 7A The density of the sacrificial gate layer 82 representing the sacrificial gate structure in the IP blocks 102-1 and 102-2 is greater than the density of the sacrificial gate layer 82 in the boundary region 104. Figure 7A Gate spacer layers 86 and 88, dielectric layer 80, fin 74, and semiconductor substrate 70 are omitted. In some embodiments, during a replacement gate (RPG) process, CMP dishing can cause under-polishing defects in an integrated circuit (IC) having two or more IP blocks and a boundary region therebetween. For example, a metal gate replacing a sacrificial gate layer in an IP block adjacent to the boundary region can have a substantially smaller height than a metal gate located in the center of the IP block.

[0071] It should be understood that the range of 0.1 μm to 3.0 μm is not arbitrarily selected. For boundary regions wider or longer than 3.0 μm, large dummy patterns (including large or spacious sacrificial gate layer patterns and large or spacious dummy fin patterns) have been employed. It should be understood that the embodiments disclosed herein can replace large dummy patterns in boundary regions wider or longer than 3.0 μm. For boundary regions narrower or shorter than 0.1 μm, the CMP dishing effect is not severe enough to cause problematic underpolishing effects because the boundary region is not large enough.

[0072] Figure 8 and Figure 9 is a cross-sectional view of an intermediate structure at an intermediate stage in an example process for forming a semiconductor device structure 40 according to some embodiments. Figure 8 As shown in , a mask layer (not shown) is formed in the first IP block 102-1 and the second IP block 102-2 to protect the materials in the first IP block 102-1 and the second IP block 102-2, and the sacrificial gate layer 82 exposed in the boundary area 104 is removed. The sacrificial gate layer 82 can be removed by an etching process that is selective to the gate layer 82, wherein the dielectric layer 80 acts as an etching stop layer. In some embodiments, one or more etching processes can then be performed to remove the dielectric layer 80 and the gate spacer layers 86 and 88. The etching process can be, for example, RIE, NBE, wet etching, or another etching process. In some embodiments, the dielectric layer 80 is not removed. Figure 8, after removing the sacrificial gate layer 82, gate spacer layers 86, 88, and in some embodiments, the dielectric layer 80, an opening 106 is formed in the boundary region 104. After removing the sacrificial gate layer 82, gate spacer layers 86, 88, and the dielectric layer 80, a portion of the fin 74 may be exposed.

[0073] like Figure 9 As shown in FIG, a metal-insulator-metal (MIM) structure 108 is formed in each opening 106. The MIM structure 108 may include one or more MIM capacitors. In some embodiments, as shown in FIG. Figure 9 As shown in FIG, MIM structure 108 includes a first conductive layer 110, a dielectric layer 112 disposed on the first conductive layer 110, and a second conductive layer 114 disposed on the dielectric layer 112. In some embodiments, the first conductive layer 110 and the second conductive layer 114 each comprise a metal or a metal nitride. For example, the first conductive layer 110 and the second conductive layer 114 each comprise titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), platinum (Pt), or a combination thereof. In some embodiments, the first conductive layer 110 and the second conductive layer 114 comprise the same material. In some embodiments, dielectric layer 112 comprises a high-k dielectric material, such as zirconium oxide (ZrO2). Alternatively, dielectric layer 112 may include one or more layers of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium silicate (HfSiON), tantalum oxide (Ta2O5), hafnium oxide (HfO2), titanium oxide (TiO2), barium strontium titanate (BST), strontium titanate oxide (STO), or combinations thereof. MIM structure 108 may contact the exposed portions of fin 74 (if dielectric layer 80 is removed) or dielectric layer 80.

[0074] In some embodiments, the MIM structure 108 can be formed by first forming a first conductive layer 110 in the opening 106. The first conductive layer 110 can be a conformal layer formed by a conformal process such as an ALD process. Next, a dielectric layer 112 is formed on the first conductive layer 110 in the opening 106. The dielectric layer 112 can be a conformal layer formed by a conformal process. Next, a second conductive layer 114 is formed on the dielectric layer 112 to fill the opening 106. Portions of the first conductive layer 110, the dielectric layer 112, and the second conductive layer 114 can be formed on a mask layer (not shown) formed in the IP blocks 102-1 and 102-2, and a CMP process can be performed to remove the portions of the first conductive layer 110, the dielectric layer 112, and the second conductive layer 114 formed on the mask layer in the IP blocks 102-1 and 102-2. The mask layer in the IP blocks 102-1 and 102-2 can also be removed by a CMP process. Figure 9 The resulting structure is shown in .

[0075] The MIM structure 108 in the boundary region 104 reduces the CMP dishing effect because the MIM structure 108 comprises different materials. In addition, the MIM structure 108 provides a MIM capacitor in the front-end-of-line (FEOL) process, which can save metal wiring to reduce IR drop compared to the MIM capacitor in the back-end-of-line (BEOL) process. It should be understood that Figure 9 The example of the MIM structure 108 shown in FIG. 1 is illustrative and not limiting, and the MIM structure 108 may have different configurations.

[0076] FIG. 10A to FIG. 10B According to some embodiments Figure 9 Various views of the MIM structure 108. Figure 10A is a top view of the MIM structure 108, and Figure 10B is a cross-sectional side view of the MIM structure 108. In some embodiments, the first conductive layer 110 is not a conformal layer. For example, the first conductive layer 110 may be formed in the opening 106 ( Figure 8 ) to fill the opening 106. Then, one or more openings are formed in the first conductive layer 110, and a dielectric layer 112 and a second conductive layer 114 are formed in the openings in the first conductive layer 110, as shown in FIG. Figure 10A and Figure 10BIn some embodiments, the opening in the first conductive layer 110 extends through the first conductive layer 110 and separates the first conductive layer 110 into a plurality of discrete portions. In some embodiments, the dielectric layer 112 contacts a portion of the fin 74 or the dielectric layer 80. Next, a CMP process may be performed to remove portions of the first conductive layer 110, the dielectric layer 112, and the second conductive layer 114 formed on the mask layer in the IP blocks 102-1 and 102-2. The mask layer in the IP blocks 102-1 and 102-2 may also be removed by a CMP process, and in Figure 10B The resulting structure is shown in FIG. Then, a conductive contact 116 is formed on the first conductive layer 110 and the second conductive layer 114, as shown in FIG. Figure 10A and Figure 10B As shown in FIG. , the conductive contact 116 comprises a conductive material, such as a metal. In some embodiments, the conductive contact 116 comprises tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or combinations thereof. Figure 22A ) to form a conductive contact 116, and the conductive contact 116 can be connected to the gate electrode 122 ( Figure 22A ) are formed simultaneously.

[0077] In some embodiments, as Figure 10A As shown in FIG, the length of the MIM structure 108 in the X direction is substantially small, such as less than about 90 nm, and the first conductive layer 110 and the second conductive layer 114 each have discrete portions. For example, the discrete portions of the first conductive layer 110 are aligned along the Y direction and separated by discrete portions of the second conductive layer 114. Each discrete portion of the second conductive layer 114 is surrounded by the dielectric layer 112, as shown in FIG. Figure 10A In some embodiments, the length of the MIM structure 108 is determined by the length of the gate electrode layer (or metal gate). The gate electrode layer may have a length greater than about 90 nm, and the first conductive layer 110 may be a continuous layer surrounding multiple discrete portions of the second conductive layer 114.

[0078] Figures 11A to 11B According to an alternative embodiment Figure 9 Various views of the MIM structure 108. Figure 11A is a top view of the MIM structure 108, and Figure 11B is a cross-sectional side view of the MIM structure 108. Figure 11A As shown in FIG, the length of the MIM structure 108 is substantially greater than Figure 10A In some embodiments, Figure 11AThe length of the MIM structure 108 shown in FIG is greater than about 90 nm. With a larger length along the X direction, the openings formed in the first conductive layer 110 may not separate the first conductive layer 110 into discrete portions. In some embodiments, the first conductive layer 110 is a continuous layer having one or more openings filled with discrete portions of the dielectric layer 112 and the second conductive layer 114, such as Figure 11A In addition, in some embodiments, the opening in the first conductive layer 110 does not extend through the first conductive layer 110, and a dielectric layer 112 is formed on the first conductive layer 110, as shown in FIG. Figure 11B In some embodiments, the opening in the first conductive layer 110 extends through the first conductive layer and forms a dielectric layer 112 on a portion of the fin 74 or the dielectric layer 80. Figure 10A and Figure 10B The same process as the MIM structure 108 in FIG. 1 is used to form the first conductive layer 110, the dielectric layer 112, the second conductive layer 114 and the conductive contact 116. In some embodiments, as Figure 11B As shown in FIG, the top surface of the first conductive layer 110 is substantially coplanar with the top surface of the second conductive layer 114 .

[0079] like Figure 11B As shown in FIG, the conductive contact 116 formed on the first conductive layer 110 does not contact the second conductive layer 114. Therefore, the process window for forming the conductive contact 116 on the first conductive layer 110 is substantially smaller. For example, in the second ILD 130 ( Figure 22A ) for forming an opening for the conductive contact 116 formed on the first conductive layer 110 cannot expose the second conductive layer 114. In some embodiments, in order to expand the process window for forming the conductive contact 116 on the first conductive layer 110, as shown in FIG. FIG. 12A to FIG. 12B A general modified MIM structure 108 is shown in FIG.

[0080] FIG. 12A to FIG. 12B According to an alternative embodiment Figure 9 Various views of the MIM structure 108. Figure 12A is a top view of the MIM structure 108, and Figure 12B is a cross-sectional side view of the MIM structure 108. Figure 12B As shown in FIG, the first conductive layer 110 is recessed from the top surface of the second conductive layer 114, and a dielectric material 140 (or dielectric region) is formed on the first conductive layer 110 adjacent to the second conductive layer 114. Figure 12A and Figure 12BAs shown in FIG, the vertical side of the second conductive layer 114 is surrounded by the dielectric material 140, and the bottom of the second conductive layer 114 is disposed above the first conductive layer 110, wherein the dielectric layer 112 is disposed therebetween. In some embodiments, the dielectric material 140 may include a dielectric material having a dielectric constant similar to that of the first ILD 100 ( Figure 6A In some embodiments, a dielectric material is formed on the first ILD 100, and the dielectric material 140 may include the same material as the first ILD 100.

[0081] 13A to 13C According to some embodiments FIG. 12A to FIG. 12B A cross-sectional side view of the intermediate structure of the MIM structure 108. FIG. 12A to FIG. 12B MIM structure 108, Figures 11A to 11B The MIM structure 108 shown in FIG can be a starting point, such as Figure 13A Next, as shown in Figure 13B As shown in FIG, portions of the first conductive layer 110 disposed adjacent to the vertical sides of the second conductive layer 114 are recessed. In some embodiments, these portions are completely removed, thereby leaving the first conductive layer 110 having a substantially constant thickness in the Z direction, as shown in FIG. Figure 13B . In some embodiments, these portions are recessed, and the thickness of the edge portions of the first conductive layer 110 (the portions on which the second conductive layer 114 is not disposed) is substantially greater than the thickness of the central portion of the first conductive layer 110 (the portion on which the second conductive layer 114 is disposed). In some embodiments, these portions are completely removed by overetching. Therefore, the thickness of the edge portions of the first conductive layer 110 is substantially less than the thickness of the central portion of the first conductive layer 110. The process of removing / recessing the portions of the first conductive layer 110 disposed adjacent to the vertical sides of the second conductive layer 114 can be a selective etching process that does not substantially affect the sacrificial gate layer 82, the gate spacer layers 86, 88, the first ILD 100 (or the dielectric material formed on the first ILD 100), the CESL 96, the dielectric layer 112, and the second conductive layer 114. In some embodiments, a portion of the second conductive layer 114 can also be removed by the selective etching process, and the resulting top surface of the second conductive layer 114 can have a concave profile.

[0082] Next, if Figure 13CAs shown in FIG, dielectric material 140 is formed in the openings created by removing / recessing portions of first conductive layer 110. Dielectric material 140 may be formed by any suitable process. In some embodiments, dielectric material 140 is formed by the same process as first ILD 100. A planarization process, such as a CMP process, may be performed to remove portions of dielectric material 140 formed in IP blocks 102-1, 102-2 and on second conductive layer 114, as shown in FIG. Figure 13C As shown in FIG. The dielectric material 140 may have a top surface that is substantially coplanar with the top surface of the second conductive layer 114. Figure 22A ), openings are formed in the second ILD 130 and the dielectric material 140. In some embodiments, openings are also formed in the CESL 96 and the first ILD 100, the CESL 96 and the first ILD 100 are positioned adjacent to the dielectric material 140, and the side surface 110S of the first conductive layer 110 may be exposed in the openings. Figure 11B Compared to the opening of the conductive contact 116 shown in FIG, the opening can be further away from the second conductive layer 114. Next, the conductive contact 116 is formed in the opening, as shown in FIG. Figure 12B The conductive contact 116 may contact a portion of the top surface of the first conductive layer 110 and the side surface 110S of the first conductive layer 110. Due to the presence of the dielectric material 140, the process window for forming the conductive contact 116 is expanded.

[0083] 14A to 14C are various views of a MIM structure 208 according to some embodiments. Figure 14A is a top view of the MIM structure 208, Figure 14B yes Figure 14A A cross-sectional side view of the MIM structure 208 taken along line CC, and Figure 14C yes Figure 14A A cross-sectional side view of the MIM structure 208 taken along line DD. 14A to 14C As shown in FIG, MIM structure 208 includes more than one MIM capacitor. In some embodiments, a first MIM capacitor includes a first conductive layer 202 and a second conductive layer 210 separated by a dielectric layer 80, while a second MIM capacitor includes a second conductive layer 210 and a third conductive layer 214 separated by a dielectric layer 212.

[0084] 15A to 15D 、 16A to 16B 、 17A to 17B 、 18A to 18B and Figures 19A to 19B According to some embodiments, the formation includes 14A to 14CVarious views of respective intermediate structures at intermediate stages in the example processing of the MIM structure 208 of the semiconductor device structure 40 . 15A to 15D yes Figure 1C FIG. 4 is a cross-sectional side view of the boundary region 104 of the semiconductor device structure 40 taken along line BB. Figure 15A As shown in FIG, the semiconductor device structure 40 is at a stage before forming the isolation region 78. Fins 74 are formed from the semiconductor substrate 70, and a dielectric material 204 (or dielectric region) is formed between adjacent fins 74. The dielectric material 204 may also be formed on the top surface of the fin 74, and a planarization process such as a CMP process may be performed to remove a portion of the dielectric material 204 and expose the top surface of the fin 74. The dielectric material 204 may include the same material as the isolation region 78. Next, in the IP blocks 102-1, 102-2 ( Figure 8 ) to protect the fins 74 and the dielectric material 204 formed in the first IP block 102-1 and the second IP block 102-2, and to remove a portion of each fin 74 in the boundary region 104, as shown in FIG. Figure 15B As shown in . A portion of the fin 74 may be removed by any suitable process such as dry etching, wet etching, or a combination thereof. The etching process may be a selective etching process that does not substantially affect the dielectric material 204 . An opening 201 is formed over the remaining fin 74 in the boundary region 104 .

[0085] Next, if Figure 15C As shown in , a first conductive layer 202 is formed in the opening 201. The first conductive layer 202 may include the same material as the first conductive layer 110 and may be formed by the same process as the first conductive layer 110. The first conductive layer 202 may also be formed on the dielectric material 204 in the boundary region 104 and on the mask layer in the first IP block 102-1 and the second IP block 102-2. A planarization process such as a CMP process may be performed to remove portions of the first conductive layer 202 formed on the dielectric material 204 in the boundary region 104 and on the mask layer in the first IP block 102-1 and the second IP block 102-2. The CMP process may also remove the mask layer in the first IP block 102-1 and the second IP block 102-2. Figure 15D As shown in FIG, the dielectric material 204 is recessed to form the isolation region 78. In some embodiments, the semiconductor device structure 40 includes the fins 74 extending over the isolation region 78 in the first IP block 102-1 and the second IP block 102-2 and the first conductive layer 202 extending over the isolation region 78 in the boundary region 104. In some embodiments, the isolation region 78 includes a top surface at or below the level of the top surface of the remaining fins 74 in the boundary region 104, as shown in FIG. Figure 15D As shown in .

[0086] Next, the semiconductor device structure 40 is processed, such as Figures 2A to 6B The process described in Figure 6A and Figure 6B FIG. 4 shows the resulting semiconductor device structure 40 in the first IP block 102-1 and the second IP block 102-2, and FIG. Figure 16A and Figure 16B The resulting semiconductor device structure 40 in the boundary region 104 is shown in FIG. Figure 16A and Figure 16B As shown in FIG, a dielectric layer 80 is formed on the first conductive layer 202, and a sacrificial gate layer 82 is formed on the dielectric layer 80. For clarity, Figure 16B The gate spacer layers 86 and 88 are omitted. Figure 16B As shown in FIG, a CESL 96 and a first ILD 100 are formed over a portion of the first conductive layer 202 , and a planarization process is performed to expose the sacrificial gate layer 82 .

[0087] like Figure 17A and Figure 17B As shown in FIG, a mask layer (not shown) is formed in the first IP block 102-1 and the second IP block 102-2 to protect the materials in the first IP block 102-1 and the second IP block 102-2, and the sacrificial gate layer 82 exposed in the boundary region 104 is removed and replaced with the second conductive layer 210. In some embodiments, the gate spacer layers 86 and 88 in the boundary region 104 are also removed. Figure 17A and Figure 17B In the embodiment shown in FIG, the dielectric layer 80 is not removed but remains on the first conductive layer 202. The dielectric layer 80 acts as the MIM structure 208 ( 14A to 14C ) of the MIM capacitor. The second conductive layer 210 may include the same material as the first conductive layer 110 and may be formed by the same process as the first conductive layer 110. Figure 8 ) to form a second conductive layer 210.

[0088] like Figure 18A and Figure 18BAs shown in FIG, an opening is formed in the second conductive layer 210, and a dielectric layer 212 and a third conductive layer 214 are formed in the opening. The dielectric layer 212 may include the same material as the dielectric layer 112 and may be formed by the same process as the dielectric layer 112. The third conductive layer 214 may include the same material as the second conductive layer 114 and may be formed by the same process as the second conductive layer 114. Portions of the second conductive layer 210, the dielectric layer 212, and the third conductive layer 214 may be formed on a mask layer (not shown) formed in the IP blocks 102-1 and 102-2, and a CMP process may be performed to remove portions of the second conductive layer 210, the dielectric layer 212, and the third conductive layer 214 formed on the mask layer in the IP blocks 102-1 and 102-2. The mask layer in the IP blocks 102-1 and 102-2 may also be removed by the CMP process. The resulting semiconductor device structure 40 may include a sacrificial gate layer 82 in the first IP block 102 - 1 and the second IP block 102 - 2 , the sacrificial gate layer 82 having a top surface substantially coplanar with top surfaces of the second conductive layer 210 and the third conductive layer 214 in the boundary region 104 .

[0089] In the case of using gate electrode 122 ( Figure 22A ) replaces the sacrificial gate layer 82 in the first IP block 102 - 1 and the second IP block 102 - 2 and forms the second ILD 130 ( Figure 22A ), a conductive contact 116 is formed on the second conductive layer 210 and the third conductive layer 214, as shown in FIG. Figure 19A and Figure 19B The conductive contact 116 in contact with the first conductive layer 202 may extend through the first ILD 100 and the CESL 96, as shown in FIG. Figure 19B In addition, the length of the first conductive layer 202 in the X direction is substantially greater than the length of the second conductive layer 210 so as to accommodate the conductive contacts 116 .

[0090] FIG. 20A to FIG. 20B According to an alternative embodiment Figures 11A to 11B MIM structure 108 or Figures 19A to 19B A top view of the MIM structure 208 is shown. FIG. 20A to FIG. 20B As shown in FIG, the conductive layer 114 / 214 can be configured in any suitable pattern. In some embodiments, the conductive layer 114 / 214 and the dielectric layer 112 / 212 have a width W and a length L, and adjacent conductive layers 114 / 214 and dielectric layers 112 / 212 are separated by a distance S in the Y direction. In some embodiments, the width W, length L, and distance S can be greater than approximately 0.144 μm. Thus, CMP dishing effects can be reduced.

[0091] Figures 21A to 21Cis a cross-sectional view of an intermediate structure at an intermediate stage in an example process of forming semiconductor device structure 40 in accordance with some embodiments. Figures 21A to 21B The semiconductor device structure 40 in the first IP block 102-1 and the second IP block 102-2 is illustrated. Figure 21C The gate spacer layers 86 and 88 are omitted. Figures 21A to 21C As shown in FIG, a mask layer (not shown) is formed over the MIM structure 108 / 208 in the boundary region 104, and the sacrificial gate layer 82 in the first IP block 102-1 and the second IP block 102-2 is removed. The sacrificial gate layer 82 can be removed by any suitable process. In some embodiments, the dielectric layer 80 disposed under the sacrificial gate layer 82 is also removed. After the sacrificial gate layer 82 and the dielectric layer 80 are removed, a replacement gate structure is formed in the recess from which the gate stack was removed.

[0092] Figures 22A to 22C is a cross-sectional view of an intermediate structure at an intermediate stage in an example process of forming semiconductor device structure 40 in accordance with some embodiments. FIG. 22A to FIG. 22B The semiconductor device structure 40 in the first IP block 102-1 and the second IP block 102-2 is illustrated. Figure 22C The gate spacer layers 86 and 88 are omitted. Figures 22A to 22C As shown in , each replacement gate structure includes one or more conformal layers 120 and a gate electrode 122. The one or more conformal layers 120 include a gate dielectric layer and may include one or more work function tuning layers. The gate dielectric layer may be conformally deposited in the recess from which the gate stack has been removed. The gate dielectric layer may be or include silicon oxide, silicon nitride, a high-k dielectric material, a multilayer thereof, or other dielectric material. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. Next, a gate electrode 122 is formed over the one or more conformal layers 120. The layer for the gate electrode 122 may fill the remaining recess from which the gate stack has been removed. The gate electrode 122 may include one or more layers of a conductive material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof.

[0093] In some embodiments, the gate electrode 122 includes a p-type gate electrode and an n-type gate electrode. For example, the gate electrode 122 formed in the first IP block 102-1 is an n-type gate electrode, while the gate electrode 122 formed in the second IP block 102-2 is a p-type gate electrode. The n-type and p-type gate electrodes 122 can be formed by first depositing a first-type gate electrode 122, such as an n-type or p-type, in both the first IP block 102-1 and the second IP block 102-2. A planarization process, such as a CMP process, is then performed to remove portions of the first-type gate electrode 122 formed on the first ILD 100 and in the boundary region 104. The CMP process can also be used to remove a mask layer formed in the boundary region 104 to protect the MIM structure 108 / 208. As described above, because the MIM structure 108 / 208 comprises multiple materials, the CMP dishing effect is reduced. Next, another mask layer is formed in the first IP block 102-1 and the boundary region 104 to protect the first type gate electrode and the MIM structure 108 / 208. The first type gate electrode 122 formed in the second IP block 102-2 is removed, and a second type gate electrode opposite to the first type gate electrode is formed in the second IP block 102-2. Another CMP process is then performed to remove a portion of the second type gate electrode formed in the first IP block 102-1 and the boundary region 104, and the mask layer formed in the first IP block 102-1 and the boundary region 104 is also removed by the CMP process. Figure 22C The resulting semiconductor device structure 40 is shown in FIG. In some embodiments, the top surface of the gate electrode 122 and the top surface of the MIM structure 108 / 208 / 308 can be substantially coplanar, as shown in FIG. Figure 22C The top surface of the MIM structure 108 / 208 / 308 may include the top surface of the conductive layer 110 ( Figure 10B 、 Figure 11B ), the top surface of the conductive layer 114 ( Figure 10B 、 Figure 11B 、 Figure 12B ), the top surface of the dielectric material 140 ( Figure 12B ), the top surface of the conductive layer 210 ( Figure 14B ) and / or the top surface of the conductive layer 214 ( Figure 14B ).

[0094] Next, if Figure 22A and Figure 22BAs shown in FIG, a second ILD 130 is formed over the replacement gate structure, the first ILD 100, and the MIM structure 108 / 208, and a conductive feature 134 is formed through the second ILD 130, the first ILD 100, and the CESL 96 to the epitaxial source / drain region 92. Although not illustrated, in some examples, an etch stop layer (ESL) may be deposited over the first ILD 100, etc., and the second ILD 130 may be deposited over the ESL. If implemented, the ESL may include or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or a combination thereof. The second ILD 130 may include or be silicon dioxide, a low-k dielectric material (such as silicon oxynitride), PSG, BSG, BPSG, USG, FSG, OSG, SiO x C y , spin-on glass, spin-on polymer, silicon carbide material, compounds thereof, composites thereof, the like, or combinations thereof. Conductive features 134 may be formed through the second ILD 130, the first ILD 100, and the CESL 96 to the epitaxial source / drain regions 92. Silicide regions 136 may be formed on upper portions of the epitaxial source / drain regions 92 by reacting the upper portions of the epitaxial source / drain regions 92 with the conductive features 134. The conductive contacts 116 of the MIM structure 108 / 208 may be formed before, after, or simultaneously with the conductive features 134. In some embodiments, the conductive contacts 116 are formed after the conductive features 134 are formed and simultaneously with the conductive features (not shown) of the gate electrode 122. For clarity, the conductive features 134 are formed in the embodiment of FIG. Figure 22C The second ILD 130 , the conductive features 134 , and the conductive contacts 116 are omitted.

[0095] FIG. 23A to FIG. 23B 3 are various views of a MIM structure 308 according to an alternative embodiment. The semiconductor device structure 40 including the MIM structure 108 / 208 shown in the previous figures is based on FinFET. The MIM structure in the boundary region 104 for reducing the CMP recess effect can be applied to other types of devices, such as planar FETs, nanostructured FETs, horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices. In some embodiments, planar FETs are formed in the first IP block 102-1 and the second IP block 102-2, and the MIM structure 308 is formed in the boundary region 104. FIG. 23A to FIG. 23BAs shown in FIG, a MIM structure 308 is formed over a semiconductor substrate 302. The semiconductor substrate 302 may include the same material as the semiconductor substrate 70. A first conductive layer 304 is formed in the semiconductor substrate 302. The first conductive layer 304 may include the same material as the first conductive layer 202 and may be formed using the same process as the first conductive layer 202. A mask layer may be formed in the first IP block 102-1 and the second IP block 102-2, and the mask layer may expose a portion of the semiconductor substrate 302 located in the boundary region 104. An opening is formed in the exposed portion of the semiconductor substrate 302, and the first conductive layer 304 is formed in the opening.

[0096] Next, a dielectric layer 306 is formed on the first conductive layer 304. The dielectric layer 306 may include the same material as the dielectric layer 80 and may be formed using the same process as the dielectric layer 80. The dielectric layer 306 may also be formed in the first IP block 102-1 and the second IP block 102-2. The dielectric layer 306 may be formed by first forming a continuous layer in the first IP block 102-1 and the second IP block 102-2 and the boundary region 104. The continuous layer is then patterned to form the dielectric layer 306. A sacrificial gate layer (not shown) is formed on the dielectric layer 306 in the first IP block 102-1 and the second IP block 102-2 and the boundary region 104. A gate spacer layer (not shown) may be formed on opposite sides of the sacrificial gate layer in the first IP block 102-1 and the second IP block 102-2. The gate spacer layer may include the same material as gate spacer layers 86 and 88 and may be formed using the same process as gate spacer layers 86 and 88. In some embodiments, no gate spacer layer is formed in boundary region 104. This can be achieved by forming a mask layer in boundary region 104 before forming the gate spacer layer. Still utilizing the mask layer formed in boundary region 104, source / drain regions (not shown) may be formed on opposite sides of the sacrificial gate layer in first IP block 102-1 and second IP block 102-2. After forming the source / drain regions, the mask layer in boundary region 104 is removed, and CESL and a first ILD are formed in first IP block 102-1, second IP block 102-2, and boundary region 104.

[0097] Next, a mask layer is formed in the first IP block 102-1 and the second IP block 102-2 to protect the sacrificial gate layer located therein, and the sacrificial gate layer exposed in the boundary region 104 is removed. A second conductive layer 310 is formed in the opening created by removing the sacrificial gate layer. The second conductive layer 310 may include the same material as the second conductive layer 210 and may be formed using the same process as the second conductive layer 310. Openings are formed in the second conductive layer 310. A dielectric layer 312 and a third conductive layer 314 are formed in each opening in the second conductive layer 310. The dielectric layer 312 may include the same material as the dielectric layer 212 and may be formed using the same process as the dielectric layer 212. The third conductive layer 314 may include the same material as the third conductive layer 214 and may be formed using the same process as the third conductive layer 214. In some embodiments, the MIM structure 308 includes a first MIM capacitor having a first conductive layer 304, a dielectric layer 306, and a second conductive layer 310, and a second MIM capacitor having a second conductive layer 310, a dielectric layer 312, and a third conductive layer 314. After forming the MIM structure 308 in the boundary region 104, a mask layer is formed in the boundary region 104, and processes such as Figures 21A to 21C and Figures 22A to 22C The process described in the above is to complete the planar FET. Then, in a second ILD 130 ( Figure 22A ) and a conductive contact 116 is formed in a second ILD (not shown).

[0098] In various embodiments, the present disclosure provides semiconductor device structures and methods for forming the same. In some embodiments, the semiconductor device structure 40 includes a MIM structure 108 / 208 / 308 located in the boundary region 104. The MIM structure 108 / 208 / 308 may include one or more MIM capacitors. Some embodiments may realize advantages. For example, utilizing the MIM structure 108 / 208 / 308 formed in the boundary region 104 reduces CMP dishing effects during the formation of the gate electrode 122. Furthermore, compared to MIM structures in the BEOL, the MIM structure 108 / 208 / 308 located in the FEOL can save metal wiring, thereby reducing IR drop.

[0099] An embodiment provides a semiconductor device structure. The structure includes a first region, a second region, and a boundary region disposed between the first region and the second region, the first region including a gate electrode disposed above a semiconductor fin. The boundary region includes a metal-insulator-metal (MIM) structure, and the MIM structure includes a first conductive layer disposed above the semiconductor fin, a first dielectric layer in contact with the first conductive layer, and a second conductive layer in contact with the first dielectric layer. The top surface of the second conductive layer and the top surface of the gate electrode may be substantially coplanar. In some embodiments of the present disclosure, the first conductive layer is disposed adjacent to multiple vertical sides of the second conductive layer, and the first dielectric layer is disposed between the multiple vertical sides of the first conductive layer and the second conductive layer. In some embodiments of the present disclosure, the first dielectric layer contacts the semiconductor fin. In some embodiments of the present disclosure, the semiconductor device structure further includes a dielectric region surrounding the multiple vertical sides of the second conductive layer, wherein the dielectric region is disposed on the first conductive layer. In some embodiments of the present disclosure, the first dielectric layer contacts the dielectric region. In some embodiments of the present disclosure, a top surface of the dielectric region is coplanar with the top surface of the second conductive layer. In some embodiments of the present disclosure, a width of the boundary region is between 0.1 μm and 3.0 μm. In some embodiments of the present disclosure, the second conductive layer and the first dielectric layer have a combined length and a combined width, and the combined length and the combined width are greater than 0.144 μm. In some embodiments of the present disclosure, the semiconductor device structure further includes a third conductive layer disposed on the semiconductor fin and a second dielectric layer disposed on the third conductive layer, wherein the first conductive layer is in contact with the second dielectric layer.

[0100] Another embodiment is a semiconductor device structure. The structure includes a first region, a second region, and a boundary region disposed between the first region and the second region, the first region including a gate electrode. The boundary region includes a metal-insulator-metal (MIM) structure, and the MIM structure includes a first conductive layer, a first dielectric layer in contact with the first conductive layer, and a second conductive layer in contact with the first dielectric layer. The top surface of the second conductive layer and the top surface of the first conductive layer may be substantially coplanar. In some embodiments of the present disclosure, the semiconductor device structure further includes a third conductive layer disposed below the first conductive layer and a second dielectric layer disposed between the first conductive layer and the third conductive layer. In some embodiments of the present disclosure, a width of the third conductive layer is greater than a width of the first conductive layer. In some embodiments of the present disclosure, the semiconductor device structure further includes a contact etch stop layer in contact with the first conductive layer and the second dielectric layer, and an interlayer dielectric disposed on the contact etch stop layer. In some embodiments of the present disclosure, the semiconductor device structure further includes a conductive contact disposed through the interlayer dielectric, the contact etch stop layer, and the second dielectric layer, wherein the conductive contact contacts the third conductive layer. In some embodiments of the present disclosure, a top surface of the interlayer dielectric is coplanar with a top surface of the second conductive layer. In some embodiments of the present disclosure, the contact etch stop layer and the interlayer dielectric are disposed adjacent to the gate electrode.

[0101] Another embodiment is a method. The method includes forming a fin above a substrate, wherein the fin is disposed in a first region, a second region, and a boundary region, wherein the boundary region is disposed between the first region and the second region. The method further includes forming a first sacrificial gate layer above a first portion of the fin located in the first region, forming a second sacrificial gate layer above a second portion of the fin located in the second region, and forming a third sacrificial gate layer above a third portion of the fin located in the boundary region. The method further includes removing the third sacrificial gate layer to create an opening; forming a metal-insulator-metal (MIM) structure in the opening; removing the first sacrificial gate layer and the second sacrificial gate layer to form openings in the first region and the second region; and depositing a gate electrode in the opening in the first region and the second region. A top surface of the gate electrode is substantially coplanar with a top surface of the MIM structure. In some embodiments of the present disclosure, the step of forming the metal-insulator-metal structure includes depositing a first conductive layer in the opening; depositing a dielectric layer on the first conductive layer; and depositing a second conductive layer on the dielectric layer. In some embodiments of the present disclosure, the step of forming the metal-insulator-metal structure further includes removing multiple portions of the first conductive layer and depositing a dielectric region to surround multiple vertical sides of the second conductive layer. In some embodiments of the present disclosure, the method further includes recessing the third portion of the fin and depositing a third conductive layer on the recessed third portion of the fin before forming the third sacrificial gate layer. In some embodiments of the present disclosure, a semiconductor device structure includes: a first region including a gate electrode; a second region; and a boundary region disposed between the first region and the second region, wherein the boundary region includes a metal-insulator-metal structure, and the metal-insulator-metal structure includes: a first conductive layer; a first dielectric layer in contact with the first conductive layer; and a second conductive layer in contact with the first dielectric layer; and a dielectric region disposed on the first conductive layer and surrounding multiple vertical sides of the second conductive layer, wherein a top surface of the second conductive layer is coplanar with a top surface of the first conductive layer, and a top surface of the dielectric region is coplanar with the top surface of the second conductive layer.

[0102] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, characterized in that: include: a first region comprising a gate electrode disposed above a semiconductor fin; a. Second District; and A boundary region is disposed between the first region and the second region, wherein the boundary region comprises a metal-insulator-metal structure, and the metal-insulator-metal structure comprises: a first conductive layer disposed above the semiconductor fin; a first dielectric layer in contact with the first conductive layer; and A second conductive layer contacts the first dielectric layer, wherein a top surface of the second conductive layer is coplanar with a top surface of the gate electrode.

2. The semiconductor device structure according to claim 1, wherein: The first conductive layer is disposed adjacent to a plurality of vertical sides of the second conductive layer, and the first dielectric layer is disposed between the first conductive layer and the plurality of vertical sides of the second conductive layer.

3. The semiconductor device structure according to claim 1, wherein: The first dielectric layer contacts the semiconductor fin.

4. The semiconductor device structure according to claim 1, wherein: The method further includes a dielectric region surrounding a plurality of vertical sides of the second conductive layer, wherein the dielectric region is disposed on the first conductive layer.

5. The semiconductor device structure according to claim 4, wherein: The first dielectric layer contacts the dielectric region.

6. The semiconductor device structure according to claim 1, wherein: A width of the boundary region is between 0.1 μm and 3.0 μm.

7. The semiconductor device structure according to claim 1, wherein: The second conductive layer and the first dielectric layer have a combined length and a combined width, and the combined length and the combined width are greater than 0.144 μm.

8. The semiconductor device structure according to claim 1, wherein: The invention further comprises a third conductive layer disposed on the semiconductor fin and a second dielectric layer disposed on the third conductive layer, wherein the first conductive layer contacts the second dielectric layer.

9. A semiconductor device structure, characterized in that: include: a first region comprising a gate electrode; a. Second District; and A boundary region is disposed between the first region and the second region, wherein the boundary region comprises a metal-insulator-metal structure, and the metal-insulator-metal structure comprises: a first conductive layer; a first dielectric layer in contact with the first conductive layer; and A second conductive layer contacts the first dielectric layer, wherein a top surface of the second conductive layer is coplanar with a top surface of the first conductive layer.

10. A semiconductor device structure, characterized in that: include: a first region comprising a gate electrode; a. Second District; and A boundary region is disposed between the first region and the second region, wherein the boundary region comprises a metal-insulator-metal structure, and the metal-insulator-metal structure comprises: a first conductive layer; a first dielectric layer in contact with the first conductive layer; a second conductive layer in contact with the first dielectric layer; and A dielectric region is disposed on the first conductive layer and surrounds multiple vertical sides of the second conductive layer, wherein a top surface of the second conductive layer is coplanar with a top surface of the gate electrode, and a top surface of the dielectric region is coplanar with the top surface of the second conductive layer.

Images