Semiconductor device

Abstract

The utility model provides a semiconductor device. The semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, where the first anode is coupled to the second anode, and the second cathode is connected to the first supply voltage. The semiconductor device includes a third diode having a third cathode connected to the first anode at the input / output pin and a third anode connected to the second supply voltage. The second anode is coupled to a circuit powered by the first supply voltage and the second supply voltage. The first diode has a first size, the second diode has a second size, and the first size is substantially larger than the second size.

Description

Technical Field

[0001] The utility model relates to a semiconductor device. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. This increase in integration density is largely due to the continued reduction in minimum feature size, which allows more components to be integrated into a given area. Utility Model Content

[0003] The utility model provides a semiconductor device, comprising: a first diode having a first cathode and a first anode, wherein the first cathode is floating; a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode, and the second cathode is connected to a first supply voltage; and a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input / output pin, and the third anode is connected to a second supply voltage; wherein the second anode is coupled to a circuit powered by the first supply voltage and the second supply voltage; wherein the first diode has a first size and the second diode has a second size, and the first size is substantially larger than the second size.

[0004] The utility model provides a semiconductor device, comprising: a substrate having a first conductivity; a first well surrounded by the substrate and having a second conductivity; a second well surrounded by the substrate and having the second conductivity; a first contact region surrounded by the first well and having the first conductivity; a second contact region surrounded by the second well and having the first conductivity; a third contact region also surrounded by the second well and having the second conductivity; a fourth contact region surrounded by the substrate, arranged on a first lateral side of the first well and the second well, and having the second conductivity; a fifth contact region surrounded by the substrate, arranged opposite to the fourth contact region relative to the first well and the second well, and having the first conductivity; a sixth contact region surrounded by the substrate, arranged on a second lateral side of the first well, and having the second conductivity; and a seventh contact region surrounded by the substrate, arranged adjacent to the sixth contact region relative to the first well, and having the first conductivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1 A diagram illustrating an example circuit for electrostatic discharge (ESD) protection according to some embodiments.

[0007] Figure 2 During an ESD event, according to some embodiments Figure 1 Example electrical paths within the example circuit shown.

[0008] Figure 3 shows similarity to that according to some embodiments Figure 1 Another example circuit for ESD protection of the example circuit shown.

[0009] Figures 4A to 4C According to some embodiments, a method for forming Figure 1 Example structures of diodes implemented in example circuits are shown.

[0010] Figure 5 Shown according to some embodiments Figure 1 Example layout of example circuit shown.

[0011] 6A to 6D Showing the Figure 5 Example positioning of the N-well associated with the example layout is shown.

[0012] 7A to 7C shows similarity to that according to some embodiments Figure 1 Example circuit shown, example layout of example circuit with six diodes for ESD protection.

[0013] Figure 8 A method for positioning according to some embodiments is shown. Figure 1 Example placement of resistors for the example circuit shown.

[0014] Figures 9A to 9C Shown are some embodiments of the Figure 1 Example placement of resistors for the example circuit shown.

[0015] Figure 10 is an example flow chart of a method for forming a semiconductor device according to some embodiments.

[0016] Figure 11 is an example flow chart of another method for fabricating a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0017] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one device or feature illustrated in the figures to another device or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0019] Generally speaking, semiconductor devices or circuits fabricated using complementary metal-oxide-semiconductor (CMOS) technology, among other types of fabrication processes, can be designed to meet or satisfy desired reliability specifications. For certain communication interfaces (e.g., advanced high-speed interfaces), such as, but not limited to, universal serial bus (USB), peripheral component interconnect express (PCIe), and Ethernet, electrostatic discharge (ESD) protection designs require relatively low parasitic capacitance (e.g., the parasitic capacitance of diodes) to reduce or minimize signal loss and smooth electrical ripple (e.g., having multiple diodes with corresponding capacitances increases capacitance distribution, thereby providing local ripple reduction and improved noise filtering, reducing parasitic inductance and resistance, enhancing frequency response, and / or improving voltage regulation) while maintaining or improving protection for the internal circuitry (e.g., various electrical components) of the semiconductor device. For example, each diode may include a corresponding capacitance or capacitance value. Higher capacitance diodes may be undesirable for ESD protection circuits due to, at least, slower response times (e.g., requiring longer time to discharge excess energy during an ESD event), increased circuit loading (e.g., capacitive interactions with circuit impedance may degrade signal integrity, thereby impacting circuit performance), and relatively higher parasitic effects (e.g., reducing the diode's effectiveness in clamping voltage while generating additional ringing or oscillation in the circuit). Thus, relatively lower capacitance diodes are desirable for implementing ESD protection circuits and other types of circuits to at least minimize signal losses (e.g., for signals (e.g., current) flowing to diodes with relatively higher capacitance).

[0020] In some systems, smaller diodes (e.g., sometimes referred to as ESD diodes) may be introduced to reduce the capacitive loading in the circuit. However, simply implementing a smaller diode with lower capacitance may result in a higher clamping voltage during an ESD event, causing current leakage that may potentially damage or destroy internal circuits (e.g., internal core circuits or components of a semiconductor device). In such cases, despite the reduced capacitance of the circuit, the ESD protection design may not be able to protect the internal circuits during certain ESD events. Therefore, the systems and methods of the technical solutions discussed herein can use diodes with reduced capacitance to fabricate semiconductor devices without compromising ESD protection of the internal circuits.

[0021] Figure 1 Figures (e.g., schematic 100 and circuit diagram 118) illustrate an example circuit 101 (e.g., an ESD protection circuit) for ESD protection according to some embodiments. Schematic 100 includes at least example circuit 101 coupled to a power clamp 114 for ESD protection. Power clamp 114 may sometimes be referred to as a power-rail ESD clamp circuit. Power clamp 114 may be electrically connected / coupled in parallel to circuit 101. Power clamp 114 may include or correspond to a circuit configured to divert excess energy (e.g., electrical) from an ESD event away from protected circuitry (e.g., internal circuitry 110 of a semiconductor device) to prevent the excess energy from reaching and damaging internal circuitry 110. For example, during an ESD event, power clamp 114 may divert excess energy to various components of circuit 101. In some cases, components of circuit 101 may be part of a power clamp 114 configured to provide ESD protection to internal circuit 110 .

[0022] As shown, components of circuit 101 may include, but are not limited to, various diodes 102 a - 102 d (e.g., sometimes referred to as diodes 102 ), at least one resistor 112, and one or more silicon-controlled rectifiers (SCRs) 116 a - 116 b (e.g., sometimes referred to as SCRs 116 ). Components of circuit 101 (e.g., diodes 102 , resistors 112 , or SCRs 116 ) may be electrically coupled to at least one power source including VDD 104 (e.g., a positive power supply voltage) and VSS 108 (e.g., a negative power supply voltage or ground reference), at least one pad (PAD) 106 , and / or internal circuitry 110 of a semiconductor device.

[0023] Pads 106 may refer to physical contact areas on an integrated circuit (IC) package or die that are configured to connect the IC or semiconductor device to at least one external component. Internal circuit 110 may include or refer to circuitry or electrical components contained within a semiconductor device. Internal circuit 110 may include any electrical components that enable or allow the semiconductor device to operate or function as intended. The components of circuit 101 may be constructed or configured to prevent current leakage (e.g., excess energy) from entering or damaging internal circuit 110.

[0024] like Figure 1 As shown, circuit 101 includes four diodes 102 (e.g., D1 through D4) for an ESD protection design. Although four diodes 102 are present, additional or fewer diodes may be implemented to provide ESD protection. Each diode 102 enables current to flow in one direction, e.g., from the anode (e.g., labeled "A") to the cathode (e.g., labeled "C") of diode 102, while preventing current from flowing in the other direction (e.g., from the cathode to the anode). Diodes 102 may be formed or constructed from two types of semiconductor materials, including a P-type (e.g., a P semiconductor material) and an N-type (e.g., an N semiconductor material). The P semiconductor material may correspond to a positively doped region of diode 102, and the N semiconductor material may correspond to a negatively doped region of diode 102. These two types of semiconductor materials are coupled to create a pn junction at the boundary between the semiconductor materials, thereby forming diode 102 including an anode terminal and a cathode terminal. The anode terminal of the diode 102 is connected to a P-type semiconductor material, and the cathode terminal of the diode 102 is connected to an N-type semiconductor material, such as, but not limited to, a combination of Figures 4A to 4C The content described in at least one of .

[0025] To reduce the capacitance of diode 102 without compromising ESD protection of internal circuit 110, diode 102 can be divided into at least two sizes (e.g., with different capacitances), and diodes 102 of different sizes can be coupled in parallel. For example, diodes 102 of circuit 101 may include diodes D1 through D4. D1 through D4 may be referred to as a first diode 102a, a second diode 102b, a third diode 102c, and a fourth diode 102d, respectively. Each diode 102 may include a corresponding anode and cathode. For example, first diode 102a includes a first cathode and a first anode, second diode 102b includes a second cathode and a second anode, third diode 102c includes a third cathode and a third anode, and fourth diode 102d includes a fourth cathode and a fourth anode. The diodes 102 may be electrically coupled / connected to each other to provide multiple current paths to and / or away from the internal circuit 110 (eg, via D1 and / or D2 ), such as to prevent excessive current or current leakage into the internal circuit 110 .

[0026] The size of diode 102 can refer to its capacitance. As shown, first diode 102a and third diode 102c can be formed or configured to have higher capacitance (e.g., larger size) than second diode 102b and fourth diode 102d. For example, first diode 102a has a first size, second diode 102b has a second size, third diode 102c has a third size, and fourth diode 102d has a fourth size. The first size can be (e.g., substantially) larger than the second size. The third size can be (e.g., substantially) larger than the fourth size. For simplicity and to provide examples herein, the first and third sizes can be the same size (or approximately the same), and the second and fourth sizes can be the same size (or approximately the same). In this case, for example, the sizes of D1 and D3 can be substantially larger than the sizes of D2 and D4. In some other cases, the first size can be different from the third size and / or the second size can be different from the fourth size.

[0027] In some cases, the size of the diode 102 can be measured according to or based on the overlapped-depleted (OD) region of the diode 102. For example, the OD region ratio between the first size of the first diode 102a and the second size of the second diode 102b can be at least 9.5:0.5 to 7:3, among other values. The reference silicon ratio between the first diode 102a and the second diode 102b can be 8.5:1.5, among other values depending on the specifications.

[0028] To provide ESD protection for circuit 101, various diodes 102 may be connected to each other to allow excess current to flow away from internal circuit 110, as described below. The first cathode of first diode 102a may be floating (e.g., not connected to the rest of circuit 101). The first anode of first diode 102a may be electrically coupled to second diode 102b via a second anode, where the second cathode of second diode 102b may be coupled to VDD 104 (e.g., a first supply voltage or power source). In this configuration, first diode 102a may be coupled to second diode 102b via resistor 112. The first anode may also be coupled to the third cathode of third diode 102c at pad 106 (e.g., an input / output pin / port for connecting to an external component). The third anode of third diode 102c may be connected to VSS 108 (e.g., a second supply voltage or power source). Similar to the first diode 102a and the third diode 102c, the second anode of the second diode 102b can be coupled to the fourth cathode of the fourth diode 102d. The fourth anode of the fourth diode 102d can be connected to VSS 108 and the third anode of the third diode 102c. The first diode 102a can have a first size that is substantially larger than the second size of the second diode 102b.

[0029] In various configurations, the first anode and third cathode (e.g., via resistor 112), as well as the second anode and fourth cathode, can be connected to the internal circuit 110, allowing current to flow to the internal circuit 110 without potential excess energy or current leakage. For example, the first diode 102a and the third diode 102c can form a first discharge path. The second diode 102b and the fourth diode 102d can form a second discharge path. Additional discharge paths can be provided, for example, by forming or implementing additional diodes 102. Thus, by providing these discharge paths, the circuit 101 can prevent discharge current from flowing to the internal circuit 110 during an ESD event. The design of the circuit 101 can enable a reduction in capacitance, for example, by at least 30% compared to certain other devices, without compromising ESD protection.

[0030] One or more SCRs 116 may be formed or implemented in circuit 101 to provide one or more discharge paths during an ESD event. Although the first cathode of first diode 102a is floating (e.g., potentially reducing the ESD discharge path), the one or more SCRs 116 may be embedded in the corresponding diode or diodes 102 to conduct ESD current during an ESD event. Each SCR 116 is a three-terminal device (e.g., a four-layer solid-state device) composed of four semiconductor layers including PNPN layers. The three terminals include an anode, a cathode, and a gate (e.g., labeled "G"), each formed at a corresponding junction of the PNPN layers (e.g., three PN junctions). SCR 116 may operate similarly to a rectifier, allowing current to flow in one direction, such as from anode to cathode. During operation, SCR 116 may operate as an open circuit until a trigger voltage (or breakdown voltage) is applied to or received by SCR 116. For example, a trigger voltage can be predetermined based on the specifications of the semiconductor device to prevent damage to the internal circuit 110. A trigger voltage can be applied when current (e.g., excess current) flows through the resistor 112, causing a voltage drop across the resistor 112. Resistor 112 implemented in circuit 101 can include a predetermined resistance based on the specifications, such as between 0.1 ohms and 0.5 ohms, among other values. When a trigger voltage is applied between the anode and cathode of the SCR 116 (e.g., at the gate terminal), the SCR 116 can enter a conductive state, thereby forming a path (e.g., a discharge path) that allows current to flow from the anode to the cathode. Thus, during an ESD event, the voltage from the ESD event can trigger the SCR 116 to enter a conductive state, allowing excess current to flow through the discharge path rather than to the internal circuit 110, thereby preventing potential damage.

[0031] like Figure 1As shown, circuit 101 may include a first SCR 116a and a second SCR 116b. The anode of first SCR 116a may be connected to VSS 108. The gate of first SCR 116a may be coupled to the first anode of first diode 102a. The cathode of first SCR 116a may be coupled to the first cathode of first diode 102a. The anode of second SCR 116b may be connected to VSS 108. The gate of second SCR 116b may be coupled to the second anode of second diode 102b. The cathode of second SCR 116b may be coupled to the second cathode of second diode 102b. First SCR 116a and second SCR 116b may be triggered based on the voltage applied to their respective gates. The trigger voltage of the second SCR 116b may be lower than the trigger voltage of the first SCR 116a because the capacitance associated with the second diode 102b is smaller than that of the first diode 102a, wherein the semiconductor material of the respective diode 102 is partially used to form the respective SCR 116. In this case, the second SCR 116b may be triggered before the first SCR 116a. The formation and / or operation of the SCR 116 may be combined with at least Figures 5 to 6D By at least Figure 1 The layout implements diode 102 and SCR 116 with lower capacitance, which can reduce / minimize the total capacitance of the ESD protection circuit (eg, circuit 101 ) and the voltage clamp compared to some other systems.

[0032] Circuit diagram 118 may correspond to schematic diagram 100 and include at least the various components of circuit 101. Circuit diagram 118 may include capacitors 120a through 120d (e.g., sometimes referred to as capacitors 120) representing the capacitance of the corresponding diodes 102. For example, first capacitor 120a may include a first capacitance corresponding to the capacitance of first diode 102a. Second capacitor 120b may include a second capacitance corresponding to the capacitance of second diode 102b. Third capacitor 120c may include a third capacitance corresponding to the capacitance of third diode 102c. Fourth capacitor 120d may include a fourth capacitance corresponding to the capacitance of fourth diode 102d. For example, first capacitor 120a (e.g., the capacitance of first diode 102a) may not be visible because the first cathode is floating.

[0033] Figure 2 During an ESD event, according to some embodiments Figure 1Schematic diagram 200 illustrates various components of circuit 101, including at least diode 102, power supplies (e.g., VDD 104 and VSS 108), pads 106 (e.g., input / output pins), paths to internal circuit 110, resistor 112, and SCR 116. The arrangement or coupling of these components may be similar to that of FIG. Figure 1 For example, the first cathode may be floating, the first anode may be coupled / connected to the second anode, the second cathode may be connected to VDD 104, the first SCR 116a may be associated with the first diode 102a, the second SCR 116b may be associated with the second diode 102b, etc.

[0034] During an ESD event, excessive current may flow from pad 106 (e.g., an input / output pin) through various components of circuit 101. The excessive current may flow through resistor 112, where the voltage applied at the terminals of resistor 112 may correspond to the voltage applied at the gate of SCR 116. In this case, the voltage applied due to the excessive current may trigger SCR 116 to activate corresponding discharge paths, including a first discharge path from the anode to the cathode of first SCR 116a and a second discharge path from the anode to the cathode of second SCR 116b. Second SCR 116b may activate its discharge path before first SCR 116a. In response to providing a discharge path, at least a portion of the excess current (e.g., current 204) may flow through the second discharge path, and another portion of the excess current (e.g., current 202) may flow through the first discharge path, such as from the pad 106 (e.g., an input / output pin) to VSS 108 (e.g., a second supply voltage), and be directed away from the internal circuit 110 to prevent damage to other electrical components.

[0035] Figure 3 shows similarity to that according to some embodiments Figure 1Another example circuit 300 for ESD protection is shown. Example circuit 300 may include components similar to example circuit 101. For example, circuit 300 may include various diodes 302a-302n (e.g., sometimes referred to as diodes 302), power supplies (e.g., VDD 104 and VSS 108), pad 106, paths to internal circuit 110, various resistors 304a-304b (e.g., sometimes referred to as resistors 304), and various SCRs 306a-306n (e.g., sometimes referred to as SCRs 306). Diode 302 may correspond to or be similar to diode 102, e.g., including similar features or functions. Resistor 304 may correspond to or be similar to resistor 112. Resistor 304 may include similar or different resistances. SCR 306 may correspond to or be similar to SCR 116.

[0036] In some embodiments, circuit 300 for ESD protection may include more than four diodes, such as eight diodes (e.g., D1 through D8, respectively). The arrangement of the components of circuit 300 may be similar to circuit 101. For example, the anodes of D1 through D4 may be coupled to one another. The cathodes of D1 through D3 may be floating, and the cathode of D4 (e.g., similar to the second cathode of second diode 102b) may be connected to VDD 104 (e.g., the first supply voltage). In some cases, at least one other cathode of at least one of D1 through D3 may be connected to VDD 104. The cathodes of D5 through D8 may be coupled to the anodes of D1 through D4, respectively. The anodes of D5 through D8 may be connected to VSS 108 (e.g., the second supply voltage). The size (e.g., capacitance) of D1 and D5 may be substantially larger than that of the other diodes 302, including at least one of D2 through D4 and / or D6 through D8 (e.g., the second size). For purposes of providing an example, D1 and D5 may comprise a first size, and D2-D4 and D6-D8 may comprise a second size, although the diodes 302 may be configured to have different sizes. The SCRs 306 may be associated with or coupled to respective diodes 302, for example, SCRs 306a-306n may be coupled to D1-Dn, respectively.

[0037] In some other configurations, more or fewer diodes 302 and / or SCRs 306 may be implemented for the ESD protection circuit. For example, additional diodes 302 may be implemented with a size substantially smaller than the first size. In some cases, additional diodes 302 may be implemented with a size larger than or similar to the first size.

[0038] Figures 4A to 4C According to some embodiments, a method for forming Figure 1Example structures 400 - 404 of diodes (eg, diode 102 ) implemented in example circuit 101 are shown. Figures 4A to 4C The illustrated structures 400-404 may represent cross-sectional views of diode 102, illustrating the various layers that form diode 102. For example, the formation of each diode 102 may include constructing a pn junction between two different types of semiconductor materials, such as a P-type (e.g., positively doped) and an N-type (e.g., negatively doped) region. The semiconductor material may be composed of, but is not limited to, at least one of silicon, germanium, gallium nitride, and the like. The semiconductor material may be positively doped to form a P-type region, or negatively doped to form an N-type region. The terminals of diode 102 (e.g., anode and cathode) may correspond to the P-type and N-type regions, respectively.

[0039] Structure 400 can be fabricated to form an N+ / PW diode. For example, a P-type substrate (Psub) can be deposited as a base (or first) layer. The P-type substrate may refer to a substrate having a first conductivity (e.g., P-type). A P-type semiconductor material (e.g., a P-well) can be formed above the P-type substrate. Furthermore, a P-type region (P+) and an N-type region (N+) (e.g., positively doped and negatively doped semiconductor materials, respectively) can be formed above the P-well (P-well, PW), separated by at least one isolation layer or material (e.g., silicon dioxide, silicon nitride, shallow trench isolation, etc.). In this case, a pn junction can be formed between the P-well and the N-type region, thereby forming an N+ / PW diode. The N+ / PW diode can correspond to at least one of the third diode 102c and / or the fourth diode 102d.

[0040] Structure 402 can be fabricated to form a P+ / PW diode. For example, similar to structure 400, a P-type substrate can be formed as a base layer, and a P-type region and an N-type region can be formed above a well layer or region. Structure 402 can be formed using an N-well (NW) instead of a P-well, thereby forming a pn junction between the P-type region and the N-well layer to form a P+ / PW diode. The P+ / PW diode can correspond to at least one of the first diode 102a (e.g., if the first cathode is floating) or the second diode 102b.

[0041] Structure 404 can be fabricated to form an N+ / Psub diode. In this case, no well layer (e.g., N-well or P-well) may be deposited or formed over the P-type substrate. Consequently, a pn junction can be formed between the N-type region and the P-type substrate to form the N+ / Psub diode. Similar to structure 400, the N+ / Psub diode can correspond to at least one of the third diode 102c and / or the fourth diode 102d. In some configurations, the substrate can be fabricated as an N-type substrate. Although not illustrated, various etching, masking, or other fabrication processes can be performed to form diode 102 of structures 400-404 or other components discussed herein.

[0042] Figure 5 Shown according to some embodiments Figure 1 An example layout 500 of example circuit 101 is shown. Example layout 500 may correspond to or represent a top view of semiconductor material fabricated to form at least a portion of a component of circuit 101. Example layout 500 may include various structures 502-516 forming a semiconductor device. Structures 502-516 may be fabricated or formed above, within, or on a base substrate (e.g., a substrate having a first conductivity (e.g., P-type)). For example, structure 502 may include an OD region (e.g., a contact region) formed to contact or connect to VSS (e.g., VSS 108 or a second supply voltage). The OD region of structure 502 may be composed of at least P-type semiconductor material. This OD region may be disposed above, within, or above a P-well layer. Structure 504 may include an OD region connected to VSS. Structure 504 may be composed of at least N-type semiconductor material disposed above the P-well layer. Structure 506 may include an OD region composed of P-type semiconductor material. This OD region can be disposed above an N-well layer (e.g., a first well surrounded by the substrate and having a second conductivity (e.g., N-type)), thereby forming a pn junction (e.g., a first contact region surrounded by the first well and having a first conductivity) of diode 102. The pn junction formed by structure 506 can be associated with D1 (e.g., the first diode 102a of circuit 101).

[0043] In other examples, structure 508 may include an OD region composed of an N-type semiconductor material disposed above a P-well layer. The OD regions of structures 506 and 508 may be connected to input / output pins (e.g., pad 106). Similar to structure 502, structure 510 may include an OD region composed of a P-type semiconductor material disposed above a P-well layer. Structures 508 and 510 may be (e.g., electrically) coupled to form a pn junction. In this case, the pn junction between structures 508 and 510 may be associated with D3 (e.g., the third diode 102c of circuit 101). Structure 512 may include an OD region composed of an N-type semiconductor material disposed above a P-well layer. This OD region may be connected to internal circuit 110. In this case, structure 510 may be coupled to structure 512 to form a pn junction associated with D4 (e.g., the fourth diode 102d of circuit 101). Structures 514 and 516 may include corresponding OD regions composed of P-type and N-type semiconductor materials, respectively, disposed above an N-well layer (e.g., a second well surrounded by the substrate and having a second conductivity (e.g., N-type)). The OD region of structure 514 may be connected to internal circuit 110. The OD region of structure 516 may be connected to VDD (e.g., VDD 104 or a first supply voltage). Structures 514 and 516 may form a pn junction associated with D2 (e.g., second diode 102b). For example, structure 514 may form a second contact region surrounded by the second well and having a first conductivity. Structure 516 may form a third contact region surrounded by the second well and having a second conductivity. The second contact region and the second well having the third contact region may form diode 102 (e.g., second diode 102b). Although one OD region is shown for each of the structures 502 - 516 of the example layout 500 , multiple OD regions (eg, multiple parallel ODs) may be implemented for at least one of the structures 502 - 516 .

[0044] In some embodiments, structure 504 may form a fourth contact region, which is surrounded by the substrate, disposed on a first lateral side (e.g., above, relative to a top view) of the first and second wells (e.g., the N-type wells of structures 506, 514, and 516), and has the second conductivity. Structure 510 may form a fifth contact region, which is surrounded by the substrate, disposed opposite the fourth contact region relative to the first and second wells (e.g., below structures 508, 512, and 516), and has the first conductivity (e.g., P-type). Structure 508 may form a sixth contact region, which is surrounded by the substrate, disposed on a second lateral side (e.g., below, relative to a top view) of the first well, and has the second conductivity. Structure 510 may form a seventh contact region, which is surrounded by the substrate, disposed adjacent to the sixth contact region relative to the first well, and has the first conductivity.

[0045] In some embodiments, an SCR can be formed between a P-type structure and an N-type structure, such as when a PNPN layer (e.g., P+, N-type layer, P-type layer, and N+) is present. For example, an exemplary cross-sectional view 518 of structures 504 and 508 is shown. Cross-sectional view 518 includes at least a P-type region 520 (P+), a P-type layer 522 (e.g., a P-well or P-substrate), an N-type layer 524 (e.g., in some cases, an N-well or N-substrate), and an N-type region 526 (N+). These regions and / or layers can form a PNPN layer with three junctions to form an SCR, such as the first SCR 116a at D1 between structures 504 and 506. Similarly, a second SCR 116b at D2 can be formed between structures 504 and 514.

[0046] The dimensions of structures 502-516 may be predetermined or configured for fabrication of a semiconductor device (or circuit 101). For example, the length of structures 512-516 may be less than or equal to 10 microns. The length of structures 506-508 may be less than or equal to 30 microns. The length of structures 502-504 and 510 may be less than or equal to 40 microns. The width of structures 502-516 may be less than or equal to 0.9 microns. The spacing or gap between structure 506 and structure 514, between structure 512 and structure 516, and between structure 508 and structure 512 may be less than or equal to 2 microns. The spacing between each of structures 508, 512, 516 and each of structures 506 and 514 may be less than or equal to 0.6 microns. The spacing between structure 502 and structure 504, the spacing between structure 504 and each of structures 506 and 514, and the spacing between structure 510 and each of structures 508, 512, and 516 can be less than or equal to 0.75 microns. Other dimensions can be used for the width, length, height, and / or spacing of / between structures 502-516 and other structures of the semiconductor device.

[0047] 6A to 6D Showing the Figure 5 Example positioning of the N-well associated with the example layouts is shown. In example layouts 600 and 602, structure 512 can be removed from circuit 101 (e.g., to form D4 or fourth diode 102d). Therefore, fourth diode 102d can be omitted from circuit 101 having example layouts 600 and 602. In example layout 600, structures 514 and 516 associated with the N-well can be positioned to the right of structures 506 and 508. In example layout 602, structures 514 and 516 associated with the N-well can be positioned to the left of structures 506 and 508.

[0048] For example, in example layouts 604 and 606, circuit 101 may include structure 512 to form fourth diode 102d. Similar to example layout 600, example layout 604 may include structures 514 and 516 positioned to the right of structures 506, 508, and 512. Similar to example layout 602, example layout 606 may include structures 514 and 516 positioned to the left of structures 506, 508, and 512. In some cases, the length of structure 508 in example layouts 600 and 602 may be relatively longer than the length of structure 508 in example layouts 604 and 606 due to the absence of structure 512. In some other cases, the length of structure 508 may be the same for example layouts 600 through 606. The positioning of the N-well region may vary in other portions of the circuit layout, not limited to those described herein.

[0049] 7A to 7C shows similarity to that according to some embodiments Figure 1 The example circuit 101 is shown as an example circuit layout 700 to 704 having six diodes (eg, D1 to D6) for ESD protection. The example layouts 700 to 704 may include circuits with Figures 5 to 6D , such as structures 502 through 516. In example layouts 700 through 704, structures 514 and 516 forming a pn junction can be associated with D3 (e.g., the third diode of the six-diode circuit). The pn junction between structures 508 and 510 can form D4 in the six-diode circuit. The pn junction between structures 510 and 512 can form D6 in the six-diode circuit.

[0050] Example layouts 700-704 may include additional structures to form additional diodes (e.g., in this case, a total of six diodes 102), including at least structures 706 and 708. For example, structure 706 may include an OD region composed of P-type semiconductor material disposed above, within, or on an N-well. The P-type semiconductor material and the N-well may form a pn junction, thereby forming a diode. In this case, the pn junction of structure 706 may form D2 in the six-diode circuit. Structure 708 may include an OD region composed of N-type semiconductor material disposed above the P-well (or P-substrate). The pn junction between the P-type material of structure 510 and the N-type material of structure 708 may form D5 in the six-diode circuit.

[0051] Similar to example layout 500, example layouts 700-704 may include SCRs formed between structures 504, 506 (e.g., an SCR associated with D1) and between structures 514, 504 (e.g., an SCR associated with D3). Furthermore, example layouts 700-704 may include an additional SCR associated with D2. This SCR may be formed between the P-type and N-type structures of structures 504, 706.

[0052] The positions of one or more structures of the example circuits may be rearranged or reconfigured, such as shown but not limited to example layouts 700 to 704. For example, in example layout 700, structures 512, 706, 708 may be located between structures 506, 508, 514, 516. Structures 506, 508 may be located to the left of structures 512, 706, 708. Structures 514, 516 (e.g., N-wells) may be located to the right of structures 512, 706, 708. Structure 708 may be located to the left of structure 512.

[0053] In another example, the positions of structures 506, 508, 512 to 516, 706, 708 can be swapped laterally in example layout 702. As shown, structures 506, 508 can be located to the right of structures 512, 706, 708. Structures 514, 516 can be located to the left of structures 512, 706, 708. Structure 708 can be located to the right of structure 512. In other examples, in example layout 704, structures 506, 508 can be rearranged or moved to the left of structures 512 to 516, 706, 708 as positioned in example layout 702. Thus, as shown, structures 514, 516 can be located between structures 506, 508 (e.g., to the left) and structures 512, 706, 708 (e.g., to the right). Other arrangements of structures may be similarly applied to form circuit 101 , six diode circuits, and other circuits for ESD protection.

[0054] Figure 8 A method for positioning according to some embodiments is shown. Figure 1 The example layout 800 of the resistor 112 of the example circuit is shown. The example layout 800 may include various structures (eg, structures 502 to 516) and arrangements similar to the example layouts 500 and 606, such as incorporating, but not limited to, at least Figures 5 to 6D In this case, example layout 800 may include a metal structure 802 corresponding to resistor 112 of circuit 101. Metal structure 802 may be coupled to at least one structure corresponding to or associated with a terminal of diode 102.

[0055] For example, metal structure 802 may be coupled to the P-type material of structure 506, which may correspond to the first anode of first diode 102a. Metal structure 802 may be coupled to the P-type material of structure 514, which may correspond to the second anode of second diode 102b. Metal structure 802 may be coupled to the N-type material of structure 508, which may correspond to the third cathode of third diode 102c. Metal structure 802 may be coupled to the N-type material of structure 512, which may correspond to the fourth cathode of fourth diode 102d. Thus, the first anode, second anode, third cathode, and fourth cathode may be electrically connected via metal structure 802 (e.g., resistor 112).

[0056] In some embodiments, the metal structure 802 of resistor 112 may be composed of a different material than the metal structure that couples resistor 112 to one or more structures within circuit 101. In some other embodiments, the metal structure 802 of resistor 112 may be composed of the same material as the metal structure that couples resistor 112 to one or more structures within circuit 101. In some arrangements, the various structures 502 to 516 of circuit 101 may be formed within a single layer of a semiconductor device. In some other arrangements, the various structures 502 to 516 of circuit 101 may be formed on multiple layers of a semiconductor device. Structures 502 to 516 may be included in a front-end-of-line (FEOL) fabrication process (e.g., an initial fabrication stage) or within a substrate. Metal structure 802 may be included in a back-end-of-line (BEOL) fabrication process (e.g., a later fabrication stage) to provide interconnects between various layers or structures. Metal structure 802 forming resistor 112 may be fabricated in a different layer of the semiconductor device than structures 502 through 516. In some cases, metal structure 802 may be fabricated in the same layer as structures 502 through 516. Metal structure 802 may be connected to one or more structures, such as structures 506, 508, 512, 514, through corresponding via structures.

[0057] Figures 9A to 9C Shown are some embodiments of the Figure 1Example layouts 900 through 904 are shown for resistor 112 of example circuit 101. Example layouts 900 through 904 may provide example locations for metal structures 802 corresponding to resistor 112 to form connections between diodes 102 (e.g., between first diode 102a through fourth diode 102d). For example, example layout 900 may include structures 502 through 516 arranged similarly to example layout 800. Compared to example layout 800, example layout 900 may include fewer metal structures 802 while maintaining connections to at least structures 506, 508, 512, and 514 associated with respective terminals of diodes 102.

[0058] In another example, in example layout 902, structure 512 may be moved or formed to the right of structure 508. As shown in this case, the length of metal structure 802 may be extended to couple with structures 506, 508, 512, and 514. In other examples, example layout 904 may include structures 502 through 516 positioned similarly to example layout 902. In this case, metal structure 802 may be divided into two portions formed between a first pair of structures 506, 514 (e.g., corresponding to first diode 102a and second diode 102b) and a second pair of structures 508, 512 (e.g., corresponding to third diode 102c and fourth diode 102d). In this manner, first diode 102a and second diode 102b may be connected via resistor 112. Third diode 102c and fourth diode 102d may be connected via resistor 112 (or a second resistor). The first diode 102a and the second diode 102b may be connected to the third diode 102c and the fourth diode 102d without the resistor 112. Although the first diode 102a and the second diode 102b may be connected to the third diode 102c and the fourth diode 102d without the resistor 112, the diodes 102 may still be connected via other via structures, such as, but not limited to, the resistor 112.

[0059] Figure 10 is an example flow chart of a method 1000 for forming a semiconductor device according to some embodiments. It should be noted that the method 1000 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that Figure 10 The order of the operations of method 1000 may be changed. Figure 10 Additional operations are provided before, during, and after the method 1000, and some other operations may be only briefly described herein. Such a semiconductor device manufactured by the method 1000 may include one or more components, such as those described above with respect to Figures 1 to 9C Therefore, as an illustrative example, the operations of method 1000 will sometimes be combined with Figures 1 to 9C To discuss.

[0060] At operation 1002, method 1000 includes forming a first diode (eg, D1 or at least Figure 1 In various embodiments, in addition to other structures of the semiconductor device, the formation of the diode may include various manufacturing processes / procedures / operations, such as, but not limited to, combining Figures 1 to 9C To form the first diode and the other diodes, a substrate having a first conductivity (e.g., P-type) may be deposited or provided as a base substrate. A first well may be deposited on or in a portion of the substrate (e.g., an etched portion). The first well may have a second conductivity (e.g., N-type). A first contact region (e.g., an OD region) may be deposited on or in the first well, whereby the first contact region is surrounded by the first well. The first contact region may have a first conductivity. With these materials, the first contact region and the first well (e.g., for example, at least Figure 5 A first diode (e.g., a P+ / NW (pad)) can be formed. The first diode can have a first cathode and a first anode. For example, P-type material (e.g., first conductivity) and N-type material (e.g., second conductivity) used to form the diode can be associated with the anode and cathode of the diode, respectively. The first cathode (e.g., first well) can be floating. The first anode (e.g., first contact region) can be coupled to an input / output pin (e.g., pad).

[0061] At operation 1004, method 1000 includes forming a second diode (eg, D2 or at least Figure 1 To form the second diode 102b, a second well may be deposited and the second well may be surrounded by the substrate. The second well may have a second conductivity (e.g., N-type) similar to the first well. A second contact region may be deposited above or within the second well such that the second contact region is surrounded by the second well. The second contact region may have a first conductivity (e.g., P-type). Similarly, a third contact region may be deposited within the second well and the third contact region is surrounded within the second well. The third contact region may have a second conductivity. The second contact region and the third contact region (e.g., Figure 5 N+ / NW(VDD)) of the second well (e.g., Figure 5 A second diode may be formed by connecting a P+ / NW (leading to the inside) to a second contact region. The second diode may include a second anode (e.g., associated with the second contact region) and a second cathode (e.g., associated with the third contact region). The third contact region (e.g., the second cathode) may be coupled to a first supply voltage (e.g., VDD).

[0062] At operation 1006, method 1000 includes coupling the first diode to the second diode. For example, the second contact region (e.g., the second anode of the second diode) may be connected to the first diode via a metal resistor disposed above the substrate (e.g., a resistor coupling the first anode to the second anode). Figure 1 A resistor 112 (e.g., a resistor 112) is coupled to a first contact region (e.g., a first anode of a first diode). The first diode has a first size and the second diode has a second size. The first size can be substantially greater than the second size. For example, the ratio of the first size to the second size can be between approximately 9.5 / 0.5 and approximately 7 / 3, among other values.

[0063] In some cases, size can refer to the length of the contact regions associated with the first diode and the second diode. For example, the first contact region can be a first length (e.g., Figure 5 The second contact area may extend to a second length (e.g., Figure 5 The first length may be substantially greater than the second length, for example, similar to the ratio of the first size to the second size.

[0064] In some embodiments, a fourth contact region (e.g., at least Figure 5 The structure 504) and the fourth contact region is surrounded by the substrate. The first lateral side of the first well and the second well (for example, Figure 5 A fourth contact region is disposed on a first lateral side of the structures 506, 514, 516. The fourth contact region may have a second conductivity. In some cases, the fourth contact region may be connected to a second supply voltage (e.g., VSS). In some embodiments, a fifth contact region may be deposited and surrounded by the substrate. The fifth contact region may be disposed opposite the fourth contact region relative to the first well and the second well. The fifth contact region may have a first conductivity. For example, the fifth contact region may be connected to at least Figure 5 In some cases, the fifth contact region can be connected to VSS.

[0065] At operation 1008, method 1000 includes forming a third diode (eg, Figure 1 D3 or the third diode 102c). To form the third diode, a sixth contact region may be deposited and surrounded by the substrate. Figure 5 A sixth contact region is provided in the structure 508. The sixth contact region may have a second conductivity. In addition, a seventh contact region may be deposited and surrounded by the substrate. For example, at least Figure 5In the structure 510, a seventh contact region may be provided adjacent to the sixth contact region relative to the first well. The seventh contact region may have a first conductivity. The sixth contact region and the substrate having the seventh contact region may form a third diode. The third diode may include a third anode (e.g., associated with the seventh contact region) and a third cathode (e.g., associated with the sixth contact region). The sixth contact region may be coupled to an input / output pin (e.g., Figure 1 The seventh contact region may be coupled to a second supply voltage (eg, VSS).

[0066] At operation 1010, method 1000 includes connecting a third diode to the first diode. The third cathode may be connected or coupled to the first anode at an input / output pin.

[0067] At operation 1012, method 1000 includes coupling a second diode to a circuit (eg, Figure 1 Internal circuit 110 of the input / output pin. For example, the second contact region (e.g., the second anode of the second diode) can be coupled to a circuit powered by a first supply voltage and a second supply voltage (e.g., VSS). At least the first to third diodes can be operable to function as an ESD protection circuit configured to provide multiple discharge paths from the input / output pin to the second supply voltage, thereby preventing excessive current from flowing into the circuit.

[0068] In some embodiments, the semiconductor device may include additional diodes, such as a fourth diode, a fifth diode, a sixth diode, etc. For example, the method 1000 may include forming a fourth diode (eg, D4 or D5) having a fourth cathode and a fourth anode. Figure 1 To form the fourth diode, an eighth contact region may be deposited and surrounded by the substrate. The eighth contact region may have a second conductivity (e.g., N-type). The eighth contact region may be formed on the second lateral side of the first well (e.g., at least at the second side of the first well). Figure 5 An eighth contact region is provided in structure 512. For example, the eighth contact region may be perpendicular to the sixth contact region and the first well. The eighth contact region and the substrate having the seventh contact region may form a fourth diode. The seventh contact region may be associated with a fourth anode. The eighth contact region may be associated with a fourth cathode. The fourth cathode may be connected to the second anode of the second diode. The fourth anode may be connected to a second supply voltage. In this case, the fourth diode may provide another discharge path for ESD protection.

[0069] The third diode may have a third size, and the fourth diode may have a fourth size. The third size may be substantially larger than the fourth size. In some cases, the third size may be similar to or different from the first size. In some cases, the fourth size may be similar to or different from the second size.

[0070] The semiconductor device may include a fifth diode (eg Figure 3 D2), where the second diode can be connected to Figure 3 The fifth diode may have a fifth cathode and a fifth anode. The fifth cathode may be floating, and the fifth anode is coupled to the input / output pin and to the second anode. Figure 3 In the embodiment, the fifth anode can be coupled to the input / output pin and the second anode respectively through different metal resistors (eg, resistor 304b and resistor 304a).

[0071] In various configurations, one or more SCRs may be formed or included in a semiconductor device. For example, a first well and a first contact region disposed therein (e.g., Figure 5 ) may be adjacent to a fourth contact region (eg, at least Figure 5 A first SCR (e.g., SCR 116a associated with first diode 102a) is formed to conduct current through a first contact region, a first well, a substrate, and a fourth contact region. The first contact region, the first well, the substrate, and the fourth contact region can each form a PNPN layer including three junctions associated with the three terminals of the first SCR.

[0072] In another example, the second well and the second contact region disposed therein (eg, with at least Figure 5 The structure 514 (associated with the structure 514) can be disposed proximate to the fourth contact region, forming a second SCR to conduct current through the second contact region, the second well, the substrate, and the fourth contact region. The second contact region, the second well, the substrate, and the fourth contact region can each form a PNPN layer including three junctions associated with the three terminals of the second SCR. In some cases, the second SCR can be configured to be formed before the first SCR is formed.

[0073] The first SCR can be configured to provide a first discharge path from a first contact area coupled to the input / output pin to VSS. The second SCR can be configured to provide a second discharge path from a second contact area coupled to the input / output pin to VSS. In some cases, the second SCR can be triggered (e.g., via a trigger voltage) before triggering the first SCR to enable the corresponding discharge path during an ESD event.

[0074] Figure 11 1 is an example flow chart of a method 1100 for fabricating a semiconductor device according to some embodiments. It should be noted that the method 1100 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that Figure 11 The order of the operations of method 1100 may be changed. Figure 11Additional operations are provided before, during, and after the method 1100, and some other operations may be only briefly described herein. Such a semiconductor device manufactured by the method 1100 may include one or more components, such as those described above with respect to Figures 1 to 9C Therefore, as an illustrative example, the operations of method 1000 will sometimes be combined with Figures 1 to 9C To discuss.

[0075] Briefly, method 1100 begins with operation 1102 of providing a substrate. The substrate may have a first conductivity (e.g., P-type or N-type, depending on the configuration). For example, the substrate may be a P-type substrate on which a base layer or first layer is deposited. In another example, the substrate may be an N-type substrate on which a base layer or first layer is deposited. The substrate may be deposited as a base layer or first layer using at least one suitable deposition technique, such as, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), chemical solution deposition (CSD), or epitaxial growth. Forming the materials or structures described herein may be performed using at least one suitable deposition technique.

[0076] An insulating material (such as, but not limited to, silicon dioxide (SiO2)) may be deposited over the substrate to form an insulating layer. A masking material, such as, but not limited to, silicon nitride (Si3N4), may be deposited over the insulating layer to form a shielding layer. The insulating layer and the shielding layer may be deposited to respective predetermined thicknesses. Subsequently, an etching process may be performed using the shielding layer to form trenches (or defined patterns) for isolating devices, such as shallow trench isolation (STI) between devices (e.g., active devices or contact areas). The etching process may include at least one suitable etching technique, such as, but not limited to, plasma etching, wet etching, laser ablation, reactive ion etching (RIE), chemical mechanical polishing (CMP), or dry etching. In some cases, after depositing the material, an etching process (such as, but not limited to, plasma etching) may be performed to remove excess or exposed material. The trenches may be filled with an insulating material, such as a field oxide (e.g., SiO2) used to isolate the contact areas. The filled trenches may be referred to as STI regions.

[0077] Next, the method 1100 proceeds to operation 1104 of forming a plurality of wells along the main surface of the substrate. Figures 4A to 9C The layout shown is used to determine the corresponding position and size of the well. For example, depending on the type of semiconductor device, the well may include P-type semiconductor material (e.g., P-well) or N-type semiconductor material (e.g., N-well). For example, a P-well may be formed above the substrate to form, for example, an N+ / PW diode. In another example, an N-well may be formed above the substrate to form, for example, a P+ / NW diode. In some embodiments, semiconductor material for forming a well may not be deposited above the substrate, for example, to form an N+ / Psub diode.

[0078] For example, to form a well, dopant ions may be implanted (e.g., ion implantation) into silicon to produce desired electrical properties, turning a particular region into an N-type material (e.g., an N-well) or a P-type material (e.g., a P-well). Figure 5 For example, ion implantation can be used to form multiple wells in regions of the device, such as a first well (e.g., associated with structure 506) and a second well (e.g., associated with structures 514 and 516) having a second conductivity different from that of the substrate. For example, if the first conductivity is P-type, the second conductivity can be N-type. In some embodiments, the implantation can be performed to adjust the threshold voltage of the device.

[0079] Next, method 1100 proceeds to operations 1106 through 1110 for forming a plurality of contact regions (including, but not limited to, first through seventh contact regions) along the major surface of the substrate. To form the respective contact regions, ion implantation may be performed at the source or drain regions of the device, for example, to form a P-type contact region or an N-type contact region. By implanting ions into the source and drain regions, gates for corresponding transistors may be formed, for example, an N+ polysilicon gate for an N-metal oxide semiconductor (NMOS) transistor and a P+ polysilicon gate for a P-metal oxide semiconductor (PMOS) transistor, respectively. In some cases, one or more spacers of a predetermined thickness or size may be deposited, for example, to protect the contact regions beneath the gates from dopants implanted during source and drain formation.

[0080] In various embodiments, in addition to other materials or structures of the semiconductor device (eg, diode), the corresponding positions and sizes of the contact regions may be based on Figures 4A to 9C At least one of but not limited to Figures 4A to 9CThe layout shown is determined. For example, the contact region (e.g., OD region) may include at least one of a P-type semiconductor material (e.g., a P-type region) or an N-type semiconductor material (e.g., an N-type region). One or more of the contact regions may be formed to contact or connect to VSS (e.g., the second supply voltage), an input / output pin (e.g., a pad), or VDD (e.g., the first supply voltage). For example, a P-type region may be formed above a P-well and in contact with VSS, and an N-type region may be formed above the P-well and in contact with the pad. A pn junction may be formed between the P-well and the N-type region, thereby forming an N+ / PW diode. In another example, an N-type region may be formed above an N-well and in contact with VDD, and a P-type region may be formed above an N-well and in contact with the pad. A pn junction may be formed between the P-type region and the N-well, thereby forming a P+ / NW diode. In the case where no well is formed on the substrate, a P-type region and an N-type region may be formed on the substrate, wherein the P-type region may contact VSS and the N-type region may contact the pad. In this case, the substrate (e.g., P-type) and the N-type region may form a pn junction, thereby forming an N+ / Psub diode. Figures 4A to 9C The formation of the substrate, well, and contact region is described using at least one of the following, although other configurations or arrangements may be provided to form the pn junction, but are not limited to those described herein.

[0081] like Figure 5 As shown, but not limited to Figure 5 For example, first to seventh contact regions may be formed for the semiconductor device. Corresponding to operation 1106, the first contact region may be formed using the techniques discussed above. The first contact region may be surrounded by the first well (e.g., deposited above or within the first well). The first contact region may have a first conductivity. In this case, for example, the first contact region may be associated with or correspond to a P+ / NW (pad), for example, in combination with at least Figure 5 shown.

[0082] Regarding the above example and corresponding to operation 1108, a second contact region and a third contact region may be formed for the semiconductor device. The second contact region and the third contact region may be surrounded by a second well. The second contact region may have a first conductivity, and the third contact region may have a second conductivity. For example, the second contact region may correspond to P+ / NW (towards the inside), and the third contact region may correspond to N+ / NW (VDD), for example, in combination with at least Figure 5 shown.

[0083] Regarding the above example and corresponding to operation 1110, a fourth contact region, a fifth contact region, a sixth contact region, and a seventh contact region may be formed for the semiconductor device. The fourth contact region, the fifth contact region, the sixth contact region, and the seventh contact region may be surrounded by the substrate (e.g., having the first conductivity). For example, a fourth contact region having the second conductivity may be provided on the first lateral side of the first well and the second well, e.g., corresponding to the combination of at least Figure 5 The N+ / PW(VSS) described above) may be provided with a fifth contact region having a first conductivity relative to the first well and the second well and the fourth contact region, for example, corresponding to the combination of at least Figure 5 A sixth contact region having a second conductivity may be provided on a second lateral side of the first well, for example corresponding to a contact region incorporating at least Figure 5 A seventh contact region having a first conductivity may be provided adjacent to the sixth contact region relative to the first well, for example corresponding to a connection with at least Figure 5 In some embodiments, the seventh contact region may be similar to the fifth contact region. In some cases, the seventh contact region may be a portion of the fifth contact region. In some other cases, the seventh contact region may not be included in the fifth contact region or may be substituted for the seventh contact region.

[0084] In some embodiments, one or more diodes may be associated with or formed between certain structures or layers within a semiconductor device. For example, a first diode may be formed having a first cathode and a first anode. The first cathode may be associated with a first contact region. The first anode may be associated with a first well. In this case, the (e.g., electrical) connection between the first contact region and the first well may form the first diode. In another example, a second diode may be formed having a second cathode and a second anode. The second cathode may be associated with a third contact region. The second anode may be associated with the second contact region. In yet another example, a third diode may be formed having a third cathode and a third anode. The third cathode may be associated with a sixth contact region. The third anode may be associated with a fifth contact region.

[0085] In some embodiments, one or more SCRs may be associated with or formed between structures or layers within a semiconductor device. For example, a first SCR may be formed to conduct current through a first contact region, a first well, a substrate, and a fourth contact region. In this case, the (e.g., electrical) connection between the first contact region, the first well, the substrate, and the fourth contact region may form a first SCR of the semiconductor device (e.g., an SCR associated with the first diode). In another example, a second SCR may be formed to conduct current through a second contact region, a second well, the substrate, and the fourth contact region. In this case, the (e.g., electrical) connection between the second contact region, the second well, the substrate, and the fourth contact region may form a second SCR of the semiconductor device (e.g., an SCR associated with the second diode). Additional or alternative structures may be fabricated or deposited to form other diodes, SCRs, and other devices.

[0086] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode, and the second cathode is connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input / output pin, and the third anode is connected to a second supply voltage. The second anode is coupled to a circuit powered by the first supply voltage and the second supply voltage. The first diode has a first size, and the second diode has a second size, and the first size is substantially larger than the second size.

[0087] In some embodiments, the device further comprises: a fourth diode having a fourth cathode and a fourth anode; wherein the fourth cathode is connected to the second anode, and the fourth anode is connected to the second supply voltage. In some embodiments, the third diode has a third magnitude and the fourth diode has a fourth magnitude, and the third magnitude is substantially greater than the fourth magnitude. In some embodiments, the first anode and the second anode are electrically coupled to each other via a resistor. In some embodiments, the device further comprises: a fifth diode having a fifth cathode and a fifth anode; wherein the fifth cathode is floating, and the fifth anode is coupled to the input / output pin and to the second anode. In some embodiments, the fifth anode is coupled to the input / output pin and the second anode via respective different resistors. In some embodiments, a ratio of the first magnitude to the second magnitude is between approximately 9.5 / 0.5 and approximately 7 / 3. In some embodiments, at least the first through third diodes are operable to function as an electrostatic discharge protection circuit configured to provide multiple discharge paths from the input / output pin to the second supply voltage.

[0088] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a substrate having a first conductivity. The semiconductor device includes a first well surrounded by the substrate and having a second conductivity. The semiconductor device includes a second well surrounded by the substrate and having the second conductivity. The semiconductor device includes a first contact region surrounded by the first well and having the first conductivity. The semiconductor device includes a second contact region surrounded by the second well and having the first conductivity. The semiconductor device includes a third contact region also surrounded by the second well and having the second conductivity. The semiconductor device includes a fourth contact region surrounded by the substrate, disposed on a first lateral side of the first and second wells, and having the second conductivity. The semiconductor device includes a fifth contact region surrounded by the substrate, disposed opposite the fourth contact region relative to the first and second wells, and having the first conductivity. The semiconductor device includes a sixth contact region surrounded by the substrate, disposed on a second lateral side of the first well, and having the second conductivity. The semiconductor device includes a seventh contact region surrounded by the substrate, disposed adjacent to the sixth contact region relative to the first well, and having the first conductivity.

[0089] In some embodiments, the first contact region forms a first diode with the first well, the first well being floating, and the first contact region is coupled to an input / output pin. In some embodiments, the second contact region forms a second diode with the second well having the third contact region, the second contact region being coupled to the first contact region via a metal resistor disposed above the substrate, and the third contact region being coupled to VDD. In some embodiments, the first contact region extends a first length, and the second contact region extends a second length, wherein the first length is substantially greater than the second length. In some embodiments, the sixth contact region forms a third diode with the substrate having the seventh contact region, the sixth contact region being coupled to an input / output pin, and the seventh contact region being coupled to VSS. In some embodiments, the first well and the first contact region disposed in the first well are disposed adjacent to the fourth contact region coupled to VSS, thereby forming a first silicon-controlled rectifier that conducts current through the first contact region, the first well, the substrate, and the fourth contact region. In some embodiments, the second well and the second contact region disposed in the second well are disposed proximate to the fourth contact region, thereby forming a second silicon-controlled rectifier (SiC) to conduct current through the second contact region, the second well, the substrate, and the fourth contact region. In some embodiments, the second SiC rectifier is configured to be formed before forming the first SiC rectifier. In some embodiments, the first SiC rectifier is configured to provide a first discharge path from the first contact region coupled to an input / output pin to VSS, and the second SiC rectifier is configured to provide a second discharge path from the second contact region coupled to the input / output pin to VSS.

[0090] In another aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed. The method includes forming a first diode having a first cathode and a first anode, wherein the first diode has a first size and wherein the first cathode is floating. The method includes forming a second diode having a second cathode and a second anode, wherein the second diode has a second size and wherein the first size is substantially greater than the second size. The method includes coupling the first anode to the second anode and connecting the second cathode to a first supply voltage. The method includes forming a third diode having a third cathode and a third anode. The method includes connecting the third cathode to the first anode at an input / output pin and connecting the third anode to a second supply voltage. The method includes coupling the second anode to a circuit powered by the first supply voltage and the second supply voltage.

[0091] In another aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed, comprising: forming a substrate having a first conductivity; forming a plurality of wells surrounded by the substrate and having a second conductivity, the plurality of wells including a first well and a second well; forming a first contact region surrounded by the first well and having the first conductivity; forming a second contact region surrounded by the second well and having the first conductivity; forming a third contact region also surrounded by the second well and having the second conductivity; forming a fourth contact region, the fourth contact region being surrounded by the substrate, disposed on a first lateral side of the first well and the second well, and having the second conductivity; forming a fifth contact region, the fifth contact region being surrounded by the substrate, disposed opposite the fourth contact region relative to the first well and the second well, and having the first conductivity; forming a sixth contact region, the sixth contact region being surrounded by the substrate, disposed on a second lateral side of the first well, and having the second conductivity; and forming a seventh contact region, the seventh contact region being surrounded by the substrate, disposed adjacent to the sixth contact region relative to the first well, and having the first conductivity.

[0092] In some embodiments, a first diode having a first cathode and a first anode is formed, wherein the first cathode is associated with the first contact region and the first anode is associated with the first well; a second diode having a second cathode and a second anode is formed, wherein the second cathode is associated with the third contact region and the second anode is associated with the second contact region; and a third diode having a third cathode and a third anode is formed, wherein the third cathode is associated with the sixth contact region and the third anode is associated with the fifth contact region. In some embodiments, a first silicon-controlled rectifier is formed to conduct current through the first contact region, the first well, the substrate, and the fourth contact region; and a second silicon-controlled rectifier is formed to conduct current through the second contact region, the second well, the substrate, and the fourth contact region.

[0093] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10% to 30% of the stated value (e.g., ±10%, ±20%, or ±30% of the stated value).

[0094] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a first diode having a first cathode and a first anode, wherein the first cathode is floating; a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode, and the second cathode is connected to a first supply voltage; as well as a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at the input / output pin, and the third anode is connected to a second supply voltage; wherein the second anode is coupled to a circuit powered by the first supply voltage and the second supply voltage; The first diode has a first size and the second diode has a second size, and the first size is substantially larger than the second size.

2. The semiconductor device according to claim 1, wherein Further including: a fourth diode having a fourth cathode and a fourth anode; The fourth cathode is connected to the second anode, and the fourth anode is connected to the second supply voltage.

3. The semiconductor device according to claim 2, wherein The third diode has a third size and the fourth diode has a fourth size, and the third size is substantially larger than the fourth size.

4. The semiconductor device according to claim 1, wherein The first anode and the second anode are electrically coupled to each other through a resistor.

5. The semiconductor device according to claim 1, wherein Further including: a fifth diode having a fifth cathode and a fifth anode; The fifth cathode is floating, and the fifth anode is coupled to the input / output pin and to the second anode.

6. The semiconductor device according to claim 5, wherein The fifth anode is coupled to the input / output pin and the second anode through respectively different resistors.

7. A semiconductor device, characterized in that: include: a substrate having a first conductivity; a first well surrounded by the substrate and having a second conductivity; a second well surrounded by the substrate and having the second conductivity; a first contact region, surrounded by the first well and having the first conductivity; a second contact region surrounded by the second well and having the first conductivity; a third contact region, also surrounded by the second well and having the second conductivity; a fourth contact region, surrounded by the substrate, disposed on a first lateral side of the first well and the second well, and having the second conductivity; a fifth contact region, surrounded by the substrate, disposed opposite to the fourth contact region relative to the first well and the second well, and having the first conductivity; a sixth contact region, surrounded by the substrate, disposed on a second lateral side of the first well, and having the second conductivity; as well as The seventh contact region is surrounded by the substrate, is disposed adjacent to the sixth contact region relative to the first well, and has the first conductivity.

8. The semiconductor device according to claim 7, wherein The first contact region and the first well form a first diode, and the first well is floating. The first contact region is coupled to an input / output pin.

9. The semiconductor device according to claim 7, wherein: The first well and the first contact region disposed in the first well are adjacent to the fourth contact region coupled to VSS, thereby forming a first silicon-controlled rectifier to conduct current through the first contact region, the first well, the substrate, and the fourth contact region.

10. The semiconductor device according to claim 9, wherein The second well and the second contact region disposed in the second well are disposed adjacent to the fourth contact region, thereby forming a second silicon-controlled rectifier to conduct current through the second contact region, the second well, the substrate and the fourth contact region.

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