Vehicle speed pulse detection circuit, vehicle speed measurement circuit and vehicle-mounted equipment

Abstract

The utility model provides a vehicle speed pulse detection circuit, a vehicle speed measuring circuit and a vehicle-mounted device, the vehicle speed pulse detection circuit comprises a first comparison circuit, a second comparison circuit and a trigger circuit, a normal vehicle speed pulse signal is output to the first comparison circuit and the second comparison circuit for high and low threshold value comparison; the two comparison circuits respectively output a first level signal and a second level signal which are opposite in level, the trigger circuit switches and outputs a jumped third level signal and a jumped fourth level signal, and after an abnormal pulse signal passes through the two comparison circuits, the trigger circuit is triggered to be kept in a holding state and maintain the output of the last level. The trigger circuit does not output a hopping level signal, and the signal processing circuit at the rear end only performs pulse counting on a normal vehicle speed pulse signal and determines vehicle speed information, so that the shielding effect of an abnormal pulse signal is realized, and the speed measurement accuracy is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of vehicle speed detection, and in particular relates to a vehicle speed pulse detection circuit, a vehicle speed measurement circuit and a vehicle-mounted device. Background Art

[0002] In the field of vehicle-mounted detection, the vehicle speed pulse signal is a very important parameter, and the accuracy of this parameter directly affects the instrument speed value.

[0003] The existing technical solution for vehicle speed pulse detection is to adopt a single-channel comparison method, set a single threshold point (generally set to the middle threshold), compare the vehicle speed pulse signal with the preset threshold point, and then give the compared signal to the signal processing circuit. The signal processing circuit determines the vehicle speed information based on the number of rising and / or falling edge jumps received.

[0004] However, if Figure 1 As shown, in the existing solution, there are some abnormal pulses (abnormal pulse 1, abnormal pulse 2) that cannot be shielded. When the vehicle speed pulse signal is compared, it will also trigger the signal jump by mistake, causing the signal processing circuit to count the vehicle speed, resulting in reduced speed measurement accuracy. Utility Model Content

[0005] The utility model aims to provide a vehicle speed pulse detection circuit, aiming to solve the problem that the traditional vehicle speed pulse detection method has abnormal signals that cannot be shielded, resulting in low speed measurement accuracy.

[0006] A first aspect of an embodiment of the present utility model provides a vehicle speed pulse detection circuit for detecting a vehicle speed pulse signal, comprising:

[0007] a first comparison circuit, configured to compare the vehicle speed pulse signal with a first threshold voltage, and output a first level signal when the vehicle speed pulse signal is greater than the first threshold voltage, and output a second level signal when the vehicle speed pulse signal is less than the first threshold voltage, wherein the first level signal and the second level signal are opposite level signals;

[0008] a second comparison circuit, configured to compare the vehicle speed pulse signal with a second threshold voltage, and output a second level signal when the vehicle speed pulse signal is greater than the second threshold voltage, and output a first level signal when the vehicle speed pulse signal is less than the second threshold voltage, the first threshold voltage being less than the second threshold voltage;

[0009] A trigger circuit, wherein a first input terminal of the trigger circuit is connected to the output terminal of the first comparison circuit, and a second input terminal of the trigger circuit is connected to the output terminal of the second comparison circuit. The trigger circuit is triggered by the second level signal output by the first comparison circuit to output a third level signal, and is triggered by the second level signal output by the second comparison circuit to output a fourth level signal, and is triggered by the first level signals output by the first comparison circuit and the second comparison circuit to maintain the output of the previous level, and the third level signal and the fourth level signal are opposite level signals.

[0010] Optionally, the first comparison circuit includes a first comparator;

[0011] The non-inverting input terminal of the first comparator is used to input the vehicle speed pulse signal to be measured, the inverting input terminal of the first comparator is used to input the first threshold voltage, and the output terminal of the first comparator constitutes the output terminal of the first comparison circuit.

[0012] Optionally, the second comparison circuit includes a second comparator;

[0013] The non-inverting input terminal of the second comparator is used to input the second threshold voltage, the inverting input terminal of the second comparator is used to input the vehicle speed pulse signal to be measured, and the output terminal of the second comparator constitutes the output terminal of the second comparison circuit.

[0014] Optionally, the trigger circuit includes a first NAND gate and a second NAND gate;

[0015] The first input end of the first NAND gate constitutes the first input end of the trigger circuit, the first input end of the second NAND gate constitutes the second input end of the trigger circuit, the second input end of the first NAND gate is connected to the output end of the second NAND gate, and the output end of the first NAND gate is connected to the second input end of the second NAND gate to constitute the output end of the trigger circuit.

[0016] Optionally, the vehicle speed pulse detection circuit further includes:

[0017] A voltage divider circuit, the input end of the voltage divider circuit is used to input the vehicle speed pulse signal, the output end of the voltage divider circuit is respectively connected to the input end of the first comparison circuit and the input end of the second comparison circuit, and the voltage divider circuit is used to output the vehicle speed pulse signal by voltage division.

[0018] Optionally, the voltage divider circuit includes a first resistor and a second resistor;

[0019] The first end of the first resistor is used to input the vehicle speed pulse signal, the second end of the first resistor and the first end of the second resistor constitute the output end of the voltage divider circuit, and the second end of the second resistor is grounded.

[0020] Optionally, the vehicle speed pulse detection circuit further includes:

[0021] A filter circuit, wherein the input end of the filter circuit is connected to the output end of the trigger circuit, the output end of the filter circuit constitutes the output end of the vehicle speed pulse detection circuit, and the filter circuit is used to filter the signal output by the trigger circuit.

[0022] Optionally, the filtering circuit includes a third resistor and a capacitor;

[0023] The first end of the third resistor constitutes the input end of the filter circuit, the second end of the third resistor is connected to the first end of the capacitor to constitute the output end of the filter circuit, and the second end of the capacitor is grounded.

[0024] A second aspect of the embodiment of the present utility model provides a vehicle speed measurement circuit, comprising a signal processing circuit and the vehicle speed pulse detection circuit as described above, wherein the signal processing circuit is connected to the vehicle speed pulse detection circuit;

[0025] The signal processing circuit is used to count the jump signals output by the vehicle speed pulse detection circuit and determine the vehicle speed information.

[0026] A third aspect of the embodiments of the present invention provides a vehicle-mounted device, comprising the vehicle speed measurement circuit as described above.

[0027] Compared with the prior art, the beneficial effects of the embodiments of the present utility model are as follows: the above-mentioned vehicle speed pulse detection circuit includes a first comparison circuit, a second comparison circuit and a trigger circuit; the normal vehicle speed pulse signal is output to the first comparison circuit and the second comparison circuit for high and low threshold comparison, and outputs a first level signal and a second level signal of opposite levels respectively; the trigger circuit switches to output a third level signal and a fourth level signal of a jump; and after the abnormal pulse signal passes through the two comparison circuits, the trigger circuit is triggered to remain in a hold state and maintain the output of the previous level; the trigger circuit will not output a jump level signal; the back-end signal processing circuit will only count the pulses of the normal vehicle speed pulse signal and determine the vehicle speed information, thereby realizing the shielding effect of the abnormal pulse signal and improving the speed measurement accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 Schematic diagram of the waveform of the vehicle speed pulse signal and abnormal signal provided by the embodiment of the present utility model;

[0030] Figure 2 A schematic diagram of the first structure of a vehicle speed pulse detection circuit provided by an embodiment of the present utility model;

[0031] Figure 3 A second structural diagram of a vehicle speed pulse detection circuit provided by an embodiment of the present utility model;

[0032] Figure 4 A circuit diagram of a vehicle speed pulse detection circuit provided by an embodiment of the present utility model;

[0033] Figure 5 This is a schematic diagram of the structure of a vehicle speed measurement circuit provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0034] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of this utility model, "plurality" means two or more, unless otherwise specifically defined.

[0036] The first aspect of the embodiment of the present utility model proposes a vehicle speed pulse detection circuit 100 for detecting a vehicle speed pulse signal f to output a jump level signal to the back-end signal processing circuit 200, and then determine the vehicle speed information according to the jump level signal to complete the speed measurement function.

[0037] In order to improve the accuracy of speed measurement, Figure 2 As shown, in this embodiment, the vehicle speed pulse detection circuit 100 includes:

[0038] A first comparison circuit 10 is configured to compare the vehicle speed pulse signal f with a first threshold voltage Vref1, and output a first level signal when the vehicle speed pulse signal f is greater than the first threshold voltage Vref1, and output a second level signal when the vehicle speed pulse signal f is less than the first threshold voltage Vref1, wherein the first level signal and the second level signal are opposite level signals;

[0039] a second comparison circuit 20 for comparing the vehicle speed pulse signal f with a second threshold voltage Vref2, and outputting a second level signal when the vehicle speed pulse signal f is greater than the second threshold voltage Vref2, and outputting a first level signal when the vehicle speed pulse signal f is less than the second threshold voltage Vref2, wherein the first threshold voltage Vref1 is less than the second threshold voltage Vref2;

[0040] A trigger circuit 30, wherein a first input terminal of the trigger circuit 30 is connected to an output terminal of the first comparison circuit 10, and a second input terminal of the trigger circuit is connected to an output terminal of the second comparison circuit 20. The trigger circuit 30 is triggered by the second level signal output by the first comparison circuit 10 to output a third level signal, and is triggered by the second level signal output by the second comparison circuit 20 to output a fourth level signal, and is triggered by the first level signal output by the first comparison circuit 10 and the second comparison circuit 20 to maintain the output of the previous level, wherein the third level signal and the fourth level signal are opposite level signals.

[0041] In this embodiment, Figure 1 As shown, the normal vehicle speed pulse signal f is composed of alternating fifth-level signals and sixth-level signals, the fifth-level signal is a low-level signal, the sixth-level signal is a high-level signal, the fifth-level signal to the sixth-level signal forms a rising edge, and the sixth-level signal to the fifth-level signal forms a falling edge. The back-end signal processing circuit 200 can determine the vehicle speed information by calculating the number of fifth-level signals or the number of sixth-level signals in unit time.

[0042] The configured first threshold voltage Vref1 is greater than the voltage of the fifth level signal, and the configured second threshold voltage Vref2 is less than the voltage of the sixth level signal.

[0043] During vehicle speed pulse detection, when a normal vehicle speed pulse signal f is input, and when the vehicle speed pulse signal f is a fifth-level signal, the fifth-level signal is less than the first threshold voltage Vref1 and the second threshold voltage Vref2, the first comparison circuit 10 outputs a second-level signal, and the second comparison circuit 20 outputs a first-level signal, the first-level signal and the second-level signal being of opposite levels. At this time, the first input terminal of the trigger circuit 30 receives the second-level signal, triggering the trigger circuit 30 to output a third-level signal. When the vehicle speed pulse signal f is a sixth-level signal, the sixth-level signal is greater than the first threshold voltage Vref1 and the second threshold voltage Vref2, the first comparison circuit 10 outputs the first-level signal, and the second comparison circuit 20 outputs the second-level signal. At this time, the second input terminal of the trigger circuit 30 receives the second-level signal, triggering the trigger circuit 30 to output a fourth-level signal, the third-level signal and the fourth-level signal being of opposite levels.

[0044] Therefore, when a normal vehicle speed pulse signal f is input, the trigger circuit 30 triggers the output of the third-level signal and the fourth-level signal that jump. The back-end signal processing circuit 200 can detect the jump level signal and can determine the number of vehicle speed pulses based on the jump third-level signal and the fourth-level signal, and thereby determine the vehicle speed information.

[0045] When the input abnormal pulse signal is abnormal pulse 1, it is composed of alternating seventh-level and eighth-level signals. The seventh-level signal is a low-level signal, and the eighth-level signal is a high-level signal. The transition from the seventh-level signal to the eighth-level signal forms a rising edge, and the transition from the eighth-level signal to the seventh-level signal forms a falling edge. The configured first threshold voltage Vref1 is less than the voltage of the seventh-level signal, and the second threshold voltage Vref2 is less than the voltage of the eighth-level signal. When abnormal pulse 1 is the seventh-level signal, the seventh-level signal is greater than the first threshold voltage Vref1 and less than the second threshold voltage Vref2. The first comparator circuit 10 outputs a first-level signal, and the second comparator circuit 20 outputs a first-level signal. At this time, both input terminals of the trigger circuit 30 input the first-level signal simultaneously, triggering the trigger circuit 30 to a hold state and maintaining the output at the previous level. When abnormal pulse 1 is the eighth-level signal, the eighth-level signal is greater than the first threshold voltage Vref1 and the second threshold voltage Vref2. The first comparator circuit 10 outputs a first-level signal, and the second comparator circuit 20 outputs a second-level signal. At this time, the second input terminal of the trigger circuit 30 inputs the second-level signal, triggering the trigger circuit 30 to output a fourth-level signal. When the abnormal pulse 1 jumps, the trigger circuit 30 outputs the third level signal and the fourth level signal without jumping. The trigger circuit 30 realizes the hysteresis function of the pulse. The back-end signal processing circuit 200 will not detect the jumping level signal, and thus will not count the abnormal pulse 1, thereby improving the accuracy of counting and speed measurement.

[0046] Similarly, when the input abnormal pulse signal is abnormal pulse 2, it is composed of alternating ninth-level and tenth-level signals, with the ninth-level signal being a low-level signal and the tenth-level signal being a high-level signal. The transition from the ninth-level signal to the tenth-level signal forms a rising edge, and the transition from the tenth-level signal to the ninth-level signal forms a falling edge. The configured first threshold voltage Vref1 is greater than the voltage of the ninth-level signal, and the second threshold voltage Vref2 is greater than the voltage of the tenth-level signal. When abnormal pulse 2 is the ninth-level signal, the ninth-level signal is less than both the first threshold voltage Vref1 and the second threshold voltage Vref2. The first comparator circuit 10 outputs the second-level signal, the second comparator circuit 20 outputs the first-level signal, and the first input terminal of the trigger circuit 30 receives the second-level signal, triggering the trigger circuit 30 to output the third-level signal. When abnormal pulse 2 is the tenth-level signal, the tenth-level signal is greater than the first threshold voltage Vref1 and less than the second threshold voltage Vref2. The first comparator circuit 10 outputs the first-level signal, and the second comparator circuit 20 outputs the first-level signal. At this point, both input terminals of the trigger circuit 30 receive the first-level signal, triggering the trigger circuit 30 to a hold state, maintaining the output at the previous level. When the abnormal pulse 2 jumps, the trigger circuit 30 outputs the third level signal and the fourth level signal without jumping. The trigger circuit 30 realizes the hysteresis function of the pulse. The back-end signal processing circuit 200 will not detect the jumping level signal, and thus will not count the abnormal pulse 2, thereby improving the accuracy of counting and speed measurement.

[0047] Among them, the first comparison circuit 10 and the second comparison circuit 20 can be composed of structures such as comparators and MOS tubes. When MOS tubes are used, MOS tubes with different threshold turn-on voltages can be used to switch and output different level signals. The specific structure is not limited.

[0048] The trigger circuit 30 may adopt structures such as different types of triggers, logic gates, etc.

[0049] In an alternative embodiment, if Figure 4 As shown, the first comparison circuit 10 includes a first comparator U1;

[0050] The non-inverting input terminal of the first comparator U1 is used to input the vehicle speed pulse signal f to be measured, the inverting input terminal of the first comparator U1 is used to input the first threshold voltage Vref1, and the output terminal of the first comparator U1 constitutes the output terminal of the first comparison circuit 10.

[0051] The second comparison circuit 20 includes a second comparator U2;

[0052] The non-inverting input terminal of the second comparator U2 is used to input the second threshold voltage Vref2 , the inverting input terminal of the second comparator U2 is used to input the vehicle speed pulse signal f to be measured, and the output terminal of the second comparator U2 constitutes the output terminal of the second comparison circuit 20 .

[0053] The trigger circuit 30 includes a first NAND gate U3 and a second NAND gate U4;

[0054] The first input end of the first NAND gate U3 constitutes the first input end of the trigger circuit 30, the first input end of the second NAND gate U4 constitutes the second input end of the trigger circuit 30, the second input end of the first NAND gate U3 is connected to the output end of the second NAND gate U4, and the output end of the first NAND gate U3 is connected to the second input end of the second NAND gate U4 to constitute the output end of the trigger circuit 30.

[0055] In this embodiment, the first level signal is a high level signal, the second level signal is a low level signal, the third level signal is a high level signal, and the fourth level signal is a low level signal.

[0056] During vehicle speed pulse detection, when a normal vehicle speed pulse signal f is input, when the vehicle speed pulse signal f is a fifth level signal, the fifth level signal is less than the first threshold voltage Vref1 and the second threshold voltage Vref2, the first comparator U1 outputs a low level signal, and the second comparator U2 outputs a high level signal. At this time, the input terminal of the second NAND gate U4 inputs a low level signal, and the output terminal of the first NAND gate U3 outputs a high level signal. When the vehicle speed pulse signal f is a sixth level signal, the sixth level signal is greater than the first threshold voltage Vref1 and the second threshold voltage Vref2, the first comparator U1 outputs a high level signal, and the second comparator U2 outputs a low level signal. At this time, the input terminal of the first NAND gate U3 inputs a low level signal, and the output terminal of the first NAND gate U3 triggers the output of the low level signal.

[0057] Therefore, when a normal vehicle speed pulse signal f is input, the first NAND gate U3 outputs a jumping high-level signal and a low-level signal. The back-end signal processing circuit 200 can detect the jumping level signal and determine the number of vehicle speed pulses based on the jumping high-level signal and the low-level signal, and thereby determine the vehicle speed information.

[0058] When the input abnormal pulse signal is abnormal pulse 1, it is composed of alternating seventh-level signals and eighth-level signals. The seventh-level signal is a low-level signal, and the eighth-level signal is a high-level signal. The seventh-level signal forms a rising edge to the eighth-level signal, and the eighth-level signal forms a falling edge to the seventh-level signal. The configured first threshold voltage Vref1 is less than the voltage of the seventh-level signal, and the second threshold voltage Vref2 is less than the voltage of the eighth-level signal. When abnormal pulse 1 is the seventh-level signal, the seventh-level signal is greater than the first threshold voltage Vref1 and less than the second threshold voltage Vref2. The first comparator U1 outputs a high-level signal, and the second comparator U2 outputs a high-level signal. At this time, the two input terminals of the first NAND gate U3 and the second NAND gate U4 simultaneously input high-level signals, triggering the trigger circuit 30 to the hold state, maintaining the output of the previous level. When abnormal pulse 1 is an eighth-level signal, the eighth-level signal is greater than the first threshold voltage Vref1 and the second threshold voltage Vref2. The first comparator U1 outputs a high-level signal, and the second comparator U2 outputs a low-level signal. At this time, the second NAND gate U4 inputs a low-level signal, and the output terminal of the first NAND gate U3 outputs a low-level signal. When abnormal pulse 1 transitions, the trigger circuit 30 outputs a non-transitioning high-level signal and a non-transitioning low-level signal. This trigger circuit 30 implements a pulse hysteresis function, and the back-end signal processing circuit 200 does not detect the transitional level signal, thus not counting abnormal pulse 1, thereby improving the accuracy of counting and speed measurement.

[0059] Similarly, when the input abnormal pulse signal is abnormal pulse 2, it is composed of alternating ninth-level and tenth-level signals, with the ninth-level signal being a low-level signal and the tenth-level signal being a high-level signal. The transition from the ninth-level signal to the tenth-level signal forms a rising edge, while the transition from the tenth-level signal to the ninth-level signal forms a falling edge. The configured first threshold voltage Vref1 is greater than the voltage of the ninth-level signal, and the second threshold voltage Vref2 is greater than the voltage of the tenth-level signal. When abnormal pulse 2 is the ninth-level signal, the ninth-level signal is less than both the first and second threshold voltages Vref1 and Vref2. The first comparator U1 outputs a low-level signal, the second comparator U2 outputs a high-level signal, the low-level signal is input to the input of the first NAND gate U3, and the output of the first NAND gate U3 outputs a high-level signal. When abnormal pulse 2 is the tenth level signal, the tenth level signal is greater than the first threshold voltage Vref1 and less than the second threshold voltage Vref2. The first comparator U1 outputs a high-level signal, and the second comparator U2 outputs a high-level signal. At this time, the first NAND gate U3 and the second NAND gate U4 simultaneously input high-level signals, triggering the trigger circuit 30 to the hold state, maintaining the output of the previous level. When abnormal pulse 2 jumps, the trigger circuit 30 outputs a high-level signal and a low-level signal without jumping. The trigger circuit 30 implements the pulse hysteresis function. The back-end signal processing circuit 200 will not detect the jumping level signal and thus will not count abnormal pulse 2, improving the accuracy of counting and speed measurement.

[0060] Furthermore, in order to ensure that the input vehicle speed pulse signal f is within the operating voltage range of the first comparison circuit 10, the second comparison circuit 20 and the trigger circuit 30, and to avoid overvoltage damage to the subsequent circuit, in an optional embodiment, as shown in FIG. Figure 3 As shown, the vehicle speed pulse detection circuit 100 further includes:

[0061] The voltage divider circuit 40 has an input end for inputting the vehicle speed pulse signal f, and an output end of the voltage divider circuit 40 is respectively connected to the input end of the first comparison circuit 10 and the input end of the second comparison circuit 20. The voltage divider circuit 40 is used to divide the vehicle speed pulse signal f and output it.

[0062] In this embodiment, the voltage divider circuit 40 can perform voltage division processing on the input vehicle speed pulse signal f, limit the amplitude of the vehicle speed pulse signal f to the operating voltage range of the subsequent circuit, prevent the subsequent circuit from being damaged by overvoltage, and improve the reliability of vehicle speed pulse detection.

[0063] The voltage divider circuit 40 may adopt a resistor voltage divider structure, a step-down circuit, etc. In order to simplify the structure of the vehicle speed pulse detection circuit 100, in an optional embodiment, as shown in FIG. Figure 4 As shown, the voltage divider circuit 40 includes a first resistor R1 and a second resistor R2;

[0064] The first end of the first resistor R1 is used to input the vehicle speed pulse signal f, the second end of the first resistor R1 and the first end of the second resistor R2 form the output end of the voltage divider circuit 40, and the second end of the second resistor R2 is grounded.

[0065] In this embodiment, the vehicle speed pulse signal f is output to the first comparison circuit 10 and the second comparison circuit 20 at the rear end after voltage division by the first resistor R1 and the second resistor R2. The ratio of the amplitude of the divided vehicle speed pulse signal f to the original vehicle speed pulse signal f is R2 / (R1+R2).

[0066] Furthermore, in order to reduce the generation of peak voltage during the vehicle speed pulse detection process and reduce the slope of the generated level signal, in an optional embodiment, as shown in FIG. Figure 3 As shown, the vehicle speed pulse detection circuit 100 further includes:

[0067] The filter circuit 50 has its input connected to the output of the trigger circuit 30 , and its output constitutes the output of the vehicle speed pulse detection circuit 100 . The filter circuit 50 is used to filter the signal output by the trigger circuit 30 .

[0068] The filter circuit 50 filters and charges and discharges the jump signal output by the trigger circuit 30, on the one hand filtering out noise, and on the other hand reducing the generation of spike voltage and lowering the slope of the jump signal, ensuring that the back-end signal processing circuit 200 samples the normal jump signal, thereby improving the working stability of the back-end signal processing circuit 200.

[0069] Correspondingly, the filter circuit 50 may adopt different types of hierarchical filter structures. In an optional embodiment, for example, Figure 4 As shown, the filter circuit 50 includes a third resistor R3 and a capacitor C1;

[0070] A first end of the third resistor R3 constitutes an input end of the filter circuit 50 , a second end of the third resistor R3 is connected to a first end of the capacitor C1 to constitute an output end of the filter circuit 50 , and a second end of the capacitor C1 is grounded.

[0071] In this embodiment, the third resistor R3 and the capacitor C1 constitute a low-pass filter circuit 50. The third capacitor C1, on the one hand, filters out noise, and on the other hand, reduces the generation of spike voltage, reduces the slope of the jump signal, ensures that the back-end signal processing circuit 200 samples the normal jump signal, and improves the working stability of the back-end signal processing circuit 200.

[0072] Compared with the prior art, the beneficial effects of the embodiment of the present invention are as follows: the above-mentioned vehicle speed pulse detection circuit 100 includes a first comparison circuit 10, a second comparison circuit 20 and a trigger circuit 30. The normal vehicle speed pulse signal f is output to the first comparison circuit 10 and the second comparison circuit 20 for high and low threshold comparison, and outputs a first level signal and a second level signal of opposite levels respectively. The trigger circuit 30 switches to output a third level signal and a fourth level signal of a jump. After the abnormal pulse signal passes through the two comparison circuits, the trigger circuit 30 is triggered to remain in a hold state and maintain the output of the previous level. The trigger circuit 30 will not output a jump level signal. The back-end signal processing circuit 200 will only count the pulses of the normal vehicle speed pulse signal f and determine the vehicle speed information, thereby realizing the shielding effect of the abnormal pulse signal and improving the speed measurement accuracy.

[0073] The utility model also proposes a vehicle speed measurement circuit, such as Figure 5 As shown, the vehicle speed measurement circuit includes a signal processing circuit 200 and a vehicle speed pulse detection circuit 100. The specific structure of the vehicle speed pulse detection circuit 100 refers to the above embodiment. Since this vehicle speed measurement circuit adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described in detail here. Among them, the signal processing circuit 200 is connected to the vehicle speed pulse detection circuit 100;

[0074] The signal processing circuit 200 is used to count the jump signals output by the vehicle speed pulse detection circuit 100 and determine the vehicle speed information.

[0075] In this embodiment, the vehicle speed pulse detection circuit 100 detects and converts the vehicle speed pulse signal f, and outputs a jump signal composed of a third level signal and a fourth level signal. The signal processing circuit 200 counts the jump signal and can count the rising edge and / or falling edge of the jump signal to determine the number of pulses and the corresponding vehicle speed information.

[0076] The signal processing circuit 200 may adopt a structure such as a counter, a timer, or a processor, and the specific structure is not limited.

[0077] The present utility model also proposes a vehicle-mounted device, which includes a vehicle speed measurement circuit. The specific structure of the vehicle speed measurement circuit refers to the above-mentioned embodiment. Since the present vehicle-mounted device adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.

[0078] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A vehicle speed pulse detection circuit for detecting a vehicle speed pulse signal, characterized in that: include: a first comparison circuit, configured to compare the vehicle speed pulse signal with a first threshold voltage, and output a first level signal when the vehicle speed pulse signal is greater than the first threshold voltage, and output a second level signal when the vehicle speed pulse signal is less than the first threshold voltage, wherein the first level signal and the second level signal are opposite level signals; a second comparison circuit, configured to compare the vehicle speed pulse signal with a second threshold voltage, and output a second level signal when the vehicle speed pulse signal is greater than the second threshold voltage, and output a first level signal when the vehicle speed pulse signal is less than the second threshold voltage, the first threshold voltage being less than the second threshold voltage; A trigger circuit, wherein a first input terminal of the trigger circuit is connected to the output terminal of the first comparison circuit, and a second input terminal of the trigger circuit is connected to the output terminal of the second comparison circuit. The trigger circuit is triggered by the second level signal output by the first comparison circuit to output a third level signal, and is triggered by the second level signal output by the second comparison circuit to output a fourth level signal, and is triggered by the first level signals output by the first comparison circuit and the second comparison circuit to maintain the output of the previous level, and the third level signal and the fourth level signal are opposite level signals.

2. The vehicle speed pulse detection circuit according to claim 1, characterized in that: The first comparison circuit includes a first comparator; The non-inverting input terminal of the first comparator is used to input the vehicle speed pulse signal to be measured, the inverting input terminal of the first comparator is used to input the first threshold voltage, and the output terminal of the first comparator constitutes the output terminal of the first comparison circuit.

3. The vehicle speed pulse detection circuit according to claim 1, characterized in that: The second comparison circuit includes a second comparator; The non-inverting input terminal of the second comparator is used to input the second threshold voltage, the inverting input terminal of the second comparator is used to input the vehicle speed pulse signal to be measured, and the output terminal of the second comparator constitutes the output terminal of the second comparison circuit.

4. The vehicle speed pulse detection circuit according to claim 1, wherein: The trigger circuit includes a first NAND gate and a second NAND gate; The first input end of the first NAND gate constitutes the first input end of the trigger circuit, the first input end of the second NAND gate constitutes the second input end of the trigger circuit, the second input end of the first NAND gate is connected to the output end of the second NAND gate, and the output end of the first NAND gate is connected to the second input end of the second NAND gate to constitute the output end of the trigger circuit.

5. The vehicle speed pulse detection circuit according to any one of claims 1 to 4, characterized in that: The vehicle speed pulse detection circuit also includes: A voltage divider circuit, the input end of the voltage divider circuit is used to input the vehicle speed pulse signal, the output end of the voltage divider circuit is respectively connected to the input end of the first comparison circuit and the input end of the second comparison circuit, and the voltage divider circuit is used to output the vehicle speed pulse signal by voltage division.

6. The vehicle speed pulse detection circuit according to claim 5, characterized in that: The voltage divider circuit includes a first resistor and a second resistor; The first end of the first resistor is used to input the vehicle speed pulse signal, the second end of the first resistor and the first end of the second resistor constitute the output end of the voltage divider circuit, and the second end of the second resistor is grounded.

7. The vehicle speed pulse detection circuit according to any one of claims 1 to 4, characterized in that: The vehicle speed pulse detection circuit also includes: A filter circuit, wherein the input end of the filter circuit is connected to the output end of the trigger circuit, the output end of the filter circuit constitutes the output end of the vehicle speed pulse detection circuit, and the filter circuit is used to filter the signal output by the trigger circuit.

8. The vehicle speed pulse detection circuit according to claim 7, characterized in that: The filtering circuit includes a third resistor and a capacitor; The first end of the third resistor constitutes the input end of the filter circuit, the second end of the third resistor is connected to the first end of the capacitor to constitute the output end of the filter circuit, and the second end of the capacitor is grounded.

9. A vehicle speed measurement circuit, characterized in that: comprising a signal processing circuit and a vehicle speed pulse detection circuit according to any one of claims 1 to 8, wherein the signal processing circuit is connected to the vehicle speed pulse detection circuit; The signal processing circuit is used to count the jump signals output by the vehicle speed pulse detection circuit and determine the vehicle speed information.

10. A vehicle-mounted device, characterized in that: The vehicle speed measuring circuit comprises the vehicle speed measuring circuit as claimed in claim 9.

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