Semiconductor package

Abstract

Semiconductor packages are provided. A semiconductor package, comprising: a first side of the semiconductor package and a second side of the semiconductor package, wherein the second side of the semiconductor package comprises a plurality of terminals; a back-to-back die comprising a first die electrically coupled to a second die; the first die electrically coupled to a first portion of the plurality of terminals through a first plurality of electrical traces and a plurality of Si blocks; the second die electrically coupled to a second portion of the plurality of terminals through a second plurality of electrical traces; wherein the back-to-back die is configured to stop running if an electrical connection to one of the plurality of terminals is broken.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to semiconductor packages, and more particularly to semiconductor packages having back-to-back dies with panel-level packaging (PLP). Background Art

[0002] Semiconductor packages are susceptible to probing or intrusion, particularly in certain industries where semiconductor packages can be used for authentication. For example, attacks that probe or intrude into semiconductor dies can be common in certain industries, such as ink cartridges that use authentication chips. If successful, such attacks can allow an attacker to learn information about the semiconductor and copy it for use in counterfeit products. While the front or top side of the die in a semiconductor package may have some protection against probing, other sides or areas of the die in the semiconductor package may still be more exposed to probing or intrusion.

[0003] There is a need for new semiconductor packages. The inventors have identified many areas for improvement in existing technologies and techniques, which are the subject of the embodiments described herein. Through dedicated effort, ingenuity, and innovation, many of these deficiencies, challenges, and problems have been addressed by developing solutions included in the embodiments of the present disclosure, some examples of which are described in detail herein. Utility Model Content

[0004] Semiconductor packages are subject to intrusion attacks that attempt to copy information on one or more dies. Various embodiments described herein are directed to improved semiconductor packages, particularly back-to-back (BTB) dies for semiconductor packages. Various embodiments of semiconductor packages with BTB dies include a Si block for improved protection, heat dissipation, and / or shielding.

[0005] According to some embodiments of the present disclosure, an example semiconductor package is provided. The semiconductor package may include: a first side of the semiconductor package and a second side of the semiconductor package, wherein the second side of the semiconductor package includes a plurality of terminals; a back-to-back (BTB) die including a first die electrically coupled to a second die; the first die electrically coupled to a first portion of the plurality of terminals via a first plurality of electrical traces and a plurality of Si blocks; and the second die electrically coupled to a second portion of the plurality of terminals via a second plurality of electrical traces; wherein the BTB die is configured to cease operation if an electrical connection to one of the plurality of terminals is broken.

[0006] In some embodiments, a semiconductor package includes a heat spreader on a first side of the semiconductor package.

[0007] In some embodiments, the heat sink is coupled to one or more terminals on the second side of the semiconductor package through one or more Si-bulks.

[0008] In some embodiments, the first die is electrically coupled to the first plurality of traces using a plurality of vias through the first laminate layer.

[0009] In some embodiments, the first laminate layer includes ABF.

[0010] In some embodiments, at least one Si block of the plurality of Si blocks is positioned on at least a first lateral side of the BTB die, and at least a second Si block of the plurality of Si blocks is positioned on at least a second lateral side of the BTB die.

[0011] In some embodiments, each lateral side of the BTB die has at least one Si block of the plurality of Si blocks positioned on the corresponding lateral side.

[0012] In some embodiments, a height of a first Si block among the plurality of Si blocks is different from a height of at least a second Si block among the plurality of Si blocks.

[0013] In some embodiments, the plurality of electrical traces are in a fan-out pattern.

[0014] In some embodiments, the semiconductor package is a first semiconductor package of a plurality of semiconductor packages in a panel.

[0015] According to some embodiments of the present disclosure, an example manufacturing method is provided. The manufacturing method may include: preparing a back-to-back (BTB) die, the back-to-back die including a first die electrically coupled to a second die; forming a first side of a semiconductor package and a second side of the semiconductor package, including electrically coupling a plurality of Si blocks to the first die via a plurality of traces and electrically coupling a plurality of terminals on the second side of the semiconductor package to the second die; wherein the BTB die is configured to cease operation if an electrical connection to one of the plurality of terminals is broken.

[0016] In some embodiments, forming the first side of the semiconductor package and the second side of the semiconductor package further includes forming a heat spreader on the first side of the semiconductor package.

[0017] In some embodiments, forming the first side of the semiconductor package and the second side of the semiconductor package further includes forming a heat spreader on the first side of the semiconductor package to electrically couple to one or more Si blocks of the plurality of Si blocks.

[0018] In some embodiments, forming the first side of the semiconductor package and the second side of the semiconductor package further includes electrically coupling the plurality of traces to the first die using a plurality of vias through the first laminate layer.

[0019] In some embodiments, the first laminate layer includes ABF.

[0020] In some embodiments, at least one Si block of the plurality of Si blocks is positioned on at least a first lateral side of the BTB die, and at least a second Si block of the plurality of Si blocks is positioned on at least a second lateral side of the BTB die.

[0021] In some embodiments, each lateral side of the BTB die has at least one Si block of the plurality of Si blocks positioned on the corresponding lateral side.

[0022] In some embodiments, a height of a first Si block among the plurality of Si blocks is different from a height of at least a second Si block among the plurality of Si blocks.

[0023] In some embodiments, the plurality of electrical traces are in a fan-out pattern.

[0024] In some embodiments, the semiconductor package is a first semiconductor package of a plurality of semiconductor packages in a panel.

[0025] The above summary is provided merely to summarize some example embodiments to provide a basic understanding of some aspects of the present disclosure. Thus, it will be appreciated that the above embodiments are merely examples and should not be construed as narrowing the scope or spirit of the present disclosure in any way. It will also be appreciated that the scope of the present disclosure encompasses many potential embodiments beyond those outlined herein, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Having generally described certain example embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0027] Figure 1 illustrates a cross-sectional view of a block diagram of a first semiconductor package having a BTB die according to one or more embodiments of the present disclosure;

[0028] Figure 2A illustrates a cross-sectional view of a block diagram of a second semiconductor package having a BTB die according to one or more embodiments of the present disclosure;

[0029] Figure 2B illustrates a cross-sectional view of a block diagram of a third semiconductor package having a BTB die according to one or more embodiments of the present disclosure;

[0030] Figure 3 illustrates a top view of a cross section of a semiconductor package having a BTB die according to one or more embodiments of the present disclosure;

[0031] Figure 4 illustrates an example flow chart of operations for manufacturing a semiconductor package according to one or more embodiments of the present disclosure;

[0032] Figure 5 illustrates an example flow chart of operations for preparing BTB die(s) according to one or more embodiments of the present disclosure;

[0033] Figures 6A-6F illustrates an example block diagram associated with operations for preparing BTB die(s) according to one or more embodiments of the present disclosure;

[0034] Figure 7 illustrates an example flow chart of operations for forming a first side of a semiconductor package(s) according to one or more embodiments of the present disclosure;

[0035] Figures 8A-8Q A cross-sectional diagram illustrating an example block diagram associated with operations for forming a first side of a semiconductor package(s) according to one or more embodiments of the present disclosure;

[0036] Figure 9A-9B illustrates an example flow chart of operations for forming a second side of a semiconductor package(s) in accordance with one or more embodiments of the present disclosure;

[0037] Figures 10A-10Y a cross-sectional diagram illustrating an example block diagram associated with operations for forming a second side of a semiconductor package(s) in accordance with one or more embodiments of the present disclosure; and

[0038] Figure 11 Illustrated is an example flow chart of operations for finishing semiconductor package(s) in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] Some embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, which illustrate some, but not all, embodiments of the present disclosure. Indeed, the various embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0040] As used herein, the term "comprising" means including, but not limited to, and should be interpreted in the manner in which it is commonly used in a patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and comprising essentially of.

[0041] The phrases "in various embodiments," "in one embodiment," "according to one embodiment," "in some embodiments," etc. generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure and may be included in more than one embodiment of the present disclosure (importantly, such phrases are not necessarily referring to the same embodiment).

[0042] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0043] If the specification states that a component or feature "may," "should," "will," "preferably," "might," "typically," "optionally," "for example," "often," or "might" (or other such language) include or have a certain characteristic, then that particular component or feature is not required to include or have that characteristic. Such a component or feature may optionally be included in some embodiments or may be excluded.

[0044] The use of the term "circuitry" as used herein with respect to components of a system or device should be understood to include specific hardware configured to perform the functions associated with the particular circuitry as described herein. The term "circuitry" should be understood broadly to include hardware, and in some embodiments, software for configuring the hardware. For example, in some embodiments, "circuitry" may include processing circuitry, communication circuitry, input / output circuitry, etc. In some embodiments, other elements may provide or supplement the functionality of the particular circuitry.

[0045] Overview

[0046] Various embodiments of the present disclosure are directed to improved semiconductor packages, particularly back-to-back (BTB) dies for semiconductor packages. Various embodiments of semiconductor packages with BTB dies include Si blocks for improved protection, heat dissipation, and / or shielding.

[0047] Semiconductor packages are susceptible to intrusion attacks that attempt to replicate information on one or more dies. For example, a semiconductor package used in a printer's ink cartridge may include one or more dies used for cartridge authentication. An attacker could attempt to compromise the semiconductor package to access the dies and replicate the ability to authenticate the cartridge. The top or front side of the semiconductor package may include a heat sink or metal layer to not only provide heat dissipation but also provide protection against detection. The embodiments described herein employ additional measures.

[0048] For example, the lateral sides of the semiconductor packages described herein can be provided with anti-probe measures for the Si-blocks that could be damaged or destroyed during an intrusion attack. The BTB die can be configured such that if an intrusion attack were to damage, destroy, disrupt, or otherwise damage one of the Si-blocks or other electrical coupling to one of the plurality of terminals, the BTB die would cease operation. Thus, the attack or probing would be thwarted. Additionally or alternatively, the Si-blocks can provide improved thermal management by dissipating heat through the Si-blocks connected to a heat sink. Furthermore, the Si-blocks can provide improved EMI shielding for the semiconductor package.

[0049] In various embodiments, the semiconductor package of the present disclosure may be manufactured in a panel level packaging (PLP) with multiple similar and / or different semiconductor packages.

[0050] It should be readily apparent that the embodiments described herein may be configured in various additional and alternative ways besides those explicitly described herein.

[0051] Exemplary Systems and Apparatus

[0052]

[0014] Embodiments of the present disclosure described herein include systems and apparatus for back-to-back (BTB) die of semiconductor packaging that can be implemented in various embodiments. Figure 1 、 Figure 2A 、 Figure 2B and Figure 3 An embodiment of a semiconductor package including a BTB die is illustrated. The BTB die 102 includes a first die 110A coupled to a second die 110B via a BTB connection layer 112 (e.g., tape, glue, ABF, etc.). There may be multiple electrical connections electrically coupling the first die 110A to the second die 110B via the BTB connection layer 112. The semiconductor package may have a first side (i.e., a top side as shown) and a second side (i.e., a bottom side as shown).

[0053] Figure 1 Illustrated is a cross-sectional view of a block diagram of a first semiconductor package having a BTB die according to one or more embodiments of the present disclosure.

[0054] Figure 1The semiconductor package 100 includes a BTB die 102. A BTB film layer 114 may be applied to each side of the BTB die 102. For example, the first side 104A of the BTB die 102 may have the first-side BTB film layer 114A, and the second side 104B of the BTB die 102 may have the second-side BTB film layer 114B. A plurality of vias 116 passing through the first-side BTB film layer 114A may connect a first plurality of traces 132 to the first die 110A of the BTB die 102. A plurality of vias 118 passing through the second-side BTB film layer 114B may connect a second plurality of traces 134 to the second die 110B of the BTB die 102.

[0055] The first plurality of traces 132 can each be electrically coupled to an associated Si block 142. Each Si block 142 can be electrically coupled to a stud 152, which is electrically coupled to a terminal 170. For example, trace 132A is electrically coupled to first die 110A and to Si block 142A through via 116A. Si block 142A is electrically coupled to stud 152C, which is electrically coupled to terminal 170C. Furthermore, trace 132B is electrically coupled to first die 110A and to Si block 142B through via 116B. Si block 142B is electrically coupled to stud 152D, which is electrically coupled to terminal 170D. Vias 116 and 118 can have one or more shapes.

[0056] The second plurality of traces 134 can each be electrically coupled to a stud 152, which is electrically coupled to a terminal 170. For example, trace 134A is electrically coupled to the second die 110B through via 118A and to stud 152A, which is electrically coupled to a terminal 170A. Furthermore, trace 134B is electrically coupled to the second die 110B through via 118B and to stud 152B, which is electrically coupled to a terminal 170B.

[0057] Although Figure 1 1 is a cross-sectional view of an example semiconductor package 100 illustrating four terminals 170 and four Si blocks 142, but it will be readily appreciated that additional terminals 170 may be electrically coupled to the first wafer 110A through the Si blocks 142 in a similar manner. Furthermore, it will be readily appreciated that additional terminals 170 may be electrically coupled to the second die 110A through the traces 134 in a similar manner. The semiconductor package 100 may be electrically connected to a larger system or device via the terminals 170.

[0058] The plastic encapsulation 120 encapsulates the BTB die 102 and its electrical connections to the terminals 170 .

[0059] Semiconductor package 100 includes a heat sink 160 on first side 104A. Heat sink 160 provides top-side intrusion protection. The sides of semiconductor package 100 are protected from intrusion attacks by the plastic package and the Si block. If traces 132, 134 or Si block 142 are damaged or disturbed, BTB die 102 will cease to function. Heat sink 160 also provides heat dissipation and EMI shielding.

[0060] In various embodiments, the films used for the BTB connection layer 112, the first-side BTB film layer 114A, and the second-side BTB film layer 114B may be made of the same material (e.g., ABF, etc.). Alternatively, the films used for one or more of the BTB connection layer 112, the first-side BTB film layer 114A, and the second-side BTB film layer 114B may be made of different materials.

[0061] In various embodiments, the studs 152 may be arranged in a fan-out pattern, where the studs 152 and the traces 132 , 134 connected to the studs may be routed outward and / or inward beyond the lateral sides of the BTB die 102 .

[0062] Figure 2A Illustrated is a cross-sectional view of a block diagram of a second semiconductor package having a BTB die according to one or more embodiments of the present disclosure. Figure 2A The semiconductor package 200A and Figure 1 The semiconductor package 200A is similar to the semiconductor package of , where the semiconductor package 200A further includes Si blocks 242A, 242A electrically coupling the heat sink 160 to the terminals 270A, 270B via the studs 282A, 282B and the studs 252A, 252B, respectively.

[0063] For example, the electrical coupling of heat sink 160 to terminals 270A, 270B provides additional protection against intrusion attacks. It also provides improved thermal management by creating a path for heat to be transferred and / or dissipated. Furthermore, it provides improved shielding for the semiconductor package by providing additional electromagnetic interference (EMI) protection.

[0064] Figure 2A Also shown is layer A, which is Figure 3 Used in association Figure 2A A cross section of an example embodiment in FIG.

[0065] Figure 2B Illustrated is a cross-sectional view of a block diagram of a third semiconductor package having a BTB die according to one or more embodiments of the present disclosure. Figure 2B The semiconductor package 200B shown in FIG. Figure 2A. However, semiconductor package 200B includes Si blocks 244A and 244B having a height different from that of Si blocks 142A and 142B. As shown, Si blocks 244A and 244B may have a height greater than that of Si blocks 142A and 142B. Alternatively, Si blocks 244A and 244B may have a height less than that of Si blocks 142A and 142B.

[0066] In various embodiments, the height of the Si block (e.g., 242 or 244) coupling the heat sink 160 to the studs 252 (e.g., 252A, 252B) can be the same as or different from the height of the Si block (e.g., 142) coupling the BTB die to the studs (e.g., 152C, 152D), and can also be offset in height. For example, this offset can provide coverage for one or more portions of the semiconductor package that might otherwise be exposed to probing by an attacker.

[0067] As will be appreciated, the various semiconductor packages 100, 200A, 200B described herein do not include bumps or wire bonds within the semiconductor package that would increase manufacturing steps. Thus, in addition to improved intrusion protection, thermal management, and shielding, the various embodiments described herein also provide increased manufacturability.

[0068] Figure 3 A top view of a cross section of a semiconductor package with a BTB die according to one or more embodiments of the present disclosure is illustrated. The top view cross section is taken along Figure 2A The image is taken by the plane indicated by A. Figure 3 The cross-section of FIG. 2 omits the mold encapsulation 120 , which would otherwise be present in the semiconductor package 200A.

[0069] As shown in the top view, semiconductor package 200A may include a plurality of traces 132A-132F. Each of the plurality of traces 132 may be electrically coupled to one or more of a plurality of input / output and / or signal pads on a die (e.g., 110A) and also electrically coupled to corresponding Si blocks 142A-142F. Additional Si blocks 282A-F may also be present that may electrically couple heat sink 160 to terminals of semiconductor package 200A.

[0070] Although Figure 3Traces 132A-132F are shown on two lateral sides of the BTB die 102 beneath the first-side BTB film layer 114A, but it will be appreciated that traces 132 may be provided in additional or fewer directions. This may include traces 132 and associated Si-blocks 142 on each side of the BTB die 102. For example, there may be six input / output pads electrically coupled to traces 132A-132E. Additionally or alternatively, Si-blocks 282 electrically coupling the heat sink 160 to the terminals 170 may also be located at various locations within the semiconductor package 200A. For example, Si-blocks 282 may be located on lateral sides of the semiconductor package and / or around the perimeter of the semiconductor package 200A to, among other things, protect against intrusion attacks from associated sides of the semiconductor package 200A.

[0071] It should be readily appreciated that the embodiments of the systems and apparatus described herein may be configured in various additional and alternative ways besides those explicitly described herein.

[0072] Exemplary Methods

[0073] Embodiments of the present disclosure include methods for making the various embodiments of the back-to-back (BTB) die semiconductor packages described herein.

[0074] In various embodiments, the semiconductor packages described herein may be manufactured separately as may multiple additional semiconductor packages, such as on a panel with panel-level packaging (PLP). It will be appreciated that while the operations described herein may relate to a panel, the operations may be performed on a panel, a wafer, etc.

[0075] Figure 4 An example flow chart illustrating operations for manufacturing a semiconductor package in accordance with one or more embodiments of the present disclosure is illustrated.

[0076] At operation 402, (one or more) BTB dies are prepared. One or more BTB dies may be prepared simultaneously. Alternatively, a single BTB die 102 may be prepared. Figure 5 and FIG. 6 describe additional operations associated with operation 402 .

[0077] At operation 404, a second side of the semiconductor package is formed. Figure 7 and Figures 8A-8Q Additional operations associated with operation 404 are described.

[0078] At operation 406, a first side of the semiconductor package is formed. Figure 9A 、 Figure 9B and Figures 10A-10X Additional operations associated with operation 406 are described.

[0079] At operation 408, the semiconductor package is finished (or completed). Figure 11 Additional operations associated with operation 402 are described.

[0080] Figure 5 Illustrated is an example flow chart of operations for preparing BTB die(s) in accordance with one or more embodiments of the present disclosure.

[0081] At operation 502, a first wafer and a second wafer are prepared. The first wafer 602A and the second wafer 602B may each contain a plurality of dies. Figure 6A ] is an illustration of an example embodiment after performing this operation.

[0082] At operation 504, the first wafer and the second wafer are back ground. The first wafer 602A and the second wafer 602B can be back ground to have a first height to be used for the BTB die. Thus, the background first wafer 610A and the background second wafer 610B can be prepared for forming the BTB die. Figure 6B ] is an illustration of an example embodiment after performing this operation.

[0083] At operation 506, a first wafer and a second wafer are mounted back-to-back to form a BTB wafer. The BTB wafer includes multiple BTB dies. The first wafer 610A and the second wafer 610B may be mounted via a BTB bonding layer 612 to form the BTB wafer. The BTB bonding layer 612 may include die attach film, glue, multiple direct bonds, and the like. Figure 6C ] is an illustration of an example embodiment after performing this operation.

[0084] At operation 508, a first lamination layer is applied to the first side of the BTB wafer. The first lamination layer 614 may include, for example, ABF or the like. Figure 6D ] is an illustration of an example embodiment after performing this operation.

[0085] At operation 510, a laminate pattern for vias is generated in the first laminate layer. The laminate pattern in the first laminate layer 614 can be generated for, for example, a plurality of vias. Each BTB die of the BTB wafer can have a plurality of vias associated therewith in the first laminate pattern. The laminate pattern can be created using one or more of laser vias, plasma etching, and back grinding of the first laminate. Figure 6E ] is an illustration of an example embodiment after performing this operation.

[0086] At operation 512, the BTB wafer is cut to prepare a plurality of BTB dies. The plurality of BTB dies in the BTB wafer may be separated from each other by cutting, etc. Cutting may separate the BTB dies from each other. Figure 6F] is an illustration of an example embodiment after performing this operation. Figure 6F A first BTB die 620A and a second BTB 620B are illustrated. It will be appreciated that the BTB wafer may include more BTB dies that are not shown.

[0087] Figure 7 An example flow chart of operations for forming a first side of a semiconductor package(s) according to one or more embodiments of the present disclosure is illustrated. Figures 8A-8Q The diagram shows the execution Figure 7 FIGURE 1 illustrates an example embodiment following the operation of FIGURE 2, which illustrates a cross-sectional view of an example block diagram associated with operations for forming a first side of a semiconductor package(s) according to one or more embodiments of the present disclosure. Figures 8A-8Q The diagram shows Figure 2A However, it will be appreciated that the operations described herein may also be used in other embodiments of the present disclosure.

[0088] At operation 702, a panel of BTB dies and Si blocks is reconstructed, wherein the first side is exposed. As described herein, embodiments may include multiple Si blocks. The BTB die and associated Si blocks (e.g., 142, 242) are positioned to expose the first side of the BTB die. The BTB die and associated Si blocks can be mounted to a carrier 810A. Mounting can utilize, for example, tape lamination and / or die mounting. The panel can be configured such that the first side of the BTB die is exposed, which first side can be the side of the BTB die opposite the laminate layer 114B. Figure 8A ] is an illustration of an example embodiment after performing this operation.

[0089] A first mold encapsulation is applied to the first side at operation 704. The mold encapsulation 120 may encapsulate the BTB die and the Si block (eg, 142, 242). Figure 8B ] is an illustration of an example embodiment after performing this operation.

[0090] At operation 706 , the first mold encapsulation is back ground. The back grinding of the mold encapsulation 120 may remove the mold encapsulation 120 to a desired height. Figure 8C ] is an illustration of an example embodiment after performing this operation.

[0091] At operation 708, the panel is released. The panel may be released from the carrier 810A. Figure 8D ] is an illustration of an example embodiment after performing this operation.

[0092] At operation 710, the panel is flipped to expose the second side.The panel may be flipped to expose the second side of the BTB die(s) of the panel. Figure 8E ] is an illustration of an example embodiment after performing this operation.

[0093] At operation 712, the panel with the second side exposed is transferred. The panel may be transferred to a second carrier 810B. The second carrier 810B may be the same as (or different from) the first carrier 810A. Transferring to the second carrier 810B may include attaching to the second carrier 810B by, for example, tape lamination and / or die attach. Figure 8F ] is an illustration of an example embodiment after performing this operation.

[0094] At operation 714 , the exposed second side is sputtered. The sputtering may utilize a sputtering material, such as Ti / Cu, etc. The sputtering may create a sputtered layer 820 . Figure 8G ] is an illustration of an example embodiment after performing this operation.

[0095] At operation 716, a first laminate layer is applied to the exposed second side. The first laminate layer of laminate 830 may cover the sputtered layer 820. The laminate may be, for example, a dry film or the like. Figure 8H FIG. 1 is an illustration of the example embodiment after performing this operation.

[0096] At operation 718, a first laminate pattern for traces is created in the first laminate layer. The first laminate pattern can be created in the first laminate layer 830 by removing one or more portions of the first laminate layer 830. For example, one or more portions of the laminate layer 830 can be removed to provide a pattern for traces, vias, and / or electrical connections to the BTB die. The first laminate layer 830 can have a pattern created by, for example, laser direct imaging (LDI). Figure 8I ] is an illustration of an example embodiment after performing this operation.

[0097] At operation 720, the exposed second side is plated. The metal plating on the exposed second side may create vias and / or traces. The metal plating may be, for example, copper. Figure 8J 8 is an illustration of an example embodiment after this operation is performed. The vias and traces are collectively shown as 832A and 832B.

[0098] A second laminate layer is applied to the exposed second side at operation 722. In some areas, the second laminate layer may be applied over the first laminate layer. Figure 8K ] is an illustration of an example embodiment after performing this operation.

[0099] At operation 724, a second lamination pattern for studs is created in the second lamination layer. The second lamination pattern can be created in the laminate of the first and second lamination layers 830. The second lamination pattern can be used, for example, for studs that will provide electrical coupling for the BTB die on the second side. Figure 8L 8 is an illustration of an example embodiment after performing this operation. In various embodiments, laminate 830 and laminate layers can be used to create patterns for fan-out semiconductor packages, where electrical connections from the semiconductor package fan out from the BTB die.

[0100] At operation 726, the exposed second side is plated. The metal plating on the exposed second side can form studs, etc. For Si blocks, studs 152, 252 can be electrically coupled to the Si block. For traces, the studs can be electrically coupled to traces 832A, 832B, which are collectively referred to as traces 834A, 834B. The metal plating can be, for example, copper. Figure 8M ] is an illustration of an example embodiment after performing this operation.

[0101] At operation 728, the laminate is peeled from the exposed second side. Peeling the laminate 830 can remove the laminate 830. For example, laminate peeling can remove a dry film laminate. Figure 8N ] is an illustration of an example embodiment after performing this operation.

[0102] At operation 730, etching is performed to remove the sputtering from the exposed second side. The etching may remove the sputtering layer 820, such as a Ti / Cu sputtering layer or the like. Figure 8O ] is an illustration of an example embodiment after performing this operation.

[0103] At operation 732, a second mold seal is applied to the exposed second side. The second mold seal may be applied to seal the second side. The second mold seal may be the same as (or may be different from) the first mold seal 120. Figure 8P ] is an illustration of an example embodiment after performing this operation.

[0104] At operation 734 , the exposed second side is back ground. Back grinding the exposed second side may remove the mold package 120 to expose external electrical connections, such as studs 152 , 252 and / or traces 834 . Figure 8Q ] is an illustration of an example embodiment after performing this operation.

[0105] Figures 9A-9B Illustrated is an example flow chart of operations for forming a second side of a semiconductor package(s) in accordance with one or more embodiments of the present disclosure. Figures 10A-10Y The diagram shows the execution Figures 9A-9B An illustration of an example embodiment following the operation of Figures 10A-10YIllustrated is a cross-sectional view of an example block diagram associated with operations for forming a second side of a semiconductor package(s) according to one or more embodiments of the present disclosure. Figures 10A-10Y The diagram shows Figure 2A However, it will be appreciated that the operations described herein may also be used in other embodiments of the present disclosure.

[0106] At operation 902, the panel is released. The panel may be released from the carrier 810B. Figure 10A ] is an illustration of an example embodiment after performing this operation.

[0107] At operation 904, the panel is flipped to expose the first side.The panel can be flipped to expose the first side of the panel, which can be associated with a first side of the BTB die(s). Figure 10B ] is an illustration of an example embodiment after performing this operation.

[0108] At operation 906, the panel with the first side exposed is transferred. The transfer of the panel may be to a carrier 1010. This may be a third carrier. In various embodiments, the carrier may be the same as (or different from) carriers 810A and / or 810B. Transferring to carrier 1010 may include attaching to carrier 1010 by, for example, tape lamination and / or die attach. Figure 10C ] is an illustration of an example embodiment after performing this operation.

[0109] At operation 908 , the exposed first side is back ground. The back grinding may remove the mold encapsulation 120 to expose the first die 110A of the BTB die. The back grinding may also reduce the height of the Si block 142 , 242 . Figure 10D ] is an illustration of an example embodiment after performing this operation.

[0110] A first laminate layer is applied to the first side at operation 910. The first laminate layer 114A may be, for example, a film such as ABF. Figure 10E ] is an illustration of an example embodiment after performing this operation.

[0111] At operation 912, a first laminate pattern for vias is generated in the first laminate layer. The first laminate pattern in the first laminate layer 114A can be generated for, for example, a plurality of vias. The BTB wafer 110A can have a plurality of vias in its associated first laminate pattern. The laminate pattern can be created using one or more of laser vias, plasma etching, and back grinding of the first laminate layer 114A. Figure 10F ] is an illustration of an example embodiment after performing this operation.

[0112] At operation 914, the exposed first side is sputtered. The sputtering may utilize a sputtering material, such as Ti / Cu, etc. The sputtering may create a sputtered layer 1020A. Figure 10G ] is an illustration of an example embodiment after performing this operation.

[0113] At operation 916, a second laminate layer is applied to the exposed first side. The second laminate layer of laminate 1030 can cover the sputtered layer 1020A. The laminate 1030 can be, for example, a dry film or the like. Figure 10H ] is an illustration of an example embodiment after performing this operation.

[0114] At operation 918, a second laminate pattern for traces is created in the second laminate layer. The second laminate pattern can be created in the second laminate layer 1030 by removing one or more portions of the second laminate layer 1030. For example, one or more portions of the laminate 1030 can be removed to provide a pattern for traces, vias, and / or electrical connections to the BTB die (particularly wafer 110A). The second laminate layer can have a pattern formed by, for example, laser direct imaging (LDI). Figure 10I ] is an illustration of an example embodiment after performing this operation.

[0115] At operation 920, the exposed first side is plated. The metal plating on the exposed first side may create vias and / or traces. The metal plating may be, for example, copper. Figure 10J ] is an illustration of an example embodiment after performing this operation.

[0116] At operation 922, a third laminate layer is applied to the exposed first side. The third laminate layer of laminate 1030 can cover the previous laminate layer(s) and / or metal plating of the vias and / or traces. Laminate 1030 can be, for example, a dry film or the like. Figure 10K ] is an illustration of an example embodiment after performing this operation.

[0117] At operation 924, a third laminate pattern for studs is generated in the third laminate layer. The third laminate pattern can be generated similarly to the generation of the second laminate pattern. For example, the third laminate pattern can remove one or more portions of the laminate 1030 to provide a pattern for studs and / or electrical connections to the Si block 242 for a heat sink. Figure 10L ] is an illustration of an example embodiment after performing this operation.

[0118] At operation 926, the exposed first side is plated. The metal plating on the exposed first side can create studs 282 (e.g., 282A, 282B) that electrically couple the heat sink and the Si block 242 (e.g., 242A, 242B). The metal plating can be, for example, copper. Figure 10M] is an illustration of an example embodiment after performing this operation.

[0119] At operation 928, the laminate is peeled from the exposed first side. Peeling the laminate 1030 can remove the laminate 1030. For example, laminate peeling can remove a dry film laminate. Figure 10N ] is an illustration of an example embodiment after performing this operation.

[0120] At operation 930, etching is performed to remove the sputtering from the exposed second side. The etching may remove the sputtering layer 1020A, such as a Ti / Cu sputtering layer or the like. Figure 10O ] is an illustration of an example embodiment after performing this operation.

[0121] At operation 932, a third mold encapsulation is applied to the exposed first side. The third mold encapsulation may be applied to encapsulate the first side, including studs (e.g., 282A, 282B) and / or electrical traces (e.g., 1032A, 1032B). The third mold encapsulation may be the same as (or different from) the first mold encapsulation 120 and / or the second mold encapsulation. Figure 10P ] is an illustration of an example embodiment after performing this operation.

[0122] At operation 934 , the mold encapsulation on the exposed first side is back ground. Back grinding the exposed first side can remove the mold encapsulation 120 to expose the studs (eg, 282A, 282B) while leaving the traces 1032A, 1032B encapsulated in the mold encapsulation 120 . Figure 10Q ] is an illustration of an example embodiment after performing this operation.

[0123] At operation 936, the exposed second side is sputtered. The sputtering may utilize a sputtering material such as Ti / Cu, etc. The sputtering may create a second sputtered layer 1020B. Figure 10R ] is an example embodiment after performing this operation.

[0124] At operation 938, a fourth lamination layer is applied to the exposed first side. The third lamination layer of the laminate 1030 can cover the second sputtered layer 1020B. The laminate 1030 can be, for example, a dry film or the like. Figure 10S ] is an illustration of an example embodiment after performing this operation.

[0125] At operation 940, a fourth laminate pattern for a heat sink is generated in the fourth laminate layer. The fourth laminate pattern can be generated similarly to the generation of the second laminate pattern. For example, the fourth laminate pattern can remove one or more portions of the laminate 1030 to provide a pattern for a heat sink and / or electrical connection to one or more studs (e.g., 282A, 282B). Figure 10T ] is an illustration of an example embodiment after performing this operation.

[0126] The exposed first side is plated at operation 942. The metal plating on the exposed first side can create a heat sink 160 electrically coupled to the studs 282 (eg, 282A, 282B). Figure 10U ] is an illustration of an example embodiment after performing this operation.

[0127] At operation 944, the laminate is peeled from the exposed first side. Peeling the laminate 1030 can remove the laminate 1030. For example, laminate peeling can remove a dry film laminate. Figure 10V ] is an illustration of an example embodiment after performing this operation.

[0128] At operation 946, etching is performed to remove the sputtering from the exposed first side. The etching may remove the sputtering layer 1020AB, such as a Ti / Cu sputtering layer or the like. Figure 10W ] is an illustration of an example embodiment after performing this operation.

[0129] At operation 948, a fourth mold is applied. The fourth mold may be applied to encapsulate the first side, including the heat sink 160. The fourth mold may (or may not) be the same material as the first mold 120, the second mold, and / or the third mold. Figure 10X ] is an illustration of an example embodiment after performing this operation.

[0130] At operation 950 , the exposed first side is back ground. Back grinding the exposed first side can remove the mold encapsulation 120 to expose the heat spreader 160 while encapsulating the remaining portion of the first side of the semiconductor package in the mold encapsulation 120 . Figure 10Y ] is an illustration of an example embodiment after performing this operation.

[0131] Figure 11 An example flow chart illustrating operations for finishing a semiconductor package in accordance with one or more embodiments of the present disclosure is illustrated.

[0132] At operation 1102 , the panel is released. The panel may be released from the carrier 1010 .

[0133] At operation 1104, a panel finishing process is applied. The panel finishing process may include applying one or more plating layers to the terminals on the first and second sides of the panel to prevent oxidation of the copper terminals. For example, the panel finishing process may include electroless nickel gold (ENIG) plating of the terminals of each semiconductor package on the panel.

[0134] At operation 1106, package component singulation is performed. Package component singulation may include singulating or dicing the panel into individual semiconductor packages.

[0135] Various operations have been described herein, and it will be appreciated that one or more of the operations may be iterated and / or repeated. For example, multiple operations described herein may be iterated to form additional traces in different layers that may be electrically coupled to additional Si blocks at various locations in the semiconductor package.

[0136] in conclusion

[0137] Although this specification contains many specific embodiments and implementation details, these should not be interpreted as limitations on the scope of any disclosure or content that may be claimed, but rather as descriptions of features of specific embodiments of specific disclosures. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Moreover, although features may be described as functioning in certain combinations and even initially claimed as such, one or more features in the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to sub-combinations or variations of sub-combinations.

[0138] Similarly, although operations are shown in a particular order in the figures, this should not be construed as requiring that these operations must be performed in the particular order shown or in the sequential order shown, or that all of the operations shown must be performed to achieve the desired results. In some cases, it may be advantageous to perform the operations in an alternative order. In some cases, the operations set forth in the claims can be performed in a different order and still achieve the desired results. Therefore, while specific embodiments of the subject matter have been described, other embodiments are within the scope of the following claims.

[0139] Although the detailed description has set forth some embodiments of the disclosure, the appended claims cover other embodiments of the disclosure according to various modifications and improvements that differ from the described embodiments.

[0140] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim, the claims are not intended to be interpreted under 35 USC §112, paragraph 6.

Claims

1. A semiconductor package, characterized in that: include: a first side of a semiconductor package and a second side of the semiconductor package, wherein the second side of the semiconductor package includes a plurality of terminals; a back-to-back die comprising a first die electrically coupled to a second die; a first die electrically coupled to a first portion of the plurality of terminals via a first plurality of electrical traces and a plurality of Si blocks; a second die electrically coupled to a second portion of the plurality of terminals via a second plurality of electrical traces; Wherein the back-to-back dies are configured to cease functioning if an electrical connection to one of the plurality of terminals is broken. 2 . The semiconductor package of claim 1 , further comprising a heat sink on the first side of the semiconductor package. 3 . The semiconductor package of claim 2 , wherein the heat sink is coupled to the one or more terminals on the second side of the semiconductor package through the one or more Si blocks. 4 . The semiconductor package of claim 1 , wherein the first die is electrically coupled to the first plurality of electrical traces using a plurality of vias passing through the first laminate layer. The semiconductor package of claim 4 , wherein the first laminate layer comprises ABF.

6. The semiconductor package of claim 1 , wherein at least one of the plurality of Si blocks is positioned on at least a first lateral side of a back-to-back die, and at least a second of the plurality of Si blocks is positioned on at least a second lateral side of the back-to-back die.

7. The semiconductor package of claim 1, wherein each lateral side of the back-to-back die has at least one Si block of the plurality of Si blocks positioned on the corresponding lateral side. 8 . The semiconductor package of claim 1 , wherein a height of a first Si block among the plurality of Si blocks is different from a height of at least a second Si block among the plurality of Si blocks.

9. The semiconductor package of claim 1, wherein the plurality of electrical traces are in a fan-out pattern. 10 . The semiconductor package of claim 1 , wherein the semiconductor package is a first semiconductor package among a plurality of semiconductor packages in a panel.

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