Package structure

Abstract

The utility model provides a packaging structure which comprises a plurality of chips which are arranged at intervals, the back faces of the chips are consistent, and the chips are packaged by a packaging material; and the plurality of heat dissipation structures are arranged on the back part of the chip at intervals and are used for conducting heat generated by the chip. Thus, the mechanical performance of the overall packaging structure is improved, each heat dissipation structure can serve as an independent heat dissipation point, and the heat dissipation efficiency of the overall packaging structure is improved. The heat dissipation structure shows high adaptability to the coefficient of thermal expansion of the chip, not only has excellent deformation tolerance so as to deal with fine deformation caused by temperature change, but also remarkably improves the strength of the whole structure. The design ensures that the heat dissipation structure can operate stably and effectively, protects the chip from being damaged by thermal stress, and prolongs the service life of the chip.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a packaging structure. Background Art

[0002] When configuring the heat sink within the package structure, thermal adhesive is placed between the chip and the heat sink. This adhesive not only acts as a thermal bridge between the two but also provides a secure connection between them. Heat generated by the chip is effectively transferred to the heat sink through this adhesive layer and then dissipated to the surrounding environment.

[0003] During this process, it is worth noting the differences in thermal conductivity between different materials. For example, the core back (chip back) material, such as silicon (Si), has a thermal conductivity coefficient of approximately 149W / m·K. However, the thermal conductivity of heat dissipation adhesives, such as aluminum oxide (Al2O3), is only 3.9W / m·K, which is significantly different from the former. The thermal conductivity of heat dissipation components, such as solid metal, is as high as approximately 86W / m·K, forming a complex heat conduction system. When heat passes from a chip with a high thermal conductivity coefficient through the heat dissipation adhesive, due to the huge difference in thermal conductivity between the two (more than 30 times), heat may accumulate at the junction, resulting in poor heat dissipation and thermal conductivity mismatch. More seriously, this heat accumulation and uneven conduction may cause the stress caused by the thermal expansion of the core back to concentrate at the junction of the chip and the heat dissipation component, thereby causing potential damage to the packaging structure and even the risk of structural rupture. Utility Model Content

[0004] The present application proposes a packaging structure.

[0005] In a first aspect, the present application provides a packaging structure, including:

[0006] A plurality of chips, wherein the plurality of chips are spaced apart and have their backs facing the same direction, and the plurality of chips are encapsulated by an encapsulation material;

[0007] A plurality of heat dissipation structures are arranged at intervals on the back of the chip and are used to conduct heat generated by the chip.

[0008] As a possible implementation, there is no actual connection between the multiple heat dissipation structures.

[0009] As a possible implementation, the multiple heat dissipation structures are arranged in an array.

[0010] As a possible implementation, the heat dissipation structure is made of metal.

[0011] As a possible implementation manner, the heat dissipation structure includes a first metal layer and a second metal layer, and the first metal layer and the second metal layer have different thicknesses and / or different crystal lattices.

[0012] As a possible implementation manner, the first metal layer is a seed layer, and the second metal layer is an electroplating layer.

[0013] As a possible implementation manner, the second metal layer is thicker than the first metal layer.

[0014] As a possible implementation manner, the gaps between the multiple heat dissipation structures are continuous grooves.

[0015] As a possible implementation method, it also includes:

[0016] A filling material is filled between the plurality of heat dissipation structures.

[0017] As a possible implementation method, it also includes:

[0018] A heat dissipation element covers the chip, and the filling material is between the chip and the heat dissipation element.

[0019] As a possible implementation manner, the multiple heat dissipation structures are between the chip and the heat dissipation element.

[0020] As a possible implementation manner, the heat dissipation structure is covered by the filling material.

[0021] As a possible implementation, part of the heat dissipation structure is a column structure.

[0022] As a possible implementation, part of the heat dissipation structure extends to the side surface of the chip.

[0023] As a possible implementation manner, the gaps between the multiple heat dissipation structures can be penetrated by infrared rays.

[0024] As a possible implementation manner, the thermal expansion coefficient of the heat dissipation structure is between the thermal expansion coefficients of the filling material and the thermal expansion coefficients of the chip back material.

[0025] As a possible implementation manner, the heat dissipation structure is made of gold, aluminum, copper, nickel, vanadium and / or alloys thereof.

[0026] As a possible implementation method, it also includes:

[0027] A substrate, on which the chip is arranged.

[0028] In order to avoid the risk of cracking caused by differences in thermal conductivity, the present application proposes a packaging structure, comprising a plurality of chips, which are spaced apart and face the same direction with their backs, and are encapsulated by a packaging material; and a plurality of heat dissipation structures, which are spaced apart on the backs of the chips and are used to conduct the heat generated by the chips. In this way, the mechanical properties of the overall packaging structure are increased, and each heat dissipation structure can serve as an independent heat dissipation point, thereby improving the heat dissipation efficiency of the overall packaging structure. The heat dissipation structure exhibits a high degree of adaptability to the thermal expansion coefficient of the chip, and not only has excellent deformation tolerance to cope with subtle deformations caused by temperature changes, but also significantly improves the strength of the overall structure. This design ensures that the heat dissipation structure can operate stably and effectively, while protecting the chip from damage caused by thermal stress and extending its service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other features, objects and advantages of the present invention will become more apparent from the detailed description of the non-limiting embodiments made with reference to the following drawings:

[0030] Figure 1 It is a structural diagram of the packaging structure of the prior art;

[0031] Figure 2 1 is a front view and a partially enlarged view of a packaging structure 100 according to an embodiment of the present invention;

[0032] Figure 3 is a side view of a packaging structure 100 according to an embodiment of the present invention;

[0033] Figure 4 1 is a top view and a partially enlarged view of a packaging structure 100 according to an embodiment of the present invention;

[0034] Figure 5 It is an infrared irradiation beam diagram for setting a single heat dissipation structure;

[0035] Figure 6 This is an infrared irradiation beam diagram of a package structure 100 provided with multiple heat dissipation structures according to an embodiment of the present invention;

[0036] Figure 7 1 is a schematic diagram of a heat dissipation structure of a packaging structure 100 according to an embodiment of the present utility model;

[0037] Figures 8-19 1 is a schematic structural diagram of a packaging structure 100 at various manufacturing stages according to an embodiment of the present invention.

[0038] Description of reference numerals / symbols:

[0039] 01-chip; 02-filling material; 03-heat dissipation structure; 04-infrared beam; 05-heat dissipation structure; 101-chip; 102-heat dissipation structure; 103-groove; 104-filling material; 105-heat dissipation element; 106-substrate; 107-infrared beam; 108-photoresist; 109-seed layer; 110-metal layer; 111-packaging material. DETAILED DESCRIPTION

[0040] The following describes the specific embodiments of the present application in conjunction with the accompanying drawings and examples. Those skilled in the art will readily understand the technical problems solved by the present application and the technical effects produced by the present application through the contents of this specification. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0041] It should be readily understood that the meanings of “on,” “over,” and “over…” in this application should be interpreted in the broadest sense, such that “on” not only means “directly on something,” but also means “on something” including intermediate components or layers therebetween.

[0042] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90° or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0043] As used herein, the term "layer" refers to a portion of a material comprising an area having a certain thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above and / or below. A layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0044] As used herein, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer. Further alternatively, the substrate can have semiconductor devices or circuits formed therein.

[0045] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in this application without affecting the efficacy and purpose that can be achieved by this application. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of this application. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of this application without substantially changing the technical content.

[0046] It should also be noted that the longitudinal section corresponding to the embodiment of the present application may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0047] In addition, the embodiments and features of the embodiments of the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0048] like Figure 1 As shown, Figure 1 It is a schematic diagram of the structure of the packaging structure of the prior art. Figure 1 The package structure shown includes:

[0049] Chip 01, heat dissipation structure 03 and filling material 02 filled between the two.

[0050] The thermal conductivity of the material on the back of chip 01 is approximately 149 W / m·K, the thermal conductivity of filler material 02 is approximately 3.9 W / m·K, and the thermal conductivity of heat dissipation structure 03 is approximately 86 W / m·K. When heat flows from chip 01 through filler material 02, due to the significant difference in thermal conductivity between the two (over 30 times), heat may accumulate at the interface, leading to poor heat dissipation and thermal conductivity mismatch. Furthermore, this heat accumulation and uneven conduction can cause stress from the thermal expansion of the back of chip 01 to concentrate at the interface between chip 01 and heat dissipation structure 03, potentially damaging the package structure and even causing the risk of structural rupture.

[0051] In order to solve the above problems, the present application proposes a packaging structure.

[0052] Combine Figure 2 、 Figure 3 、 Figure 4 , which respectively show the front view and partial enlarged view, side view, top view and partial enlarged view of the package structure 100. The package structure 100 includes:

[0053] Multiple chips 101 are arranged at intervals with their backs facing the same direction. Further, the multiple chips 101 can be packaged into a combination chip (Combination die) by packaging material 111;

[0054] A plurality of heat dissipation structures 102 are arranged at intervals on the back of the chip 101 to conduct heat generated by the chip 101 .

[0055] This improves the mechanical performance of the overall package structure 100. Each heat dissipation structure 102 can serve as an independent heat dissipation point, increasing the heat dissipation area and improving the heat dissipation efficiency of the overall package structure 100. The multiple heat dissipation structures 102 exhibit a high degree of adaptability to the thermal expansion coefficient of the chip 101. They not only have excellent deformation tolerance to cope with subtle deformations caused by temperature changes, but also significantly enhance the strength of the overall structure. This design ensures that the heat dissipation structures 102 can operate stably and effectively, while protecting the chip 101 from thermal stress damage that could cause warping or even fracture.

[0056] It should be noted that each heat dissipation structure 102 is as follows Figure 4 As shown in the enlarged image on the upper left, the heat dissipation structure 102 serves as an independent heat dissipation point, improving the heat dissipation efficiency of the chip 101. If there are multiple chips 101, heat dissipation structures 102 made of different materials can be selectively provided on the backs of the chips 101 to adapt to their thermal expansion coefficients, improve heat conduction efficiency, reduce thermal expansion deformation, and protect each chip 101 from thermal stress damage.

[0057] As a possible implementation, there is no actual connection between the multiple heat dissipation structures 102, and continuous grooves 103 can be formed between the heat dissipation structures 102 to serve as heat dissipation grooves. The specific arrangement of the heat dissipation structures 102 can be flexibly adjusted according to the actual application scenario, such as Figure 4 As shown, they are arranged in an array in an orderly manner, thereby ensuring that the groove 103 can present the following Figure 4 The enlarged image on the right shows the periodic arrangement. This design not only optimizes heat dissipation but also increases structural flexibility and adaptability.

[0058] Considering that the manufacturing process of the packaging structure usually requires infrared heating, the gaps (i.e., grooves 103) between the multiple heat dissipation structures 102 can provide an unobstructed penetration channel for infrared rays (such as lasers with a wavelength of 980nm). The infrared rays penetrate through the gaps, which not only ensures the efficient transfer of infrared energy, but also promotes the uniformity and efficiency of the heating process. Specifically, by Figure 5 The infrared irradiation beam diagram of the single heat dissipation structure is shown as well as Figure 6 As shown in the infrared irradiation beam diagram with multiple heat dissipation structures, when the heat dissipation structure 102 is single, the infrared rays will be effectively blocked due to the shielding effect of its metal material; however, when there are multiple heat dissipation structures 102 and there are certain gaps between them, the infrared rays can cleverly pass through the gaps between these heat dissipation structures 102, thereby achieving a heating effect.

[0059] As a possible implementation, the shape of the heat dissipation structure 102 can also be set as needed. For example, see Figure 2 In the enlarged view above, part of the heat dissipation structure 102 may be a columnar structure, for example Figure 7 As shown in the cylinder or prism. As an example, the base diameter a of the cylinder can be 0.5 μm and the height b can be 1 μm; the length c of the prism can be 0.5 μm, the width e can be 0.5 μm, and the height d can be 1 μm. For another example, see Figure 2 In the partially enlarged view on the left, part of the heat dissipation structure 102 can be extended to the side of the chip 101 to increase the heat conduction performance of the side.

[0060] As a possible embodiment, the material of the heat dissipation structure 102 can also be set as needed. For example, the heat dissipation structure 102 can be made of metal, such as gold, aluminum, copper, nickel, vanadium and / or their alloys. Further, it can include a first metal layer and a second metal layer. Among them, the first metal layer can be a seed layer, which lays the foundation for the entire heat dissipation structure 102, and the second metal layer can be an electroplating layer, which gives the heat dissipation structure 102 better heat dissipation performance. The material, thickness and lattice structure of the two metal layers can be set according to actual needs to maximize their performance advantages. Preferably, the thickness of the second metal layer can be set to be greater than the first metal layer, so as to ensure that the heat dissipation structure 102 maintains its structural stability and durability while dissipating heat efficiently.

[0061] As a possible implementation, package structure 100 may further include a filler material 104, which is filled between the multiple heat dissipation structures 102. The heat dissipation structures 102 are covered by the filler material 104. The provision of multiple heat dissipation structures 102 not only changes the accumulation of heat energy but also increases the contact area with the filler material 104, further improving heat dissipation efficiency. Furthermore, the provision of multiple heat dissipation structures 102 reduces the use of filler material 104, facilitating miniaturization of package structure 100.

[0062] As a possible implementation, the thermal expansion coefficient of the heat dissipation structure 102 may be between the thermal expansion coefficients of the filling material 104 and the material on the back of the chip 101 , so that the discontinuity of the heat dissipation structure 102 has a stronger deformation tolerance to the back of the chip 101 .

[0063] As a possible implementation method, it also includes:

[0064] The heat dissipation element 105 covers the chip 101. The filler material 104 and the multiple heat dissipation structures 102 are located between the chip 101 and the heat dissipation element 105. This allows heat generated by the chip 101 to be transferred first to the heat dissipation structures 102, and then from the heat dissipation structures 102 to the heat dissipation element 105. This gradual transfer of heat from different materials avoids stress accumulation caused by mismatched thermal expansion coefficients, preventing defects caused by warping.

[0065] As a possible implementation method, it also includes:

[0066] The substrate 106 , on which the chip 101 is disposed.

[0067] Refer to the following Figures 8-19 The following are the steps for manufacturing a package structure 100 according to an embodiment of the present invention:

[0068] Step 1: See Figure 8, using packaging material 111 to package the multiple chips 101 on the substrate 106 into a combined chip;

[0069] Step 2: See Figure 9 , coating photoresist 108 and exposing;

[0070] Step 3: See Figure 10 , based on the photoresist 108 , depositing a seed layer 109 ;

[0071] Step 4: See Figure 11 , based on the photoresist 108 , depositing a metal layer 110 on the seed layer 109 ;

[0072] Step 5: See Figure 12 , remove Figure 11 Photoresist 108;

[0073] Step 6: See Figure 13 , re-coating photoresist 108;

[0074] Step 7: See Figure 14 , exposing the photoresist 108;

[0075] Step 8: See Figure 15 , so that the photoresist 108 is fixed;

[0076] Step 9: See Figure 16 , based on photoresist 108, etching Figure 15 The metal layer 110 forms a plurality of heat dissipation structures 102;

[0077] Step 10: See Figure 17 , remove Figure 16 Photoresist 108;

[0078] Step 11: See Figure 18 , coating the filling material 104;

[0079] Step 12: See Figure 19 , install the heat dissipation element 105 so that the heat dissipation element 105 covers the chip 101.

[0080] As used herein, the terms "substantially," "substantial," "approximately," and "about" are used to indicate and explain minor variations. For example, when used in conjunction with a numerical value, the above terms may refer to a variation range of less than or equal to ±10% of the corresponding numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a film or layer having a thickness that is "substantially uniform" may refer to a film or layer having an average thickness that has a standard deviation of less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces that are within 50 μm along the same plane, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane. Two components may be considered "substantially aligned" if, for example, they overlap or are within 200 μm, 150 μm, 100 μm, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm. Two surfaces or components may be considered "substantially perpendicular" if the angle between them is, for example, 90° ± 10°, such as ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°. When used in conjunction with an event or circumstance, the terms "substantially," "substantial," "approximately," and "about" may refer to both situations where the event or circumstance occurs exactly and situations where the event or circumstance occurs very approximately.

Claims

1. A packaging structure, characterized in that: include: A plurality of chips, wherein the plurality of chips are spaced apart and have their backs facing the same direction, and the plurality of chips are encapsulated by an encapsulation material; A plurality of heat dissipation structures are arranged at intervals on the back of the chip and are used to conduct heat generated by the chip.

2. The packaging structure according to claim 1, wherein: There is no actual connection between the multiple heat dissipation structures.

3. The packaging structure according to claim 1, wherein: The multiple heat dissipation structures are arranged in an array.

4. The packaging structure according to claim 1, wherein: The heat dissipation structure is made of metal.

5. The packaging structure according to claim 1, wherein: The heat dissipation structure includes a first metal layer and a second metal layer, and the thickness of the second metal layer is greater than that of the first metal layer.

6. The packaging structure according to claim 1, wherein: The gaps between the multiple heat dissipation structures are continuous grooves.

7. The packaging structure according to claim 1, wherein: Also includes: A filling material is filled between the plurality of heat dissipation structures.

8. The packaging structure according to claim 7, wherein: Also includes: A heat dissipation element covers the chip, and the filling material is between the chip and the heat dissipation element.

9. The packaging structure according to claim 8, wherein: The plurality of heat dissipation structures are between the chip and the heat dissipation element.

10. The packaging structure according to claim 7, wherein: The heat dissipation structure is covered by the filling material.

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