Overvoltage protection device and inverter

Abstract

The utility model discloses an overvoltage protection device. The overvoltage protection device comprises an overvoltage detection unit; the overvoltage latch unit comprises a first output end and a first input end connected with the overvoltage detection unit, and when the first input end receives the low level, the first output end outputs the low level; otherwise, the first output end outputs high level; the delay unit is connected with the first output end and is used for outputting a low level after delay time is set; the AND gate circuit comprises a second input end and a second output end, and when the second input end receives the low level output by the first output end or the low level output by the delay unit, the second output end turns off the upper bridge switch; and the OR gate circuit comprises a third input end and a third output end, and when the second input end receives the low level output by the first output end and the low level output by the delay unit, the third output end enables the lower bridge switch to be switched on. According to the utility model, the time required for the inverter to enter the ASC safety state can be shortened. The utility model also provides an inverter.

Description

Technical Field

[0001] The utility model relates to the field of inverters, in particular to an overvoltage protection device and an inverter. Background Art

[0002] An inverter converts direct current (DC) into alternating current (AC). When an inverter experiences an overvoltage fault—that is, the voltage of the inverter's DC bus exceeds the normal operating voltage—it must be controlled to enter the ASC (active short circuit) safety state to prevent overvoltage current from damaging components such as the inverter's IGBTs (Insulated Gate Bipolar Transistors). ASC is a protection strategy used to protect circuits from overcurrent damage during short-circuit conditions. In an inverter, the ASC safe operating state is achieved by turning off the IGBT switches in the inverter's upper arm and turning on the IGBT switches in the inverter's lower arm.

[0003] In the prior art, when performing a high-voltage overvoltage protection test on an inverter, the overvoltage fault is identified by software, and after software processing, a PWM (Pulse Width Modulation) signal is sent to the driver chip to control the on and off of the IGBT of the inverter. However, the software response time required for the above process is relatively long. During the response time of the software identifying and processing the fault signal, the overvoltage current will damage the IGBT and other components of the inverter. Therefore, it is necessary to shorten the time required for the inverter to enter the ASC safety state from the occurrence of the overvoltage fault to the occurrence of the inverter as much as possible. Utility Model Content

[0004] The purpose of the present invention is to solve the problem of how to prevent overvoltage faults from damaging the components of the inverter. The present invention provides an overvoltage protection device that can shorten the time required from the occurrence of an overvoltage fault in the inverter to the inverter entering the ASC safe state.

[0005] In order to solve the above technical problems, the embodiment of the present utility model discloses an overvoltage protection device, comprising:

[0006] an overvoltage detection unit, configured to detect the voltage of the inverter, and output a low level when the voltage of the inverter is higher than a preset value;

[0007] an overvoltage latch unit, comprising a first input terminal and a first output terminal, wherein the first input terminal is connected to the overvoltage detection unit, and when the first input terminal receives the low level, the first output terminal outputs the low level;

[0008] a delay unit connected to the first output terminal and configured to output the low level after a set delay time;

[0009] An AND gate circuit, comprising a second input terminal and a second output terminal, the delay unit and the first output terminal being connected in parallel to the second input terminal, the second output terminal being used to be connected to an upper bridge switch of the inverter, and when the second input terminal receives a low level output by the first output terminal or a low level output by the delay unit, the upper bridge switch is turned off;

[0010] An OR gate circuit includes a third input terminal and a third output terminal, the delay unit and the first output terminal are connected in parallel to the third input terminal, the third output terminal is used to be connected to the lower bridge switch of the inverter, when the second input terminal receives the low level output by the first output terminal and the low level output by the delay unit, the lower bridge switch is turned on, otherwise the lower bridge switch is in the off state.

[0011] By adopting the above technical solution, the overvoltage detection unit is used to monitor whether the voltage of the inverter is overvoltage. When the voltage of the inverter is higher than the preset value, the overvoltage detection unit outputs a low level to the overvoltage latch unit. The overvoltage latch unit can ensure that the first output end stably outputs a low level. At this time, the second input end of the AND gate circuit receives the low level output by the first output end, and the second output end outputs a low level to turn off the upper bridge switch. The second input end of the OR gate circuit needs to receive the low levels output by the first output end and the delay unit at the same time after a set delay time. Only then will the second output end output a low level to turn on the lower bridge switch. During the set delay time, both the upper bridge switch and the lower bridge switch are in the off state, which can prevent overvoltage current from damaging components.

[0012] This solution uses hardware circuits to prevent overvoltage faults from damaging the inverter's components. The response time of the hardware circuit is much shorter than the response time of software processing. Therefore, it can shorten the time required from the occurrence of an overvoltage fault in the inverter to the inverter entering the ASC safe state, thereby improving the safety performance of the inverter.

[0013] According to another specific embodiment of the present invention, an embodiment of the present invention discloses an overvoltage protection device, wherein the overvoltage detection unit includes a high-voltage detection module and a high-voltage comparison module, the high-voltage detection module is used to connect to the inverter and transmit the high-voltage signal of the inverter to the high-voltage comparison module, when the high-voltage comparison module detects that the voltage of the high-voltage signal is greater than a set value, the high-voltage comparison module outputs the low level.

[0014] According to another specific embodiment of the present invention, an embodiment of the present invention discloses an overvoltage protection device, wherein the delay unit includes an RC circuit and a Schmitt trigger, the RC circuit is arranged between the first output end and the Schmitt trigger, and when the output voltage of the RC circuit reaches the first threshold of the Schmitt trigger after the delay time, the Schmitt trigger outputs a low level.

[0015] By adopting the above technical solution, the delay time is determined by the RC circuit and the Schmitt trigger, which is low in cost and can adjust the delay time by adjusting the parameters such as the resistance and capacitance of the RC circuit.

[0016] According to another specific embodiment of the present invention, an embodiment of the present invention discloses an overvoltage protection device, wherein the set time is 4 microseconds.

[0017] The above technical solution can avoid the damage of the inverter components due to overvoltage and current caused by a long delay time.

[0018] According to another specific embodiment of the present invention, an embodiment of the present invention discloses an overvoltage protection device, the overvoltage latch unit includes a trigger input end, the overvoltage protection device includes a single-chip microcomputer, and when the trigger input end receives a fault clearing instruction issued by the single-chip microcomputer, the first output end outputs a high level.

[0019] With the above technical solution, when the inverter operates normally after the fault is eliminated, it is necessary to send a fault clearing instruction to the trigger input terminal through the single chip microcomputer to avoid affecting the normal use of the inverter and improve work efficiency.

[0020] According to another specific embodiment of the present invention, an embodiment of the present invention discloses an overvoltage protection device, wherein the overvoltage latch unit includes a D trigger, the first input end is the RD end, the first output end is the Q end, and the trigger input end is the CP input end.

[0021] By adopting the above technical solution, the low-level signal output by the overvoltage detection unit after detecting an overvoltage fault is latched by the D flip-flop, so that the Q end can output a low level stably without interference.

[0022] According to another specific embodiment of the present invention, an overvoltage protection device is disclosed, comprising:

[0023] a first multiplexer, the first multiplexer comprising a fourth input terminal, a fourth output terminal, and a fifth input terminal, the fourth input terminal being connected to the second output terminal, the fifth input terminal being used to be connected to a single-chip microcomputer, and the fourth output terminal being used to be connected to the upper bridge switch;

[0024] a second multiplexer, the second multiplexer comprising a sixth input terminal, a sixth output terminal, and a seventh input terminal, the sixth input terminal being connected to the third output terminal, the seventh input terminal being used to be connected to the single-chip microcomputer, and the sixth output terminal being used to be connected to the lower bridge switch;

[0025] When the first output terminal outputs a low level, the output signal of the fourth output terminal is the same as the input signal of the fourth input terminal, and the output signal of the sixth output terminal is the same as the input signal of the sixth input terminal;

[0026] When the first output terminal outputs a high level, the output signal of the fourth output terminal is the same as the input signal of the fifth input terminal, and the output signal of the sixth output terminal is the same as the input signal of the seventh input terminal.

[0027] By adopting the above technical solution, it is possible to switch between PWM output in normal state and PWM output in ASC state. Without affecting the normal use of the inverter, it is possible to shorten the time required from the occurrence of an overvoltage fault of the inverter to the inverter entering the ASC safe state.

[0028] The present invention also discloses an inverter comprising at least the overvoltage protection device of any of the above embodiments. The inverter comprises an upper bridge switch and a lower bridge switch, wherein the upper bridge switch is connected to the second output terminal of the AND gate circuit, and the lower bridge switch is connected to the third output terminal of the OR gate circuit.

[0029] By adopting the above technical solution, the safety performance of the inverter can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A circuit diagram of an inverter including an overvoltage protection device provided in an embodiment of the present application is shown.

[0031] Figure 2 A module schematic diagram of the overvoltage protection device provided in an embodiment of the present application is shown.

[0032] Figure 3 A schematic diagram of a module of an overvoltage protection device provided in an embodiment of the present application including a single chip microcomputer is shown.

[0033] Figure 4 A schematic diagram of a circuit module of an overvoltage protection device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] The following is an explanation of the implementation of the present invention by means of specific specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this utility model are limited to this implementation. On the contrary, the purpose of introducing the utility model in conjunction with the implementation is to cover other options or modifications that may be extended based on the claims of the present invention. In order to provide an in-depth understanding of the present invention, the following description will contain many specific details. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0035] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0036] In the description of this embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the utility model product is usually placed when in use. They are only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as a limitation on the utility model.

[0037] The terms “first”, “second”, etc. are only used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0038] In the description of this embodiment, it should be noted that, unless otherwise specified or limited, the terms "disposed," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this embodiment based on specific circumstances.

[0039] In order to make the purpose, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0040] In some embodiments, see Figure 1The present application provides an inverter, including an overvoltage protection device 10, an upper bridge driver chip 20, a lower bridge driver chip 30, an upper bridge switch 40, and a lower bridge switch 50. The upper bridge driver chip 20 and the lower bridge driver chip 30 are connected in parallel to the overvoltage protection device 10, and the upper bridge driver chip 20 is connected in series with the upper bridge switch 40 to control the upper bridge switch 40 to be turned on at a high level and turned off at a low level. The lower bridge driver chip 30 is connected in series with the lower bridge switch 50 to control the lower bridge switch 50 to be turned on at a low level and turned off at a high level. The upper bridge driver chip 20 and the lower bridge driver chip 30 are both gate drivers (GDA, Gate Drive Unit), and the upper bridge switch 40 and the lower bridge switch 50 are both IGBT switch tubes.

[0041] In some embodiments, see Figure 2 、 Figure 3 The overvoltage protection device 10 includes an overvoltage detection unit 11, an overvoltage latch unit 12, a delay unit 13, an AND gate circuit 14, an OR gate circuit 15, a first multiplexer 16, and a second multiplexer 17. The overvoltage detection unit 11 has a high-voltage input terminal 111, which is connected to the inverter bus and is used to detect the inverter bus voltage. When the inverter voltage is higher than a preset value, the overvoltage detection unit 11 outputs a low level. The overvoltage latch unit 12 includes a first input terminal 121 and a first output terminal 122. The first input terminal 121 is connected to the overvoltage detection unit 11. When the first input terminal 121 receives a low level, the first output terminal 122 outputs a low level.

[0042] The delay unit 13 is connected to the first output terminal 122 and is configured to output a low level after a set delay time. The AND gate circuit 14 includes a second output terminal 142 and two second input terminals 141. The delay unit 13 is connected in parallel with the first output terminal 122 and the second input terminal 141. The second output terminal 142 is configured to connect to the inverter's upper bridge switch 40. When the second input terminal 141 receives a low level output from the first output terminal 122 or a low level output from the delay unit 13, the upper bridge switch 40 is turned off. The OR gate circuit 15 includes a third output terminal 152 and two third input terminals 151. The delay unit 13 is connected in parallel with the first output terminal 122 and the third input terminal 151. The third output terminal 152 is configured to connect to the inverter's lower bridge switch 50. When the second input terminal 141 receives a low level output from the first output terminal 122 and a low level output from the delay unit 13, the lower bridge switch 50 is turned on. Otherwise, the lower bridge switch 50 remains off.

[0043] With the above technical solution, the overvoltage detection unit 11 is used to monitor whether the voltage of the inverter is overvoltage. When the voltage of the inverter is higher than a preset value, the overvoltage detection unit 11 outputs a low level to the overvoltage latch unit 12. The overvoltage latch unit 12 can ensure that the first output terminal 122 stably outputs a low level. At this time, the second input terminal 141 of the AND gate circuit 14 receives the low level output by the first output terminal 122, and the second output terminal 142 outputs a low level to turn off the upper bridge switch 40. The second input terminal 141 of the OR gate circuit 15 needs to receive the low levels output by the first output terminal 122 and the delay unit 13 at the same time after a set delay time. Only then will the second output terminal 142 output a low level to turn on the lower bridge switch 50. During the set delay time, both the upper bridge switch 40 and the lower bridge switch 50 are in the off state, which can prevent overvoltage current from damaging components.

[0044] In some embodiments, see Figure 2 、 Figure 3 、 Figure 4 The overvoltage detection unit 11 includes a high voltage detection module ( Figure 4 HVMeasurementCircuit) and high voltage comparison module ( Figure 4 The high voltage detection module is used to connect with the inverter and transmit the high voltage signal of the inverter to the high voltage comparison module. When the high voltage comparison module detects that the voltage of the high voltage signal is greater than the set value, the high voltage comparison module outputs a low level. For example, the high voltage comparison module includes a comparator. After the high voltage detection module transmits the collected bus voltage signal to the comparator, the comparator compares the voltage signal value of the bus current with the set value ( Figure 4 When the voltage signal value of the bus current is greater than the reference voltage value, the comparator outputs a low level, that is, the comparator outputs a fault signal ( Figure 4 / FOV FAULT).

[0045] In some embodiments, see Figure 2 、 Figure 3 、 Figure 4 The overvoltage latch unit 12 includes a trigger input terminal 123, and the overvoltage protection device includes a single chip microcomputer 18 ( Figure 4 MCU, Microcontroller Unit), when the trigger input terminal 123 receives the fault clearing instruction ( Figure 4 CLR in When the inverter is operating normally after the fault is eliminated, the single chip microcomputer 18 needs to send a fault clearing instruction to the trigger input terminal 123, which changes the potential of the trigger input terminal 123 from a low level to a high level, so that the first output terminal 122 outputs a high level.

[0046] For example, see Figure 2 、 Figure 3 、 Figure 4 The overvoltage latch unit 12 includes a D flip-flop, with a first input terminal 121 being the RD terminal (reset signal input terminal), a first output terminal 122 being the Q terminal, and a trigger input terminal 123 being the CP input terminal. The D flip-flop also includes an SD terminal (direct set input terminal) and a D terminal (control signal input terminal). When a low level input is received at the RD terminal and a high level input is received at the SD terminal, the Q terminal outputs a low level. At this time, the CP terminal and the D terminal can be either low or high, without affecting the low level output of the Q terminal, thereby latching the fault signal, i.e., latching the low level signal output by the overvoltage detection unit 11 after detecting an overvoltage fault. When the microcontroller 18 issues a fault clear instruction to the trigger input terminal 123, even if the potential of the trigger input terminal 123 changes from a low level to a high level, the potential state of the D terminal of the D flip-flop is the same as the potential state of the Q terminal, causing the Q terminal to output a high level.

[0047] In some embodiments, see Figure 2 、 Figure 3 、 Figure 4 The delay unit 13 includes an RC circuit 131 and a Schmitt trigger 132. The RC circuit 131 is provided between the first output terminal 122 and the Schmitt trigger 132. When the output voltage of the RC circuit 131 reaches the first threshold of the Schmitt trigger 132 after the delay time, the Schmitt trigger 132 outputs a low level. Exemplarily, the RC circuit 131 includes a resistor 1311 and a capacitor 1312 connected in series. One end of the capacitor 1312 is grounded. Under given conditions of the resistor 1311 and the capacitor 1312, the capacitor 1312 will gradually charge or discharge through the resistor 1311, thereby causing the output response of the RC circuit 131 to change. When the output response change of the RC circuit 131 reaches the first threshold of the Schmitt trigger 132, the Schmitt trigger 132 outputs a low level.

[0048] For example, the delay time is set to 4 microseconds. It is understandable that by adjusting parameters such as the resistor 1311, the capacitor 1312, and the power, the set delay time can be controlled to achieve the desired delay effect. This application does not limit the set delay time, and for example, it can also be 2 microseconds, 3 microseconds, 5 microseconds, etc.

[0049] In some embodiments, see Figure 2 、 Figure 3 、 Figure 4 The first multiplexer 16 includes a fourth input terminal 161, a fourth output terminal 162, and a fifth input terminal 163. The second output terminal 142 is connected to the fourth input terminal 161, the fifth input terminal 163 is used to connect to the single-chip microcomputer 18, and the fourth output terminal 162 is used to connect to the upper bridge switch 40. The second multiplexer 17 includes a sixth input terminal 171, a sixth output terminal 172, and a seventh input terminal 173. The third output terminal 152 is connected to the sixth input terminal 171, the seventh input terminal 173 is used to connect to the single-chip microcomputer 18, and the sixth output terminal 172 is used to connect to the lower bridge switch 50. Exemplarily, both the first multiplexer 16 and the second multiplexer 17 include a SELECT terminal, which is connected to the first output terminal 122.

[0050] When the first output terminal 122 outputs a low level, the SELECT terminal is a low level input, the output signal of the fourth output terminal 162 is the same as the input signal of the fourth input terminal 161, and the output signal of the sixth output terminal 172 is the same as the input signal of the sixth input terminal 171; when the first output terminal 122 outputs a high level, the SELECT terminal is a high level input, the output signal of the fourth output terminal 162 is the same as the input signal of the fifth input terminal 163, and the output signal of the sixth output terminal 172 is the same as the input signal of the seventh input terminal 173.

[0051] For example, the AND gate circuit 14 includes two second input terminals 141, one of which is connected to the first output terminal 122, and the other is connected to the Schmitt trigger 132. For the AND gate circuit 14, the circuit output is high only when all input terminals are high, otherwise the output is low. Therefore, when the second input terminal 141 receives the low level output by the first output terminal 122, the second output terminal 142 immediately switches the / SFY between the second output terminal 142 and the fourth input terminal 161 to the / SFY _ The H signal becomes a low-level signal.

[0052] The OR gate circuit 15 includes two third input terminals 151, one of which is connected to the first output terminal 122, and the other is connected to the Schmitt trigger 132. For the OR gate circuit 15, as long as one of the inputs is at a high level, the output is at a high level; only when all the inputs are at a low level, the output is at a low level. Therefore, only after a set delay time, when the third input terminal 151 receives the low level output of the first output terminal 122 and the Schmitt trigger 132, the second output terminal 142 will switch the / SFY between the second output terminal 142 and the fourth input 161. _ The potential of the L signal becomes a low level.

[0053] In some embodiments, see Figure 2 、 Figure 3 、 Figure 4 The fourth output terminal 162 of the first multiplexer 16 includes a 1Y output terminal, a 2Y output terminal, and a 3Y output terminal, which respectively correspond to the output PWM _ UH _ FB, PWM _ VH _ FB, PWM _ WH _ The FB control signal is sent to the upper bridge switch 40 of the inverter. The fourth input terminal 161 of the first multiplexer 16 includes the 1B input terminal, the 2B input terminal, and the 3B input terminal. When the inverter enters the ASC safety state, the PWM output of the fourth output terminal 162 is UH FB, PWM VH FB, PWM WH The FB control signal potential is the same as that of the 1B input terminal, 2B input terminal, and 3B input terminal, that is, when / SFY _ When the potential of the H signal is low, PWM UH FB, PWM VH FB, PWM WH The potential of the FB control signal is also at a low level, turning off the high bridge switch 40 .

[0054] The fifth input terminal 163 of the first multiplexer 16 includes a 1A input terminal, a 2A input terminal, and a 3A input terminal for receiving the normal PWM output signal of the single chip microcomputer 18, which are MCU _ PWM _ UH、MCU _ PWM _ VH、MCU PWM WH, when / SFY _ When the potential of the H signal is high, the inverter does not have an overvoltage fault and does not need to enter the ASC safety state. Therefore, the PWM signal output by the single chip microcomputer 18 controls the normal operation of the inverter. The PWM signal output by the fourth output terminal 162 is UH FB, PWM VH FB, PWM WH The potential of the FB control signal is the same as that of the 1A input terminal, 2A input terminal, and 3A input terminal.

[0055] In some embodiments, see Figure 2 、 Figure 3 、 Figure 4 The sixth output terminal 172 of the second multiplexer 17 includes a 1Y output terminal, a 2Y output terminal, and a 3Y output terminal, which respectively correspond to the output PWM _ UL _ FB, PWM _ VL _ FB, PWM WL The FB control signal is sent to the lower bridge switch 50 of the inverter. The sixth input terminal 171 of the second multiplexer 17 includes the 1B input terminal, the 2B input terminal, and the 3B input terminal. When the inverter enters the ASC safety state, the PWM output of the sixth output terminal 172 is UL FB, PWM VL FB, PWM WL The FB control signal potential is the same as that of the 1B input terminal, 2B input terminal, and 3B input terminal, that is, when / SFY _ When the potential of the L signal is low, the PWM _ UL _ FB, PWM _ VL _ FB, PWM WL The potential of the FB control signal is also at a low level, turning on the low bridge switch 50 .

[0056] The seventh input terminal 173 of the second multiplexer 17 includes a 1A input terminal, a 2A input terminal, and a 3A input terminal for receiving the normal PWM output signal of the single chip microcomputer 18, which are MCU _ PWM _ UL, MCU _ PWM _ VL、MCU _ PWM _ WL, when / SFY _ When the potential of the L signal is high, the inverter does not have an overvoltage fault and does not need to enter the ASC safety state. Therefore, the PWM signal output by the single chip microcomputer 18 controls the normal operation of the inverter. The PWM signal output by the sixth output terminal 172 is _ UL _ FB, PWM _ VL _ FB, PWM _ WL _ The potential of the FB control signal is the same as that of the 1A input terminal, 2A input terminal, and 3A input terminal.

[0057] The above technical solution makes full use of the characteristic of the multiplexer (or mux) that it can select a signal from multiple analog or digital input signals and forward it, and output different selected signals to the same output line to achieve switching between PWM output in normal state and PWM output in ASC state. Without affecting the normal use of the inverter, it can shorten the time required from the occurrence of an overvoltage fault of the inverter to the inverter entering the ASC safe state.

[0058] Table 1 is a circuit truth table of the overvoltage protection device provided by the present application. In Table 1, H represents a high level, L represents a low level, X represents that neither a high level nor a low level affects the truth value, ↑ represents a positive transition from a low level to a high level, Inputs A represents 1A input terminal, 2A input terminal, and 3A input terminal, Inputs B represents 1B input terminal, 2B input terminal, and 3B input terminal, Outputs Y represents 1Y output terminal, 2Y output terminal, and 3Y output terminal. According to Table 1 and the combination thereof, Figure 4 It can be seen that when the RD terminal is low, the Q terminal and the SELECT terminal are both low, the true value of Outputs Y is the same as the true value of Inputs B, and the inverter is in the SC safe state. When the overvoltage fault is eliminated and the inverter needs to operate normally, the RD terminal is high. At this time, the microcontroller 18 causes the CP terminal to transition from low to high, making the Q terminal high and the SELECT terminal also high. At this time, the true value of Outputs Y is the same as the true value of Inputs A, and the inverter operates normally.

[0059] Table 1 (Circuit truth table of overvoltage protection device)

[0060]

[0061] Although the present invention has been illustrated and described with reference to certain preferred embodiments of the present invention, it should be understood by those skilled in the art that the above description is provided to further illustrate the present invention in conjunction with specific embodiments, and that the present invention should not be construed as being limited to these descriptions. Those skilled in the art may make various changes in form and detail, including simple deductions or substitutions, without departing from the spirit and scope of the present invention.

Claims

1. An overvoltage protection device, characterized in that: include: an overvoltage detection unit, configured to detect the voltage of the inverter, and output a low level when the voltage of the inverter is higher than a preset value; an overvoltage latch unit, comprising a first input terminal and a first output terminal, wherein the first input terminal is connected to the overvoltage detection unit, and when the first input terminal receives the low level, the first output terminal outputs the low level; a delay unit connected to the first output terminal and configured to output the low level after a set delay time; An AND gate circuit, comprising a second input terminal and a second output terminal, the delay unit and the first output terminal being connected in parallel to the second input terminal, the second output terminal being used to be connected to an upper bridge switch of the inverter, and when the second input terminal receives a low level output by the first output terminal or a low level output by the delay unit, the upper bridge switch is turned off; An OR gate circuit includes a third input terminal and a third output terminal, the delay unit and the first output terminal are connected in parallel to the third input terminal, the third output terminal is used to be connected to the lower bridge switch of the inverter, when the second input terminal receives the low level output by the first output terminal and the low level output by the delay unit, the lower bridge switch is turned on, otherwise the lower bridge switch is in the off state.

2. The overvoltage protection device according to claim 1, characterized in that: The overvoltage detection unit includes a high-voltage detection module and a high-voltage comparison module. The high-voltage detection module is used to connect to the inverter and transmit the high-voltage signal of the inverter to the high-voltage comparison module. When the high-voltage comparison module detects that the voltage of the high-voltage signal is greater than a set value, the high-voltage comparison module outputs the low level.

3. The overvoltage protection device according to claim 1, characterized in that: The delay unit includes an RC circuit and a Schmitt trigger. The RC circuit is arranged between the first output terminal and the Schmitt trigger. When the output voltage of the RC circuit reaches the first threshold of the Schmitt trigger after the delay time, the Schmitt trigger outputs a low level.

4. The overvoltage protection device according to claim 3, characterized in that: The set delay time is 4 microseconds.

5. The overvoltage protection device according to claim 1, wherein: The overvoltage latch unit includes a trigger input terminal, and the overvoltage protection device includes a single-chip microcomputer. When the trigger input terminal receives a fault clearing instruction issued by the single-chip microcomputer, the first output terminal outputs a high level.

6. The overvoltage protection device according to claim 5, characterized in that: The overvoltage latch unit includes a D trigger, the first input terminal is the RD terminal, the first output terminal is the Q terminal, and the trigger input terminal is the CP input terminal.

7. The overvoltage protection device according to claim 1, wherein: The overvoltage protection device comprises: a first multiplexer, the first multiplexer comprising a fourth input terminal, a fourth output terminal, and a fifth input terminal, the fourth input terminal being connected to the second output terminal, the fifth input terminal being used to be connected to a single-chip microcomputer, and the fourth output terminal being used to be connected to the upper bridge switch; a second multiplexer, the second multiplexer comprising a sixth input terminal, a sixth output terminal, and a seventh input terminal, the sixth input terminal being connected to the third output terminal, the seventh input terminal being used to be connected to the single-chip microcomputer, and the sixth output terminal being used to be connected to the lower bridge switch; When the first output terminal outputs a low level, the output signal of the fourth output terminal is the same as the input signal of the fourth input terminal, and the output signal of the sixth output terminal is the same as the input signal of the sixth input terminal; When the first output terminal outputs a high level, the output signal of the fourth output terminal is the same as the input signal of the fifth input terminal, and the output signal of the sixth output terminal is the same as the input signal of the seventh input terminal.

8. An inverter, characterized in that: The overvoltage protection device comprises the overvoltage protection device according to any one of claims 1 to 7, wherein the inverter comprises an upper bridge switch and a lower bridge switch, the upper bridge switch is connected to the second output terminal of the AND gate circuit, and the lower bridge switch is connected to the third output terminal of the OR gate circuit.

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