High-efficiency DCDC power converter with peak-valley current control type soft switching

Abstract

The utility model provides a peak-valley current control type soft switching high-efficiency DCDC power supply converter. The peak-valley current control type soft switching high-efficiency DCDC power supply converter comprises a current sampling circuit, a current comparison circuit, a voltage sampling circuit, a logic circuit, a first switching tube driving circuit, a second switching tube driving circuit, a zero cross detection circuit and a power circuit. The current sampling circuit collects the current size and direction of the power circuit; the voltage acquisition circuit provides an upper limit reference current and a lower limit reference current, and the current comparison circuit is used for comparing the acquired inductive current with the upper limit reference current and the lower limit reference current respectively; and the logic circuit controls the on-off of the first switching tube driving circuit and the second switching tube according to the comparison result. By using the soft switching power supply, the conversion efficiency of the switching power supply is improved, the loss is reduced, the heating is reduced, the overheat risk of the switching tube is reduced, the service life of the power supply is prolonged, and the power supply is energy-saving and environment-friendly.

Description

Technical Field

[0001] The utility model relates to the field of power electronics, and more specifically to a peak-valley current controlled soft-switching high-efficiency DCDC power converter. Background Art

[0002] VICOR's ZVS BUCK-BOOST technology currently uses the junction capacitance of the MOSFET to allow current to flow through the capacitor at the moment of shutdown, making Ids almost zero to achieve ZCS soft switching and reduce turn-off power loss. The control circuit detects when the voltage across the MOSFET crosses zero and turns on to achieve ZVS, thereby reducing conduction power loss.

[0003] The current circuit requires the use of expensive high-frequency MOSFETs; the junction capacitance of the MOSFET is fully used to absorb the large current during shutdown, but the capacity is insufficient to reduce a large amount of switching losses. The structure of the control circuit is complex, and the dead zone control of the switch is difficult; the use of non-isolated bootstrap drive can easily cause the power circuit to interfere with the control circuit if the design is not good; the control circuit requires complex digital and software control, which is difficult to design and has high cost. Summary of the Invention

[0004] The utility model aims to solve the technical problems existing in the prior art and provides a peak-valley current controlled soft switching high-efficiency DCDC power converter, which can reduce the conduction loss power of the switch tube.

[0005] The utility model provides a peak-valley current controlled soft-switching high-efficiency DCDC power converter, comprising a current sampling circuit, a current comparison circuit, a voltage sampling circuit, a logic circuit, a first switch tube drive circuit, a second switch tube drive circuit, a zero-crossing detection circuit and a power circuit;

[0006] The current sampling circuit collects the current magnitude and direction of the power circuit and inputs the data into the current comparison circuit;

[0007] The voltage sampling circuit is used to provide an upper limit reference current and a lower limit reference current for the current comparison circuit;

[0008] The current comparison circuit is used to compare the collected inductor current with the upper limit reference current and the lower limit reference current respectively, and transmit the comparison result to the logic circuit;

[0009] The logic circuit performs logic processing on the comparison result and transmits the result to the first switch tube driving circuit and the second switch tube driving circuit respectively, so as to control the on and off of the first switch tube driving circuit and the second switch tube;

[0010] The zero-crossing detection circuit performs zero-crossing detection on the first switch tube driving circuit and the second switch tube driving circuit respectively.

[0011] The utility model provides a peak-valley current controlled soft-switching high-efficiency DCDC power converter. The switch tube of the soft-switching power supply operates in a completely soft-switching state. The capacitor absorbs and stores the impact energy at the switching moment, which significantly reduces the loss of the switch tube at the switching moment. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a circuit schematic diagram of a peak-valley current controlled soft switching high-efficiency DCDC power converter provided by the utility model. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be arbitrarily combined with each other to form a feasible technical solution. This combination is not restricted by the order of steps and / or structural composition mode, but must be based on the ability of ordinary technicians in this field to implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0014] Figure 1 The utility model provides a peak-valley current controlled soft switching high efficiency DCDC power converter, such as Figure 1 As shown, the DCDC power converter mainly includes a current sampling circuit 1, a current comparison circuit 2, a voltage sampling circuit 3, a logic circuit 4, a first switch tube drive circuit 5, a second switch tube drive circuit 6, a zero-crossing detection circuit 7 and a power circuit.

[0015] Among them, the current sampling circuit 1 collects the current magnitude and direction of the power circuit and inputs it into the current comparison circuit 2; the voltage sampling circuit 3 is used to provide the upper limit reference current and the lower limit reference current for the current comparison circuit 2; the current comparison circuit 2 is used to compare the collected inductor current with the upper limit reference current and the lower limit reference current, respectively, and transmit the comparison result to the logic circuit 4; the logic circuit 4 performs logical processing on the comparison result and transmits it to the first switch tube drive circuit 5 and the second switch tube drive circuit 6, respectively, to control the on and off of the first switch tube drive circuit 5 and the second switch tube 6; the zero crossing detection circuit 7 performs zero crossing detection on the first switch tube drive circuit 5 and the second switch tube drive circuit 6, respectively.

[0016] Exemplarily, the power circuit includes an inductor L1, a shunt resistor R5, a capacitor C1, a capacitor C2, a switch Q1, a capacitor C5, a switch Q2, and a capacitor C6, wherein the models of the switch Q1 and the switch Q2 are IRFP064 or P75NF75. One end of the inductor L1 is connected to the current sampling circuit 1 via the shunt resistor R5, and the other end of the inductor L1 is connected to the source of the switch Q1 via the capacitor C2 and the capacitor C1. The gate of the switch Q1 is connected to the first switch driver circuit 5, the drain of the switch Q1 is connected to the source of the switch Q2, and the capacitor C5 is connected in parallel between the source and drain of the switch Q1. The gate of the switch Q2 is connected to the second switch driver circuit 6, the drain of the switch Q2 is connected to the common end of the capacitor C1 and the capacitor C2, and the capacitor C6 is connected in parallel between the source and drain of the switch Q2.

[0017] Among them, capacitor C5 is added between the source and drain of the switch tube Q1, and capacitor C6 is added between the source and drain of the switch tube Q2. Capacitors C5 and C6 must be high-frequency, low-ESR MLCC capacitors to increase the Cds junction capacitance of the MOSFET. At the moment the MOSFET is turned off, capacitors C5 and C6 can prolong the state where the voltage across the MOSFET is almost zero, so that the current at the moment the MOSFET is turned off is bypassed to capacitors C5 and C6, charging capacitors C5 or C6, further reducing the switching loss of the MOSFET. Most of the energy stored in the capacitor is not lost as heat energy, but is discharged before the MOSFET is turned on in the next cycle to continue supplying energy to the load.

[0018] Exemplarily, the current sampling circuit 1 includes a resistor R7, a resistor R8, a resistor R10, a resistor R11, a resistor R15, a resistor R16, a resistor R17, an operational amplifier U9A, and an operational amplifier U9B. The models of the operational amplifier U9A and the operational amplifier U9B are LM6442AIN, INA282, or ACS712. One end of the resistor R7 is connected to the first end of the resistor R5, the other end of the resistor R7 is connected to the output end of the operational amplifier U9B through the resistor R9, the common end of the resistor R7 and the resistor R9 is connected to the negative input end of the operational amplifier U9B, one end of the resistor R8 is connected to the second end of the resistor R5, the other end of the resistor R8 is grounded through the resistor R10, the common end of the resistor R8 and the resistor R10 is connected to the positive input end of the operational amplifier U9B, and the positive input end of the operational amplifier U9B is also connected to the current comparison circuit 2 through the resistor R11; the output end of the operational amplifier U9B is connected to the pin 3 of the operational amplifier U9A. Pin 2 of the operational amplifier U9A is grounded through resistor R16, pin 2 of the operational amplifier U9A is connected to the first end of resistor R17, the second end of the resistor R17 is connected to the current comparison circuit 2, pin 4 of the operational amplifier U9A is grounded, pin 8 of the operational amplifier U9A is connected to the second end of the resistor R7, pin 1 of the operational amplifier U9A is connected to pin 2 of the operational amplifier U9A through resistor R15, and pin 1 of the operational amplifier U9A is also grounded, wherein pin 3 of the operational amplifier U9A is the positive input end, pin 2 of the operational amplifier U9A is the negative input end, and pin 1 of the operational amplifier U9A is the output end.

[0019] Exemplarily, the voltage sampling circuit 3 includes a resistor R24 ​​, a resistor R25 , a resistor R26 , a resistor R27 and an operational amplifier U6A. The model of the operational amplifier U6A is LM6142AIN.

[0020] One end of the inductor L1 away from the resistor R5 is grounded through the resistor R26 and the resistor R25. The common end of the resistor R26 and the resistor R25 is connected to pin 2 of the operational amplifier U6A. Pin 3 of the operational amplifier U6A is connected to the resistor R24. The resistor R24 ​​is a position changer. One end of the resistor R24 ​​is grounded. The other end of the resistor R24 ​​is connected to the first switch tube drive circuit and the logic circuit 4. Pin 1 of the operational amplifier U6A is connected to pin 2 of the operational amplifier U6A through resistor R27. Pin 4 of the operational amplifier U6A is grounded. Pin 8 of the operational amplifier U6A is connected to the first switch tube drive circuit and the logic circuit. Pin 3 of the operational amplifier U6A is the positive input end, pin 2 is the negative input end, and pin 1 is the output end.

[0021] Exemplarily, the current comparison circuit (2) includes a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R34, a diode D3, a diode D4, a power supply V4, a comparator U7A and a comparator U7B, the comparator U7A and the comparator U7B are of the LM339D type, and the diode D3 and the diode D4 are of the 1N4148 type.

[0022] Pin 1 of the operational amplifier U6A is connected to pin 6 of the comparator U7A through a diode D3, and is connected to pin 5 of the comparator U7B through a diode D4. Pin 6 of the comparator U7A is connected to the second switch tube drive circuit 6 through a resistor R18, and pin 6 is grounded through a resistor R19. Pin 7 of the comparator U7A is connected to pin 4 of the comparator U7B. Pin 4 of the comparator U7A is connected to pin 1 of the operational amplifier U9A in the current sampling circuit 1. Pin 3 of the comparator U7A is connected to a common node, and the common node is connected to the second switch tube drive circuit 6. The comparator Pin 1 of U7A is connected to the logic circuit 4, and pin 1 of the comparator U7A is also connected to the first common node through resistor R20. Pin 22 of the comparator U7A is grounded. Pin 2 of the comparator U7B is connected to the logic circuit 4, and pin 2 of the comparator U7B is also connected to the first common node through resistor R21. One end of the power supply V4 is grounded, and the other end is connected to the first common node. Pin 3 of the comparator U7B is grounded through resistor R22, and connected to the first common node through resistor R23. The common end of the resistor R22 and the resistor R23 is connected to the first common node through resistor R34 and switch S1.

[0023] Illustratively, the logic circuit 4 includes a NOR gate U3A, a NOR gate U3B, a Zener diode D5, a Zener diode D6, a Zener diode D7, a Zener diode D8, a Zener diode D9, a Zener diode D10, a capacitor C7, a capacitor C8, a resistor R13, a resistor R30, a resistor R33, a NAND gate U10C, and a NAND gate U10D. The NOR gate U3A and the NOR gate U3B are of model 74LS02D, the NAND gate U10C and the NAND gate U10D are of model 74LS00D, and the Zener diodes D5, D6, D7, D8, D9, and D10 are of model 1N6000B.

[0024] One input end of the NOR gate U3A is connected to pin 1 of the comparator U7A, the other input end of the NOR gate U3A is connected to the output end of the NOR gate U3B, the output end of the NOR gate U3A is connected to the other input end of the NOR gate U3B, the output end of the NOR gate U3A is also connected to the first input end of the NAND gate U10C, the output end of the NOR gate U3B is connected to the first input end of the NAND gate U10D, the second input end of the NAND gate U10C is connected to the cathode of the Zener diode D9, the anode of the Zener diode D9 is connected to the second common node, the second common node is connected to the cathode of the Zener diode D9 through the capacitor C8 and the resistor R33, the common end of the capacitor C8 and the resistor R33 is grounded, and the second common node is connected to the cathode of the Zener diode D9 through the capacitor C8 and the resistor R33. The first input terminal of the NAND gate U10C is connected to the first input terminal of the NAND gate U10C through the resistor R30 and the Zener diode D5, the second input terminal of the NAND gate U10C is connected to the zero-crossing detection circuit 7 through the Zener diode D8, the second input terminal of the NAND gate U10D is connected to the cathode of the Zener diode D10, the anode of the Zener diode D10 is connected to the third common node, the third common node is connected to the cathode of the Zener diode D10 through the capacitor C7, the resistor R3 and the Zener diode D6 in sequence, the third common node is connected to the third common node through the Zener diode D7 and the resistor R13 respectively, the common terminal of the capacitor C7 and the resistor R31 is grounded, and the common terminal of the capacitor C7 and the resistor R31 is also connected to the common terminal of the capacitor C8 and the resistor R33.

[0025] Exemplarily, the first switch tube drive circuit 5 includes a resistor R1, a resistor R2, a resistor R12, an optocoupler U1, and a capacitor C3, wherein the model of the optocoupler U1 is ACPL-P346-000E or TLP250. Pin 1 of the optocoupler U1 is connected to the second switch tube drive circuit 6 and the zero-crossing detection circuit 7, pin 3 of the optocoupler U1 is connected to the NAND gate U10C via resistor R12, pin 4 of the optocoupler U1 is connected to a fourth common node via resistor R2, pin 4 of the optocoupler U1 is further connected to pin 6 of the optocoupler U1 via power supply V2, pin 5 of the optocoupler U1 is connected to a fourth common node via resistor R1, capacitor C3 is connected in parallel across the resistor R1, and the fourth common node is connected to the gate of the switch tube Q1.

[0026] Exemplarily, the second switch tube driving circuit 6 includes a resistor R3, a resistor R4, a resistor R32, a capacitor C4 and an optocoupler U2, wherein the model of the optocoupler U2 is ACPL-P346-000E.

[0027] Pin 1 of the optocoupler U2 is connected to pin 1 of the optocoupler U1, pin 3 of the optocoupler U2 is connected to the output end of the NAND gate U10D through resistor R32, pin 4 of the optocoupler U2 is connected to the fifth common node through resistor R4, pin 4 of the optocoupler U2 is also connected to pin U6 of the optocoupler U2 through power supply V3, pin 5 of the optocoupler U2 is connected to the fifth common node through resistor R3, the capacitor C4 is connected in parallel to both ends of the resistor R3, and the fifth common node is connected to the gate of the switch tube Q2.

[0028] Exemplarily, the zero-crossing detection circuit 7 includes a resistor R6, a resistor R28, a resistor R29, a diode D1, a diode D2 and an optocoupler U5, wherein the diode D1 and the diode D2 are of type 1N4148, and the optocoupler U5 is of type HCPL-263L-000E.

[0029] Pin 1 of the optocoupler U5 is connected to the power supply V1, pin 2 of the optocoupler U5 is connected to the drain of the switch tube Q1 through the diode D2, pin 3 of the optocoupler U5 is connected between the capacitor C1 and the capacitor C2, pin 4 of the optocoupler U5 is connected to the drain of the switch tube Q2 through the diode D1, resistor R6 is connected between pins 2 and 4 of the optocoupler U5, pin 5 of the optocoupler U5 is connected between the capacitor C1 and the capacitor C2, pin 6 of the optocoupler U5 is connected to one end of the resistor R29, and the other end of the resistor R29 is respectively connected to pin 8 of the optocoupler U5 and pin 7 of the optocoupler U5 through resistor R28, pin 6 of the optocoupler U5 is also connected to the second input end of the NAND gate U10D through the voltage regulator diode D6, and pin 8 of the optocoupler U5 is also connected to the power supply V4.

[0030] The main control circuit comprises two comparators, U7A and U7B, two NOR gates, U3A and U3B, two NAND gates, U10A and U10B, and peripheral resistors, capacitors, and diodes. The real-time inductor current signal, measured by the current sampling circuit, is fed into the positive input of comparators U7A and the negative input of U7B, respectively, for comparison with the resistor divider circuits R18, R19, R22, and R23, which set the maximum and minimum current values. The comparison outputs are connected to an RS flip-flop consisting of two NOR gates. NOR gates are used because, under certain circumstances, both voltage comparators will output a high level. If at least one of the NOR gate inputs is high, the outputs of both gates must be low, turning off both MOSFETs Q1 and Q2. This prevents simultaneous conduction and short-circuit damage. High-speed optocoupler U5, along with U10C and U10D, form the ZVS (zero voltage switching) detection circuit, enabling the MOSFETs to conduct with virtually no switching losses when Vds is zero.

[0031] Exemplarily, the DCDC power converter further includes a load resistor R14 , which is connected to both ends of the capacitor C2 via a switch S2 .

[0032] The DCDC power converter also includes three oscilloscopes XSC1, XSC2, and XSC3 outside. Oscilloscope XSC1 is used to observe the waveform of the second switch tube drive circuit 6, oscilloscope XSC2 is used to observe the waveform of the current sampling circuit 1, and oscilloscope XSC3 is used to observe the waveform of the first switch tube drive circuit 5. The component parameters of the DCDC power converter can be adjusted according to the waveforms of the three oscilloscopes.

[0033] The working process of the DCDC power converter provided by the utility model is as follows:

[0034] First, the startup phase begins. When the circuit is not started, the inductor current is zero, and the current sampling amplifier circuit receives a 2.5V input. When startup switch S1 is closed (in actual circuits, startup is typically performed automatically by the reset circuit), the voltage at the positive input of comparator U7B exceeds the 2.5V at the negative input, resulting in a high output. RS flip-flop NOT gate U3A is set to output a high level. Since the voltage on the left side of the inductor remains constant during this phase, the output signal of high-speed optocoupler U5 also remains unchanged. Regardless of whether the output is 0 or 1, the output of NOR gate U3A remains high, charging capacitor C8 through resistor R30. After a period of time, the voltage on capacitor C8 reaches a high level, and NAND gate U10C, with both inputs high, outputs a low level. Optocoupler U1 turns on MOSFET Q1, and the switching power supply enters CCM operation. At this point, the upper and lower limits of the inductor current set by the two voltage comparators are both greater than zero, and the inductor current does not cross zero. The operating process is as follows: Q1 turns on, Q2 turns off, the inductor current increases, and power is supplied to the load. When the current reaches the upper limit, the RS trigger resets, Q2 turns on, and Q1 turns off. The inductor continues to supply power to the load through Q2, and the current decreases. When the current decreases to the lower limit, the RS trigger resets again, returning to the state where Q1 turns on and Q2 turns off, and the cycle repeats. At this point, the power supply has not yet entered the soft switching state, but it can automatically start oscillation.

[0035] After the power supply starts, the startup switch S1 opens, the upper current limit is greater than zero, and the lower current limit is less than zero. The power supply transitions to the DCM high-efficiency soft-switching mode for stable operation. High-speed optocoupler U5 automatically controls the soft-switching dead zone of Q1 and Q2. Assume that at a certain moment, Q1 turns on and Q2 turns off, causing the inductor current to increase in the positive direction, supplying power to the load. When the inductor reaches the upper limit set by the comparator, the RS trigger resets, and Q1, with the assistance of C5, turns off softly with zero current. However, due to the illumination of the LED below optocoupler U5, D1 is reversely blocked, pulling U5's pin 6 output low. Furthermore, due to its large capacitance, C7 has not yet fully charged at the moment RS flips. Therefore, U10D's lower input is low, and its output is high. Q2 is not conducting, indicating a dead zone. After a very short time, current continues to flow due to L1's self-inductance, charging C5 and discharging C6. When the voltage on C6 drops to 0V, D1 turns on, shorting the LED below U5. Pin 6 outputs a high level, U10D outputs a low level, and Q2 softly turns on with zero voltage. The inductor continues to supply power to the load, reducing the current to zero. The output filter capacitor C2, through the inductor and Q2, forms a loop with reverse current, gradually increasing the inductor current. At this point, the load is completely powered by the output filter capacitor C2, so the output capacitor must be large enough to ensure relatively stable output voltage. When the inductor current reaches another voltage comparator, the RS trigger is set, and Q2, with the help of C6, turns off with zero current. Similarly, Q1 is turned on with zero voltage by shorting out the other optocoupler LED above U5. This repetitive process allows the switching power supply to operate in a completely soft-switching state with high efficiency.

[0036] Voltage regulation principle: After the voltage sampling signal is amplified by U6A, it is used by D3 and D4 to change the peak and valley current settings of the voltage comparator. When the output voltage is too low, D3 conducts, increasing the inductor peak current; when the output voltage is too low, D4 conducts, reducing the inductor valley current. Negative feedback regulates the output voltage to ensure that it is consistent with the set voltage of the reference power supply, thus achieving voltage regulation.

[0037] The present invention provides a peak-valley current controlled soft-switching high-efficiency DC-DC power converter. In conventional hard-switching power supplies, approximately 40% of energy loss occurs at the switching moment. The switching tube of the soft-switching power supply operates in a completely soft-switching state, and the capacitor absorbs and stores the impact energy at the switching moment, significantly reducing the switching loss of the switching tube.

[0038] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0039] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0040] Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.

Claims

1. A peak-valley current controlled soft switching high efficiency DC-DC power converter, characterized in that: It comprises a current sampling circuit (1), a current comparison circuit (2), a voltage sampling circuit (3), a logic circuit (4), a first switch tube driving circuit (5), a second switch tube driving circuit (6), a zero-crossing detection circuit (7) and a power circuit; The current sampling circuit (1) collects the current magnitude and direction of the power circuit and inputs the data into the current comparison circuit (2); The voltage sampling circuit (3) is used to provide an upper limit reference current and a lower limit reference current for the current comparison circuit (2); The current comparison circuit (2) is used to compare the collected inductor current with the upper limit reference current and the lower limit reference current, and transmit the comparison result to the logic circuit (4); The logic circuit (4) performs logic processing on the comparison result and transmits the result to the first switch tube drive circuit (5) and the second switch tube drive circuit (6) respectively, so as to control the on and off of the first switch tube drive circuit (5) and the second switch tube (6); The zero-crossing detection circuit (7) performs zero-crossing detection on the first switch tube drive circuit (5) and the second switch tube drive circuit (6) respectively.

2. The peak-valley current controlled soft switching high efficiency DCDC power converter according to claim 1, characterized in that: The power circuit includes an inductor L1, a shunt resistor R5, a capacitor C1, a capacitor C2, a switch tube Q1, a capacitor C5, a switch tube Q2 and a capacitor C6; One end of the inductor L1 is connected to the current sampling circuit (1) through the shunt resistor R5, and the other end of the inductor L1 is connected to the source of the switch tube Q1 through the capacitor C2 and the capacitor C1. The gate of the switch tube Q1 is connected to the first switch tube drive circuit (5), the drain of the switch tube Q1 is connected to the source of the switch tube Q2, and the capacitor C5 is connected in parallel between the source and drain of the switch tube Q1; the gate of the switch tube Q2 is connected to the second switch tube drive circuit (6), the drain of the switch tube Q2 is connected to the common end of the capacitor C1 and the capacitor C2, and the capacitor C6 is connected in parallel between the source and drain of the switch tube Q2.

3. The peak-valley current controlled soft switching high efficiency DCDC power converter according to claim 2, characterized in that: The current sampling circuit (1) includes a resistor R7, a resistor R8, a resistor R10, a resistor R11, a resistor R15, a resistor R16, a resistor R17, an operational amplifier U9A and an operational amplifier U9B; One end of the resistor R7 is connected to the first end of the resistor R5, the other end of the resistor R7 is connected to the output end of the operational amplifier U9B through the resistor R9, the common end of the resistor R7 and the resistor R9 is connected to the negative input end of the operational amplifier U9B, one end of the resistor R8 is connected to the second end of the resistor R5, the other end of the resistor R8 is grounded through the resistor R10, the common end of the resistor R8 and the resistor R10 is connected to the positive input end of the operational amplifier U9B, and the positive input end of the operational amplifier U9B is also connected to the current comparison circuit (2) through the resistor R11; The output end of the operational amplifier U9B is connected to pin 3 of the operational amplifier U9A, pin 2 of the operational amplifier U9A is grounded through resistor R16, pin 2 of the operational amplifier U9A is connected to the first end of resistor R17, the second end of the resistor R17 is connected to the current comparison circuit (2), pin 4 of the operational amplifier U9A is grounded, pin 8 of the operational amplifier U9A is connected to the second end of the resistor R7, pin 1 of the operational amplifier U9A is connected to pin 2 of the operational amplifier U9A through resistor R15, and pin 1 of the operational amplifier U9A is also grounded, wherein pin 3 of the operational amplifier U9A is the positive input end, pin 2 of the operational amplifier U9A is the negative input end, and pin 1 of the operational amplifier U9A is the output end.

4. The peak-valley current controlled soft switching high efficiency DCDC power converter according to claim 3, characterized in that: The voltage sampling circuit (3) includes a resistor R24, a resistor R25, a resistor R26, a resistor R27 and an operational amplifier U6A; The end of the inductor L1 away from the resistor R5 is grounded through the resistor R26 and the resistor R25. The common end of the resistor R26 and the resistor R25 is connected to the pin 2 of the operational amplifier U6A. The pin 3 of the operational amplifier U6A is connected to the resistor R24. The resistor R24 ​​is a position changer. One end of the resistor R24 ​​is grounded. The other end of the resistor R24 ​​is connected to the first switch tube drive circuit and the logic circuit (4). The pin 1 of the operational amplifier U6A is connected to the pin 2 of the operational amplifier U6A through the resistor R27. The pin 4 of the operational amplifier U6A is grounded. The pin 8 of the operational amplifier U6A is connected to the first switch tube drive circuit and the logic circuit. The pin 3 of the operational amplifier U6A is the positive input end, the pin 2 is the negative input end, and the pin 1 is the output end.

5. The peak-valley current controlled soft switching high efficiency DCDC power converter according to claim 4, characterized in that: The current comparison circuit (2) includes a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R34, a diode D3, a diode D4, a power supply V4, a comparator U7A and a comparator U7B; Pin 1 of the operational amplifier U6A is connected to pin 6 of the comparator U7A through a diode D3, and is connected to pin 5 of the comparator U7B through a diode D4. Pin 6 of the comparator U7A is connected to the second switch tube drive circuit (6) through a resistor R18, and pin 6 is grounded through a resistor R19. Pin 7 of the comparator U7A is connected to pin 4 of the comparator U7B. Pin 4 of the comparator U7A is connected to pin 1 of the operational amplifier U9A in the current sampling circuit (1). Pin 3 of the comparator U7A is connected to a common node, and the common node is connected to the second switch tube drive circuit (6). Pin 1 of the comparator U7A is connected to the logic circuit (4), and pin 1 of the comparator U7A is also connected to the first common node through a resistor R20. Pin 22 of the comparator U7A is grounded. Pin 2 of the comparator U7B is connected to the logic circuit (4), and pin 2 of the comparator U7B is also connected to the first common node through a resistor R21. One end of the power supply V4 is grounded, and the other end is connected to the first common node. Pin 3 of the comparator U7B is grounded through a resistor R22, and is connected to the first common node through a resistor R23. The common end of the resistors R22 and R23 is connected to the first common node through a resistor R34 and a switch S1.

6. The peak-valley current controlled soft switching high efficiency DCDC power converter according to claim 5, characterized in that: The logic circuit (4) includes a NOR gate U3A, a NOR gate U3B, a voltage regulator diode D5, a voltage regulator diode D6, a voltage regulator diode D7, a voltage regulator diode D8, a voltage regulator diode D9, a voltage regulator diode D10, a capacitor C7, a capacitor C8, a resistor R13, a resistor R30, a resistor R33, a NAND gate U10C and a NAND gate U10D; One input end of the NOR gate U3A is connected to pin 1 of the comparator U7A, the other input end of the NOR gate U3A is connected to the output end of the NOR gate U3B, the output end of the NOR gate U3A is connected to the other input end of the NOR gate U3B, the output end of the NOR gate U3A is also connected to the first input end of the NAND gate U10C, the output end of the NOR gate U3B is connected to the first input end of the NAND gate U10D, the second input end of the NAND gate U10C is connected to the cathode of the Zener diode D9, the anode of the Zener diode D9 is connected to the second common node, the second common node is connected to the cathode of the Zener diode D9 through the capacitor C8 and the resistor R33, the common end of the capacitor C8 and the resistor R33 is grounded, and the second common node is respectively The first input terminal of the NAND gate U10C is connected via the resistor R30 and the voltage-stabilizing diode D5, the second input terminal of the NAND gate U10C is connected to the zero-crossing detection circuit (7) via the voltage-stabilizing diode D8, the second input terminal of the NAND gate U10D is connected to the cathode of the voltage-stabilizing diode D10, the anode of the voltage-stabilizing diode D10 is connected to the third common node, the third common node is connected to the cathode of the voltage-stabilizing diode D10 via the capacitor C7, the resistor R3 and the voltage-stabilizing diode D6 in sequence, the third common node is connected to the third common node via the voltage-stabilizing diode D7 and the resistor R13 respectively, the common terminal of the capacitor C7 and the resistor R31 is grounded, and the common terminal of the capacitor C7 and the resistor R31 is also connected to the common terminal of the capacitor C8 and the resistor R33.

7. The peak-valley current controlled soft switching high efficiency DCDC power converter according to claim 6, characterized in that: The first switch tube drive circuit (5) comprises a resistor R1, a resistor R2, a resistor R12, an optocoupler U1 and a capacitor C3, wherein pin 1 of the optocoupler U1 is connected to the second switch tube drive circuit (6) and the zero-crossing detection circuit (7), pin 3 of the optocoupler U1 is connected to the NAND gate U10C via the resistor R12, pin 4 of the optocoupler U1 is connected to a fourth common node via the resistor R2, pin 4 of the optocoupler U1 is further connected to pin 6 of the optocoupler U1 via the power supply V2, pin 5 of the optocoupler U1 is connected to the fourth common node via the resistor R1, the capacitor C3 is connected in parallel to both ends of the resistor R1, and the fourth common node is connected to the gate of the switch tube Q1.

8. The peak-valley current controlled soft switching high efficiency DCDC power converter according to claim 7, characterized in that: The second switch tube driving circuit (6) comprises a resistor R3, a resistor R4, a resistor R32, a capacitor C4 and an optocoupler U2; Pin 1 of the optocoupler U2 is connected to pin 1 of the optocoupler U1, pin 3 of the optocoupler U2 is connected to the output end of the NAND gate U10D through resistor R32, pin 4 of the optocoupler U2 is connected to the fifth common node through resistor R4, pin 4 of the optocoupler U2 is also connected to pin U6 of the optocoupler U2 through power supply V3, pin 5 of the optocoupler U2 is connected to the fifth common node through resistor R3, the capacitor C4 is connected in parallel to both ends of the resistor R3, and the fifth common node is connected to the gate of the switch tube Q2.

9. The peak-valley current controlled soft switching high efficiency DC-DC power converter according to claim 7, characterized in that: The zero-crossing detection circuit (7) includes a resistor R6, a resistor R28, a resistor R29, a diode D1, a diode D2 and an optical coupler U5; Pin 1 of the optocoupler U5 is connected to the power supply V1, pin 2 of the optocoupler U5 is connected to the drain of the switch tube Q1 through the diode D2, pin 3 of the optocoupler U5 is connected between the capacitor C1 and the capacitor C2, pin 4 of the optocoupler U5 is connected to the drain of the switch tube Q2 through the diode D1, resistor R6 is connected between pins 2 and 4 of the optocoupler U5, pin 5 of the optocoupler U5 is connected between the capacitor C1 and the capacitor C2, pin 6 of the optocoupler U5 is connected to one end of the resistor R29, and the other end of the resistor R29 is respectively connected to pin 8 of the optocoupler U5 and pin 7 of the optocoupler U5 through resistor R28, pin 6 of the optocoupler U5 is also connected to the second input end of the NAND gate U10D through the voltage regulator diode D6, and pin 8 of the optocoupler U5 is also connected to the power supply V4.

10. The peak-valley current controlled soft switching high efficiency DCDC power converter according to claim 2, characterized in that: The DCDC power converter further includes a load resistor R14 , which is connected to both ends of the capacitor C2 via a switch S2 .

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