High-precision dual-channel input detection and logic processing device

Abstract

The utility model relates to a high-precision dual-channel input detection and logic processing device, belongs to the technical field of input circuits, and solves the problems of large time delay and low precision when multi-signal input is detected in the prior art. Comprising two groups of input channels, a Schmitt trigger and a logic processing module, each group of input channels comprises an operational amplifier module, a buffer and a level shifter which are connected in sequence; wherein the two input ends of the Schmitt trigger are respectively connected with the output ends of the level translators in the two input channels; the logic processing module comprises a plurality of groups of NAND gates; wherein the input ends A of the two groups of NAND gates are respectively used for being connected with the outputs of the two Schmitt triggers, and after logical operation is carried out on signals input by the input ends B of the two groups of NAND gates, the output ends of the two groups of NAND gates output logical processing results. The double-channel input detection and logic processing device is fast in response and high in precision and has logic processing capacity.

Description

Technical Field

[0001] The utility model relates to the technical field of input circuits, in particular to a high-precision dual-channel input detection and logic processing device. Background Art

[0002] Input testing of devices connected to a bus network plays a crucial role in many areas. For example, it verifies the compatibility and stability of devices connected to the bus network, and ensures data integrity and security.

[0003] Existing input detection circuits for bus network access devices mostly use simple single-channel input designs, such as the TLP2355 optocoupler. These traditional input detection circuits suffer from slow response times and significant time delays when handling input detection from multiple signal sources. Furthermore, these circuits are susceptible to interference in high-noise environments, making them unable to provide stable input signals and resulting in low detection accuracy.

[0004] Since the single-channel input detection circuit only has one input signal, it does not have logic processing capabilities and cannot meet multi-functional requirements, thus reducing the overall performance of the system. Utility Model Content

[0005] In view of the above analysis, the present invention aims to provide a high-precision dual-channel input detection and logic processing device to solve the problems of large delay and low precision of existing input detection circuits.

[0006] The purpose of this utility model is mainly achieved through the following technical solutions:

[0007] It includes two groups of input channels, Schmitt triggers and logic processing modules; each group of input channels includes an operational amplifier module, a buffer, and a level converter connected in sequence; among them,

[0008] The operational amplifier module has an input end for receiving an external input signal and an output end connected to the input end of the buffer;

[0009] The level converter has an input end connected to the output end of the buffer;

[0010] The two input terminals of the Schmitt trigger are respectively connected to the output terminals of the level converters in the two input channels;

[0011] The logic processing module includes multiple groups of NAND gates; wherein, the A input ends of two groups of NAND gates are respectively used to connect to the outputs of two Schmitt triggers, and after performing logical operations with the signals input from the B input ends of the two groups of NAND gates, the output ends of the two groups of NAND gates output the logic processing results.

[0012] Based on the further improvement of the above scheme, the operational amplifier module includes a chip OPA836, a first resistor, a second resistor, and a third resistor. Pin 1 of the chip OPA836 is the output end; pin 3 is the positive input end, which is connected to the input signal through the first resistor; pin 4 is the negative input end, which is connected to the input signal through the second resistor, and is connected to the output end through the third resistor.

[0013] Based on a further improvement of the above solution, the buffer includes a chip SN74LVC1G34, with pin 2 as an input end and pin 4 as an output end.

[0014] Based on the further improvement of the above scheme, the level converter includes a chip SN74LVC1T45, pin 1 is the first voltage input terminal, which inputs the original voltage; pin 6 is the second voltage input terminal, which inputs the converted voltage; pin 5 is the direction control input terminal, which inputs the converted voltage; pin 3 is the data input terminal; and pin 4 is the data output terminal.

[0015] Based on a further improvement of the above solution, the Schmitt trigger includes a chip 74HC14T14, wherein pin 1 is a first input terminal connected to the output terminal of a level converter in an input channel; pin 2 is a first inverting output terminal connected to the A input terminal of the first NAND gate of the logic processing module; pin 3 is a second input terminal connected to the output terminal of the level converter in another input channel; and pin 4 is a second inverting output terminal connected to the A input terminal of the second NAND gate of the logic processing module.

[0016] Based on a further improvement of the above solution, the logic processing module includes a chip 74HC00, pin 1 is the A input terminal of the first NAND gate; pin 2 is the B input terminal of the first NAND gate, connected to the power supply or ground or the A input terminal of the second NAND gate; pin 3 is the output terminal of the first NAND gate; pin 4 is the A input terminal of the second NAND gate; pin 5 is the B input terminal of the second NAND gate, connected to the power supply or ground or the A input terminal of the first NAND gate; pin 6 is the output terminal of the second NAND gate.

[0017] Based on a further improvement of the above solution, the front end of the operational amplifier module in each group of input channels also includes a low-pass filter circuit.

[0018] Based on a further improvement of the above scheme, each group of low-pass filter circuits includes a fourth resistor and a capacitor; wherein, one end of the fourth resistor is connected to the external input signal, and the other end is respectively connected to the first resistor, the second resistor and one end of the capacitor, and the other end of the capacitor is grounded.

[0019] Based on a further improvement of the above solution, the power supply voltage of the buffer and the logic processing module is 3.3V; the power supply voltage of the Schmitt trigger is 5V.

[0020] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0021] 1. By setting up two sets of input channels, Schmitt triggers and logic processing modules, two external input signal sources can be detected simultaneously, increasing the response speed of the input detection circuit when processing complex signals. Especially in time-sensitive bus networks, it can significantly shorten the processing delay of the input signal, solving the problem of large time delay in traditional input detection circuits when processing data from multiple signal sources.

[0022] 2. Through the combination of low-pass filter circuit and Schmitt trigger, high-frequency noise and small-amplitude interference signals in the input signal are effectively suppressed, effectively improving the anti-noise ability and capture accuracy of input signal detection.

[0023] 3. Through dual-channel design and independent logic processing modules, it can process multiple signal inputs at the same time and perform logic processing on the input data, thereby adapting to more complex network environments and improving the overall performance of the system.

[0024] 4. Through the level converter, the seamless collaboration of modules running under different voltage standards is ensured, enhancing the compatibility and scalability of the system.

[0025] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following content, and some advantages will become apparent from the description or be understood through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the text and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. Throughout the accompanying drawings, the same reference symbols denote the same components.

[0027] Figure 1 This is a block diagram of a high-precision dual-channel input detection and logic processing device according to an embodiment of the present invention;

[0028] Figure 2 This is a circuit diagram of a high-precision dual-channel input detection and logic processing device according to another embodiment of the present invention;

[0029] Reference numerals:

[0030] 1- Operational amplifier module; 2- Buffer; 3- Level converter; 4- Schmitt trigger; 5- Logic processing module; 6- Low-pass filter circuit. DETAILED DESCRIPTION

[0031] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0032] A specific embodiment of the present utility model discloses a high-precision dual-channel input detection and logic processing device, such as Figure 1 Shown, including:

[0033] Two groups of input channels, Schmitt triggers and logic processing modules; each group of input channels includes an operational amplifier module 1, a buffer 2, and a level converter 3 connected in sequence; wherein,

[0034] The operational amplifier module has an input end for receiving an external input signal and an output end connected to the input end of the buffer;

[0035] The level converter has an input end connected to the output end of the buffer;

[0036] The two input terminals of the Schmitt trigger 4 are respectively connected to the output terminals of the level converters in the two input channels;

[0037] The logic processing module 5 includes multiple groups of NAND gates; wherein, the A input terminals of two groups of NAND gates are respectively used to connect to the outputs of two Schmitt triggers, and after performing logical operations with the signals input from the B input terminals of the two groups of NAND gates, the output terminals of the two groups of NAND gates output the logical processing results.

[0038] Another specific embodiment of the present invention is as follows Figure 2 As shown:

[0039] The operational amplifier module 1 includes a chip OPA836, a first resistor, a second resistor, and a third resistor. Pin 1 of the chip OPA836 is the output end; pin 3 is the positive input end, connected to the input signal through the first resistor; pin 4 is the negative input end, connected to the input signal through the second resistor, and connected to the output end through the third resistor.

[0040] For example, in the operational amplifier module 1 in one channel, R6 is the first resistor, R5 is the second resistor, and R7 is the third resistor; in the operational amplifier module 1 in another channel, R2 is the first resistor, R3 is the second resistor, and R1 is the third resistor.

[0041] It should be noted that the chip OPA836 is a high-speed operational amplifier used to amplify the filtered input signal. The chip provides a bandwidth of up to 205MHz and a conversion rate of 0.95V / μs, allowing the input signal to be quickly amplified and passed to the next level circuit, effectively improving the response speed of signal processing and ensuring that high-frequency signals can also be quickly captured.

[0042] Buffer 2 includes the SN74LVC1G34 chip, with pin 2 as the input and pin 4 as the output. It's worth noting that the buffer not only improves signal transmission stability but also acts as a signal isolation device, ensuring smooth signal transmission to the level shifter circuit without being affected by external interference, thus improving the circuit's noise immunity.

[0043] Level converter 3 includes the SN74LVC1T45 chip. Pin 1 is the first voltage input, which receives the original voltage; pin 6 is the second voltage input, which receives the converted voltage; pin 5 is the direction control input, which receives the converted voltage; pin 3 is the data input; and pin 4 is the data output. It's worth noting that the level converter resolves the level incompatibility issue between the input signal and the next-level logic circuit, ensuring seamless signal connection between systems with different voltage standards and guaranteeing system compatibility and scalability.

[0044] The Schmitt trigger 4 includes a 74HC14T14 chip. Pin 1 is the first input, connected to the output of a level shifter in one input channel; pin 2 is the first inverting output, connected to the A input of the first NAND gate of the logic processing module; pin 3 is the second input, connected to the output of the level shifter in another input channel; and pin 4 is the second inverting output, connected to the A input of the second NAND gate of the logic processing module. It should be noted that the Schmitt trigger detects the edge of the input signal and further removes small noise signals, ensuring reliable capture of rising and falling signal changes. It is particularly suitable for high-precision timestamp capture in time-sensitive networks.

[0045] Logic processing module 5 includes a 74HC00 chip. Pin 1 is the A input of the first NAND gate; pin 2 is the B input of the first NAND gate, connected to power, ground, or the A input of the second NAND gate; pin 3 is the output of the first NAND gate; pin 4 is the A input of the second NAND gate; pin 5 is the B input of the second NAND gate, connected to power, ground, or the A input of the first NAND gate; and pin 6 is the output of the second NAND gate. It is worth noting that the 74HC00 chip includes multiple groups of NAND gates, enabling complex logical judgments on multiple signals and outputting the logical processing results. This greatly enhances the flexibility and functionality of the input signal, allowing this solution to perform a variety of logical judgments based on actual needs.

[0046] The front end of the operational amplifier module in each input channel also includes a low-pass filter circuit 6. The RC low-pass filter circuit can effectively filter high-frequency noise to ensure the purity of the input signal. The two external input signals are transmitted through independent input channels, making this solution capable of processing multiple signal sources simultaneously. Each low-pass filter circuit includes a fourth resistor and a capacitor; wherein,

[0047] One end of the fourth resistor is connected to the external input signal, and the other end is respectively connected to the first resistor, the second resistor and one end of the capacitor, and the other end of the capacitor is grounded.

[0048] Exemplarily, in the low-pass filter circuit at the front end of one channel, R8 is the fourth resistor and C2 is the capacitor; in the low-pass filter circuit at the front end of the other channel, R4 is the fourth resistor and C1 is the capacitor.

[0049] Specifically, the power supply voltage of the buffer and the logic processing module is 3.3V; the power supply voltage of the Schmitt trigger is 5V.

[0050] During implementation, two sets of input channels receive two external input signal sources. Each channel's signal first passes through an RC low-pass filter circuit composed of resistors and capacitors to suppress high-frequency noise and ensure input signal purity. The cutoff frequency of the RC filter circuit can be adjusted to optimize noise suppression for different frequency bands.

[0051] The two filtered signals then enter the positive inputs of two OPA836 operational amplifiers. The OPA836 is a high-speed operational amplifier with a 205MHz bandwidth and a slew rate of up to 0.95V / μs. It precisely amplifies the signal and prevents signal attenuation during processing, ensuring the integrity and stability of the input signal. This makes it particularly suitable for high-speed signal processing.

[0052] The two amplified signals are then fed into two SN74LVC1G34 buffers, which stabilize and isolate the signals. The buffers' primary function is to prevent signal distortion during transmission due to load variations or external interference, further ensuring signal accuracy during subsequent level conversion.

[0053] Next, the output signals of the two SN74LVC1G34 buffers are fed into the data inputs of two SN74LVC1G34 level converters. The level converters convert the 3.3V signals into 5V logic signals, ensuring compatibility with subsequent logic processing modules. The level converters not only improve the circuit's compatibility but also enhance the system's scalability, enabling its application in network environments with multiple voltage standards.

[0054] Next, the output signals of the two SN74LVC1G34 level shifters are fed into the two inputs of a 74HC14T14 Schmitt trigger. This trigger detects both rising and falling edges of the input signal, ensuring accurate capture of signal changes. Furthermore, the Schmitt trigger removes small interference signals from the signal, ensuring signal stability.

[0055] Next, the signals output from the two output terminals of the Schmitt trigger 74HC14T14 are respectively input into the two input terminals of the logic processing module 74HC00. For example, pin 1 is the A input terminal of the first NAND gate, which receives the signal output from the first inverting output terminal of the 74HC14T14. Pin 2 is the B input terminal of the first NAND gate, which is connected to the A input terminal of the second NAND gate and receives the signal output from the second inverting output terminal of the 74HC14T14. Pin 3 is the output terminal of the first NAND gate, which outputs the result of the logic processing of the first NAND gate. Pin 4 is the A input terminal of the second NAND gate. Pin 5 is the B input terminal of the second NAND gate, which is connected to the power supply. Pin 6 is the output terminal of the second NAND gate, which outputs the logic processing signal of the second NAND gate.

[0056] It should be noted that the logic input module 74HC00 includes multiple groups of NAND gates. The inputs of each group of NAND gates include the output signals of the two output terminals of the 74HC14T14, power supply, and ground. In implementation, these inputs can be combined in different usage scenarios to achieve different logic processing to control external circuits accordingly. For example, the input terminals of the first group of NAND gates can output a logic control signal by performing a NAND relationship between the inverted signal of the processed first channel output signal and a high-level power supply signal or a low-level ground signal. Alternatively, the input terminals of the first group of NAND gates can output a logic control signal by performing a NAND relationship between the inverted signal of the processed first channel output signal and the inverted signal of the second channel output signal.

[0057] Compared with the prior art, the high-precision dual-channel input detection and logic processing device provided in this embodiment integrates an operational amplifier module, a buffer, a level converter, a Schmitt trigger, and a logic processing module by providing two sets of input channels. This can simultaneously detect two external input signal sources, increasing the response speed of the input detection circuit when processing complex signals. In particular, in time-sensitive bus networks, it can significantly shorten the processing delay of the input signal, solving the problem of large delay time when traditional input detection circuits process synchronous data from multiple signal sources. The combination of a low-pass filter circuit and a Schmitt trigger effectively suppresses high-frequency noise and small-amplitude interference signals in the input signal, effectively improving the noise immunity and capture accuracy of input signal detection. The dual-channel design and independent logic processing module can simultaneously process multiple signal inputs and perform logic processing on the input data, thereby adapting to more complex network environments and improving the overall performance of the system. The level converter ensures seamless cooperation between modules operating at different voltage standards, enhancing the compatibility and scalability of the system.

[0058] Those skilled in the art will appreciate that this invention does not involve any software improvements. This invention merely requires connecting devices with corresponding functions using the connection relationships provided in the embodiments of this invention, and does not involve any software improvements. The connection methods between the hardware devices with corresponding functions can be implemented by those skilled in the art using existing technologies and will not be described in detail here.

[0059] The above is only a preferred specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the protection scope of the present invention.

Claims

1. A high-precision dual-channel input detection and logic processing device, characterized in that: It includes two groups of input channels, Schmitt triggers and logic processing modules; each group of input channels includes an operational amplifier module, a buffer, and a level converter connected in sequence; among them, The operational amplifier module has an input end for receiving an external input signal and an output end connected to the input end of the buffer; The level converter has an input end connected to the output end of the buffer; The two input terminals of the Schmitt trigger are respectively connected to the output terminals of the level converters in the two input channels; The logic processing module includes multiple groups of NAND gates; wherein, the A input ends of two groups of NAND gates are respectively used to connect to the outputs of two Schmitt triggers, and after performing logical operations with the signals input from the B input ends of the two groups of NAND gates, the output ends of the two groups of NAND gates output the logic processing results.

2. The high-precision dual-channel input detection and logic processing device according to claim 1, characterized in that: The operational amplifier module includes a chip OPA836, a first resistor, a second resistor, and a third resistor. Pin 1 of the chip OPA836 is the output end; pin 3 is the positive input end, connected to the input signal through the first resistor; pin 4 is the negative input end, connected to the input signal through the second resistor, and connected to the output end through the third resistor.

3. The high-precision dual-channel input detection and logic processing device according to claim 1, characterized in that: The buffer includes a chip SN74LVC1G34, wherein pin 2 is an input end and pin 4 is an output end.

4. The high-precision dual-channel input detection and logic processing device according to claim 1, characterized in that: The level converter includes a chip SN74LVC1T45, wherein pin 1 is a first voltage input terminal, which inputs the original voltage; pin 6 is a second voltage input terminal, which inputs the converted voltage; pin 5 is a direction control input terminal, which inputs the converted voltage; pin 3 is a data input terminal; and pin 4 is a data output terminal.

5. The high-precision dual-channel input detection and logic processing device according to claim 1, characterized in that: The Schmitt trigger includes a chip 74HC14T14, wherein pin 1 is a first input terminal connected to the output terminal of a level converter in an input channel; pin 2 is a first inverting output terminal connected to the A input terminal of the first NAND gate of the logic processing module; pin 3 is a second input terminal connected to the output terminal of the level converter in another input channel; and pin 4 is a second inverting output terminal connected to the A input terminal of the second NAND gate of the logic processing module.

6. The high-precision dual-channel input detection and logic processing device according to claim 5, characterized in that: The logic processing module includes a chip 74HC00, wherein pin 1 is the A input terminal of the first NAND gate; pin 2 is the B input terminal of the first NAND gate, connected to the power supply, ground, or the A input terminal of the second NAND gate; pin 3 is the output terminal of the first NAND gate; pin 4 is the A input terminal of the second NAND gate; pin 5 is the B input terminal of the second NAND gate, connected to the power supply, ground, or the A input terminal of the first NAND gate; and pin 6 is the output terminal of the second NAND gate.

7. The high-precision dual-channel input detection and logic processing device according to claim 2, characterized in that: The front end of the operational amplifier module in each group of input channels also includes a low-pass filtering circuit.

8. The high-precision dual-channel input detection and logic processing device according to claim 7, characterized in that: Each low-pass filter circuit includes a fourth resistor and a capacitor; wherein, One end of the fourth resistor is connected to the external input signal, and the other end is respectively connected to the first resistor, the second resistor and one end of the capacitor, and the other end of the capacitor is grounded.

9. The high-precision dual-channel input detection and logic processing device according to any one of claims 1 to 7, characterized in that: The power supply voltage of the buffer and logic processing module is 3.3V; the power supply voltage of the Schmitt trigger is 5V.

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