Liquid crystal screen driving circuit capable of resisting external interference

Abstract

The utility model relates to the technical field of liquid crystal screens, and discloses a liquid crystal screen driving circuit capable of resisting external interference, which can effectively reduce the influence of external electromagnetic interference on signals, improve the anti-interference capability of the signals and ensure the stable transmission of the signals through the design of an anti-interference signal processing circuit and a differential signal transmission circuit. The influence of external noise on the signals is remarkably reduced, and noise signals are often eliminated when acting on the two signals, so that the quality and the reliability of the signals are improved; through the design of the data decoding circuit, received signals are decoded to restore original data, through the high-precision decoding algorithm and circuit design, the accuracy of the data can be ensured, the bit error rate can be reduced, and the details and precision of the signals can be reserved through the differential signal transmission circuit. And the quality of the signal in the data transmission process can be better maintained.

Description

Technical Field

[0001] The utility model relates to the technical field of liquid crystal screens, in particular to the driving field of liquid crystal screens, and specifically to a liquid crystal screen driving circuit capable of resisting external interference. Background Art

[0002] The liquid crystal screen uses liquid crystal material as its basic component. The liquid crystal material is filled between two parallel plates. Voltage is used to change the arrangement of the molecules inside the liquid crystal material to achieve the purpose of shading and transmitting light to display images of varying depths and staggered patterns. Moreover, as long as a three-primary color filter layer is added between the two flat plates, color images can be displayed.

[0003] A search revealed patent application number CN201320684639.7, which discloses a handheld terminal LCD screen driver circuit. This circuit uses a charge pump circuit to alternately turn the LCD screen on and off, providing a highly efficient and stable regulated voltage for the LCD screen. This voltage is then applied to the display electrodes, allowing the voltage difference between the display electrodes and the common electrode to act on the liquid crystal to achieve display, effectively ensuring circuit stability. This utility model's backlight driver circuit is connected to an enable control terminal, LCD_PWREN, which operates when the voltage is high and shuts down when the voltage is low, effectively saving power. Compared to existing technologies, this utility model boasts a simple circuit structure, low power consumption, and stable and reliable operation.

[0004] The current LCD driver circuit does not handle external electromagnetic interference signals well, resulting in unstable circuit signal transmission and reduced signal quality and reliability. The data processing precision is not high, which reduces data accuracy and increases the bit error rate. Therefore, we need to propose an LCD driver circuit that can resist external interference. Utility Model Content

[0005] The purpose of the present utility model is to provide a liquid crystal display driving circuit that is resistant to external interference. Through the design of an anti-interference signal processing circuit and a differential signal transmission circuit, the influence of external electromagnetic interference on the signal can be effectively reduced, the anti-interference ability of the signal can be improved, the stable transmission of the signal can be ensured, and the influence of external noise on the signal can be significantly reduced. The noise signal is often eliminated when it acts on two signals, thereby improving the quality and reliability of the signal; through the design of a data decoding circuit, the received signal is decoded and processed to restore the original data. Through a high-precision decoding algorithm and circuit design, the accuracy of the data can be ensured and the bit error rate can be reduced. The differential signal transmission circuit can retain the details and accuracy of the signal, so that the quality of the signal is better maintained during the data transmission process, so as to solve the problems raised in the above background technology.

[0006] To achieve the above-mentioned purpose, the present invention provides the following technical solution: a liquid crystal display driving circuit capable of resisting external interference, comprising:

[0007] A signal receiving circuit responsible for receiving a controller driving signal;

[0008] Anti-interference signal processing circuit for performing interference processing on received signals;

[0009] A differential signal transmission circuit that uses differential signal transmission to suppress common-mode interference;

[0010] A drive and control circuit that amplifies the processed signal and converts it into the drive signal required by the LCD screen;

[0011] A power supply circuit that provides stable operating voltage and current for the entire drive circuit;

[0012] A timing control circuit for ensuring that each circuit works in coordination according to a predetermined timing sequence;

[0013] A data decoding circuit that converts binary codes into high and low level signals;

[0014] The signal receiving circuit, anti-interference signal processing circuit, differential signal transmission circuit, timing control circuit, and data decoding circuit are all electrically connected to the driving and control circuit and the power supply circuit, and the signal receiving circuit is electrically connected to the anti-interference signal processing circuit and the differential signal transmission circuit respectively.

[0015] Preferably, the signal receiving circuit includes a chip U2, a terminal block M2, a transistor Q1, a transistor Q2, and a transistor Q5. The chip U2 is connected to the terminal block M2. A resistor R14 is connected between the base of the transistor Q1 and pin 13 of the chip U2. A resistor R12 is connected between the base of the transistor Q2 and pin 11 of the chip U2. A resistor R19 is connected between the base of the transistor Q5 and pin 12 of the chip U2. Resistors R1 and R18 are connected between the collector of the transistor Q2 and the collector of the transistor Q5.

[0016] Preferably, the anti-interference signal processing circuit includes a chip U4 and an optocoupler U1, pin 1 of the optocoupler U1 is connected to a resistor R1 connected to a 5V voltage, a resistor R4 is connected between pins 5 and 6 of the optocoupler U1, pin 5 of the optocoupler U1 is connected to pin 2 of the chip U4, pin 1 of the chip U4 is connected to a capacitor C1, and a capacitor C2 is connected between pins 5 and 6 of the chip U4.

[0017] Preferably, the differential signal transmission circuit includes an amplifier IC2A, an amplifier IC2B, and an amplifier IC4; a resistor R80 is connected between pins 1 and 2 of the amplifier IC2A; a resistor R120 is connected between pins 6 and 7 of the amplifier IC2B; and resistors R30 and R60 are connected between pins 2 and 6 of the amplifier IC4;

[0018] A resistor R90 is connected between pin 2 of the amplifier IC2A and pin 6 of the amplifier IC2B, a resistor R20 is connected between pin 1 of the amplifier IC2A and pin 2 of the amplifier IC4, and a resistor R150 is connected between pin 7 of the amplifier IC2B and pin 3 of the amplifier IC4.

[0019] Preferably, the drive and control circuit includes a chip U8, a capacitor C15 is connected between pins 2 and 3 of the chip U8, a capacitor C16 is connected between pins 4 and 5 of the chip U8, a resistor R88 and a diode VD2 arranged in parallel and a grounded capacitor C17 are connected to pin 14 of the chip U8, a resistor R91 connected to a 3.3V voltage and a grounded resistor R111 are respectively connected to pin 15 of the chip U8, a resistor R101 connected to a 3.3V voltage is connected to pin 18 of the chip U8, and a resistor R121 connected to a 3.3V voltage is connected to pin 20 of the chip U8.

[0020] Preferably, the timing control circuit includes a data output terminal and four triggers connected to the data output terminal, and the four triggers are connected to a direct clear terminal, a clock control terminal, and a data input terminal.

[0021] Preferably, the data decoding circuit includes a chip U10, a chip U20, a connector S1, a connector S2, a terminal JP4, and a terminal JP5. The chip U10 is connected to the connector S1, and the chip U20 is connected to the connector S2. The chip U10 and the chip U20 are both connected to the terminal JP4. The 16th pin of the chip U10 and the 16th pin of the chip U20 are both connected to the 1st pin of the terminal JP5 and connected to the power supply voltage.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] 1. The utility model can effectively reduce the impact of external electromagnetic interference on the signal through the design of anti-interference signal processing circuit and differential signal transmission circuit, improve the anti-interference ability of the signal, ensure the stable transmission of the signal, and significantly reduce the impact of external noise on the signal. The noise signal is often eliminated when acting on the two signals, thereby improving the quality and reliability of the signal;

[0024] 2. The utility model decodes the received signal and restores the original data through the design of the data decoding circuit. The high-precision decoding algorithm and circuit design can ensure the accuracy of the data and reduce the bit error rate. The differential signal transmission circuit can retain the details and accuracy of the signal, so that the signal quality is better maintained during the data transmission process. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a circuit diagram of the signal receiving circuit of the utility model;

[0026] Figure 2 This is a circuit diagram of the anti-interference signal processing circuit of the utility model;

[0027] Figure 3 This is a circuit diagram of the differential signal transmission circuit of the present utility model;

[0028] Figure 4 This is a circuit diagram of the drive and control circuit of the utility model;

[0029] Figure 5 This is a circuit diagram of the timing control circuit of the utility model;

[0030] Figure 6 This is a circuit diagram of the data decoding circuit of the present utility model. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0032] See also Figure 1-6 The present invention provides a technical solution: a liquid crystal display driving circuit capable of resisting external interference, comprising:

[0033] A signal receiving circuit responsible for receiving a controller driving signal;

[0034] The signal receiving circuit includes a chip U2, a terminal block M2, a transistor Q1, a transistor Q2, and a transistor Q5. The chip U2 is connected to the terminal block M2. A resistor R14 is connected between the base of the transistor Q1 and pin 13 of the chip U2. A resistor R12 is connected between the base of the transistor Q2 and pin 11 of the chip U2. A resistor R19 is connected between the base of the transistor Q5 and pin 12 of the chip U2. Resistors R1 and R18 are connected between the collector of the transistor Q2 and the collector of the transistor Q5.

[0035] A resistor R16 is connected between pins 15 and 16 of chip U2, and a resistor R15 connected to the supply voltage is connected to the collector of transistor Q1. The emitters of transistors Q1, Q2, and Q5 are all grounded.

[0036] Anti-interference signal processing circuit for performing interference processing on received signals;

[0037] The anti-interference signal processing circuit includes a chip U4 and an optocoupler U1. Pin 1 of the optocoupler U1 is connected to a resistor R1 connected to a 5V voltage. A resistor R4 is connected between pins 5 and 6 of the optocoupler U1. Pin 5 of the optocoupler U1 is connected to pin 2 of the chip U4. Pin 1 of the chip U4 is connected to a capacitor C1. A capacitor C2 is connected between pins 5 and 6 of the chip U4.

[0038] The anti-interference signal processing circuit also includes an optocoupler U22, wherein pin 1 of the optocoupler U22 is connected to a resistor R22 connected to a 5V voltage, a resistor R5 is connected between pins 5 and 6 of the optocoupler U22, and pin 5 of the optocoupler U22 is connected to pin 3 of the chip U4.

[0039] The anti-interference signal processing circuit also includes an optocoupler U3, wherein pin 1 of the optocoupler U3 is connected to a resistor R3 connected to a 5V voltage, a resistor R6 is connected between pins 5 and 6 of the optocoupler U3, and pin 5 of the optocoupler U3 is connected to pin 4 of the chip U4.

[0040] A differential signal transmission circuit that uses differential signal transmission to suppress common-mode interference;

[0041] The differential signal transmission circuit includes an amplifier IC2A, an amplifier IC2B, and an amplifier IC4. A resistor R80 is connected between pins 1 and 2 of the amplifier IC2A, a resistor R120 is connected between pins 6 and 7 of the amplifier IC2B, and resistors R30 and R60 are connected between pins 2 and 6 of the amplifier IC4.

[0042] A resistor R90 is connected between pin 2 of the amplifier IC2A and pin 6 of the amplifier IC2B, a resistor R20 is connected between pin 1 of the amplifier IC2A and pin 2 of the amplifier IC4, and a resistor R150 is connected between pin 7 of the amplifier IC2B and pin 3 of the amplifier IC4.

[0043] Pin 3 of amplifier IC2A is connected to a grounded resistor R40, pin 5 of amplifier IC2B is connected to a grounded resistor R190, and pin 3 of amplifier IC4 is connected to resistors R160 and R170 connected in series and grounded.

[0044] A drive and control circuit that amplifies the processed signal and converts it into the drive signal required by the LCD screen;

[0045] The drive and control circuit includes a chip U8, a capacitor C15 is connected between pins 2 and 3 of the chip U8, a capacitor C16 is connected between pins 4 and 5 of the chip U8, a resistor R88 and a diode VD2 arranged in parallel, and a grounded capacitor C17 are connected to pin 14 of the chip U8, a resistor R91 connected to a 3.3V voltage and a grounded resistor R111 are respectively connected to pin 15 of the chip U8, a resistor R101 connected to a 3.3V voltage is connected to pin 18 of the chip U8, and a resistor R121 connected to a 3.3V voltage is connected to pin 20 of the chip U8.

[0046] A power supply circuit that provides stable operating voltage and current for the entire drive circuit;

[0047] The power supply circuit includes but is not limited to: rectifier circuit, voltage stabilization circuit, protection circuit (overcurrent, overvoltage circuit, etc.).

[0048] A timing control circuit for ensuring that each circuit works in coordination according to a predetermined timing sequence;

[0049] The timing control circuit includes a data output terminal and four triggers connected to the data output terminal. The four triggers are connected to a direct clear terminal, a clock control terminal, and a data input terminal.

[0050] A data decoding circuit that converts binary codes into high and low level signals;

[0051] The data decoding circuit includes a chip U10, a chip U20, a connector S1, a connector S2, a terminal JP4, and a terminal JP5. The chip U10 is connected to the connector S1, and the chip U20 is connected to the connector S2. The chip U10 and the chip U20 are both connected to the terminal JP4. The 16th pin of the chip U10 and the 16th pin of the chip U20 are both connected to the 1st pin of the terminal JP5 and connected to the power supply voltage.

[0052] The signal receiving circuit, anti-interference signal processing circuit, differential signal transmission circuit, timing control circuit, and data decoding circuit are all electrically connected to the driving and control circuit and the power supply circuit, and the signal receiving circuit is electrically connected to the anti-interference signal processing circuit and the differential signal transmission circuit respectively.

[0053] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A liquid crystal display driving circuit resistant to external interference, characterized in that: include: A signal receiving circuit responsible for receiving a controller driving signal; Anti-interference signal processing circuit for performing interference processing on received signals; A differential signal transmission circuit that uses differential signal transmission to suppress common-mode interference; A drive and control circuit that amplifies the processed signal and converts it into the drive signal required by the LCD screen; A power supply circuit that provides stable operating voltage and current for the entire drive circuit; A timing control circuit for ensuring that each circuit works in coordination according to a predetermined timing sequence; A data decoding circuit that converts binary codes into high and low level signals; The signal receiving circuit, anti-interference signal processing circuit, differential signal transmission circuit, timing control circuit, and data decoding circuit are all electrically connected to the driving and control circuit and the power supply circuit, and the signal receiving circuit is electrically connected to the anti-interference signal processing circuit and the differential signal transmission circuit respectively.

2. The liquid crystal display driving circuit capable of resisting external interference according to claim 1, characterized in that: The signal receiving circuit includes a chip U2, a terminal block M2, a transistor Q1, a transistor Q2, and a transistor Q5. The chip U2 is connected to the terminal block M2. A resistor R14 is connected between the base of the transistor Q1 and pin 13 of the chip U2. A resistor R12 is connected between the base of the transistor Q2 and pin 11 of the chip U2. A resistor R19 is connected between the base of the transistor Q5 and pin 12 of the chip U2. Resistors R1 and R18 are connected between the collector of the transistor Q2 and the collector of the transistor Q5.

3. The liquid crystal display driving circuit capable of resisting external interference according to claim 1, characterized in that: The anti-interference signal processing circuit includes a chip U4 and an optocoupler U1. Pin 1 of the optocoupler U1 is connected to a resistor R1 connected to a 5V voltage. A resistor R4 is connected between pins 5 and 6 of the optocoupler U1. Pin 5 of the optocoupler U1 is connected to pin 2 of the chip U4. Pin 1 of the chip U4 is connected to a capacitor C1. A capacitor C2 is connected between pins 5 and 6 of the chip U4.

4. The liquid crystal display driving circuit capable of resisting external interference according to claim 1, characterized in that: The differential signal transmission circuit includes an amplifier IC2A, an amplifier IC2B, and an amplifier IC4. A resistor R80 is connected between pins 1 and 2 of the amplifier IC2A, a resistor R120 is connected between pins 6 and 7 of the amplifier IC2B, and resistors R30 and R60 are connected between pins 2 and 6 of the amplifier IC4. A resistor R90 is connected between pin 2 of the amplifier IC2A and pin 6 of the amplifier IC2B, a resistor R20 is connected between pin 1 of the amplifier IC2A and pin 2 of the amplifier IC4, and a resistor R150 is connected between pin 7 of the amplifier IC2B and pin 3 of the amplifier IC4.

5. The liquid crystal display driving circuit capable of resisting external interference according to claim 1, characterized in that: The drive and control circuit includes a chip U8, a capacitor C15 is connected between pins 2 and 3 of the chip U8, a capacitor C16 is connected between pins 4 and 5 of the chip U8, a resistor R88 and a diode VD2 arranged in parallel, and a grounded capacitor C17 are connected to pin 14 of the chip U8, a resistor R91 connected to a 3.3V voltage and a grounded resistor R111 are respectively connected to pin 15 of the chip U8, a resistor R101 connected to a 3.3V voltage is connected to pin 18 of the chip U8, and a resistor R121 connected to a 3.3V voltage is connected to pin 20 of the chip U8.

6. The liquid crystal display driving circuit capable of resisting external interference according to claim 1, characterized in that: The timing control circuit includes a data output terminal and four triggers connected to the data output terminal. The four triggers are connected to a direct clear terminal, a clock control terminal, and a data input terminal.

7. The liquid crystal display driving circuit capable of resisting external interference according to claim 1, characterized in that: The data decoding circuit includes a chip U10, a chip U20, a connector S1, a connector S2, a terminal JP4, and a terminal JP5. The chip U10 is connected to the connector S1, and the chip U20 is connected to the connector S2. The chip U10 and the chip U20 are both connected to the terminal JP4. The 16th pin of the chip U10 and the 16th pin of the chip U20 are both connected to the 1st pin of the terminal JP5 and connected to the power supply voltage.

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