Capacitive coupling structure, chip and electronic equipment

Abstract

The utility model discloses a capacitance coupling structure, a chip and electronic equipment. The capacitive coupling structure comprises at least one capacitor bank, the capacitor bank is used for providing multi-capacitor matching, each capacitor bank comprises at least one metal layer, and each metal layer comprises a common polar plate and a common polar plate, the common polar plate comprises a common substrate extending along a first direction, and an isolation polar plate and a finger-shaped polar plate which extend along a second direction and are connected with the common substrate; each independent polar plate and the common polar plate form a capacitor, at least two common substrates are connected through the isolation polar plate to define a plurality of mutually separated areas, and each independent polar plate is surrounded by the common substrate and the isolation polar plate in the corresponding area. And the isolation polar plates and the finger-shaped polar plates in the region form an interdigitated structure. Independent polar plates in the same capacitor bank and independent polar plates in different capacitor banks are isolated through the common polar plates, and stray capacitance between different independent polar plates is effectively reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, and in particular to a capacitive coupling structure, a chip and an electronic device. Background Art

[0002] In integrated circuit design, there is often a need for capacitor matching, especially in some high-performance analog circuits, such as ADC (Analog-to-Digital Converter) and DAC (Digital-to-Analog Converter), which have a large number of matching capacitor designs.

[0003] Figure 1 A simplified circuit of a serial charge redistribution DAC is given. Figure 1 The DAC shown includes four switches S1-S4, two capacitors of equal value C1 and C2, and a reference voltage source Vref. Specifically, switch S1, known as the redistribution switch, connects C1 and C2 in parallel, averaging and equalizing the voltages of C1 and C2 through charge redistribution. Switches S2 and S3 precharge capacitor C1 to Vref or 0 depending on the data bit value. Switch S4 initially discharges capacitor C2 at the start of a conversion.

[0004] In the prior art, for parallel capacitors (such as Figure 1 The capacitors C1 and C2 in the circuit usually adopt a MOM (Metal-Oxide-Metal) capacitor structure. Figure 2 Shown is the existing MOM capacitor structure. Figure 2 As shown, the upper plate 110 and the lower plate 120 of the MOM capacitor 100 use the same layer of metal and form an interdigital structure. Different layers of metal on the same plate are connected at both ends of the plate through through holes, and the capacitance is mainly provided by the sidewall capacitance between different plates of the same layer of metal.

[0005] For multiple capacitors connected in parallel, the parasitic capacitance between the plates of different capacitors greatly affects the circuit performance. Figure 1 In the DAC shown, digital signal conversion always starts from the LSB (Least Significant Bit) and ends at the MSB (Most Significant Bit). This requires multiple, sequential closures of the corresponding switches during the conversion process. When using existing MOM capacitors for layout, a significant parasitic capacitance Cc is introduced between the top plates of capacitors C1 and C2, significantly limiting DAC performance. Utility Model Content

[0006] In view of the above problems, the purpose of this application is to provide a capacitor coupling structure, chip and electronic device to reduce the cross-parasitic capacitance between connected plates during multi-capacitor matching, thereby improving circuit performance.

[0007] According to one aspect of the present application, a capacitive coupling structure is provided, wherein the capacitive coupling structure includes at least one capacitor group, the capacitor group is used to provide multi-capacitance matching, each of the capacitor groups includes at least one metal layer, and each of the metal layers includes: a common electrode plate, the common electrode plate includes a common substrate extending along a first direction and an isolation electrode plate and a finger electrode plate extending along a second direction and connected to the common substrate; and a plurality of comb-shaped independent electrodes, each of the independent electrodes forms a capacitor with the common electrode plate, wherein at least two of the common substrates are connected via the isolation electrodes to enclose a plurality of mutually isolated areas, and each of the independent electrodes is surrounded by the common substrate and the isolation electrode plate in the corresponding area, and forms an interdigitated structure with the isolation electrode plate and the finger electrode plate in the area.

[0008] Optionally, the independent electrode plate includes: a first independent electrode plate, which forms a first capacitor with the common electrode plate, and the first independent electrode plate includes a plurality of comb-tooth-shaped first sub-electrode plates; and a second independent electrode plate, which forms a second capacitor with the common electrode plate, and the second independent electrode plate includes a plurality of comb-tooth-shaped second sub-electrode plates, and the area corresponding to the first sub-electrode plate and the area corresponding to the second sub-electrode plate are distributed with a common centroid.

[0009] Optionally, the capacitor group includes multiple layers of the metal layers, and the corresponding areas of each metal layer overlap in the projected areas in the stacking direction of the metal layers. The capacitor group also includes: a first through hole for connecting the first independent plates of each metal layer to form a first capacitor plate; a second through hole for connecting the second independent plates of each metal layer to form a second capacitor plate; and a third through hole for connecting the common plates of each metal layer to form a third capacitor plate, wherein the first capacitor plate and the third capacitor plate form the first capacitor, and the second capacitor plate and the third capacitor plate form the second capacitor.

[0010] Optionally, the regions of each metal layer are arranged in an array, and the regions include a first region and a second region distributed diagonally and a third region and a fourth region distributed diagonally, the first sub-plate is located in the first region and the second region, and the second sub-plate is located in the third region and the fourth region.

[0011] Optionally, the metal layer includes: a first metal layer, in which the first region and the second region of the first metal layer are connected and separated from the third region and the fourth region; a second metal layer, in which the regions of the second metal layer are separated from each other; and a third metal layer, in which the third region and the fourth region of the third metal layer are connected and separated from the first region and the second region, and in the stacking direction of the metal layers, the first metal layer or the third metal layer is only adjacent to the second metal layer.

[0012] Optionally, the first independent electrode plate further includes a first connecting plate, which connects the first sub-plates of the first region and the second region on the first metal layer, and the second independent electrode plate further includes a second connecting plate, which connects the second sub-plates of the third region and the fourth region on the third metal layer.

[0013] Optionally, the common substrate includes a first common substrate and a second common substrate, the isolation plate includes a first isolation plate and a second isolation plate, and in each metal layer, the first common substrate and the first isolation plate are located on the four sides of the capacitor group, the second common substrate is located between adjacent first common substrates, isolating the adjacent areas in the second direction, and the second isolation plate is located between adjacent first isolation plates, isolating the adjacent areas in the first direction.

[0014] Optionally, the common plate also includes an extension plate extending from the second isolation plate, and the extension plates connected to different second isolation plates are connected to the isolation plates on both sides of the same first common substrate via corresponding second common substrates to form different connection channels between the different extension plates, wherein in the first metal layer and the third metal layer, the first common substrates to which the second isolation plates are connected are different.

[0015] According to another aspect of the present application, a chip is provided, wherein the chip includes the capacitive coupling structure as described in any one of the above items.

[0016] Optionally, the chip includes a digital-to-analog converter or an analog-to-digital converter.

[0017] According to a third aspect of the present application, an electronic device is provided, wherein the electronic device includes the capacitive coupling structure as described in any one of the above

[0018] According to the capacitive coupling structure, chip and electronic device provided in the present application, isolation between independent plates in the same capacitor group and isolation between independent plates between different capacitor groups are achieved by surrounding the independent plates with a common plate, which effectively reduces the cross-parasitic capacitance between independent plates during multi-capacitor matching and is conducive to improving circuit performance.

[0019] Furthermore, by splitting each independent plate into multiple sub-plates, the areas corresponding to the sub-plates of different independent plates are distributed using a common centroid method to reduce the impact of process gradient differences, which is conducive to improving capacitance matching accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic circuit diagram of a DAC is shown;

[0022] Figure 2 The MOM capacitor structure of prior art is shown;

[0023] Figure 3 A schematic diagram showing a capacitive coupling structure according to a first embodiment of the present application is shown;

[0024] Figure 4 A schematic diagram of the common centroid distribution is shown;

[0025] Figure 5 A three-dimensional schematic diagram showing a capacitive coupling structure according to a second embodiment of the present application;

[0026] Figure 6 Show Figure 5 A plan view of the first metal layer;

[0027] Figure 7 Show Figure 5 A schematic plan view of the second metal layer;

[0028] Figure 8 Show Figure 5 A schematic plan view of the third metal layer;

[0029] Figure 9 Show Figure 5 Schematic diagram of the projection of the through hole on the first metal layer;

[0030] Figure 10 Show Figure 5 Schematic diagram of the projection of the through hole on the third metal layer. DETAILED DESCRIPTION

[0031] Various embodiments of the present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.

[0032] Certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different terms to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in their functions.

[0033] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0034] The present application discloses a capacitive coupling structure, which is used to provide a capacitor bank with multi-capacitance matching.

[0035] Figure 3 The schematic structure diagram of the capacitive coupling structure of the first embodiment of the present application is shown in FIG. Figure 3 The capacitive coupling structure 200 shown includes a capacitor group that provides three capacitors for matching. However, it should be understood that the present application should not be limited to this. For example, each capacitor group can also provide other numbers (such as 2, 4, 5, etc.) of capacitors for matching. In addition, according to actual needs, a single capacitor group can also be used as a repeated unit structure in the capacitor plate structure to provide a larger number of capacitor matching. Figure 3 The capacitive coupling structure of the present application is further described.

[0036] like Figure 3 As shown, each capacitor group includes at least one metal layer, and each metal layer includes a common electrode plate 210 and multiple independent electrodes 220. The common electrode plate 210 and the independent electrodes 220 are isolated by filling an insulating layer. Figure 3, the case where the metal layer includes a first independent electrode plate 220 a , a second independent electrode plate 220 b and a third independent electrode plate 220 c is exemplarily shown.

[0037] The common plate 210 includes a common substrate extending along a first direction (eg Figure 3 The common substrates 211a, 211b and 211c shown in FIG. 1 and the isolation plates (eg, Figure 3 Isolation plates 212a, 212b, 212c, and 212d) and finger plates (e.g. Figure 3 Finger plates 213a, 213b and 213c are shown).

[0038] The independent plates 220 are comb-shaped. Specifically, taking the first independent plate 220a as an example, the independent plates 220 include an independent substrate 221 extending along a first direction and a metal strip 222 extending along a second direction and connected to the independent substrate. Each independent plate forms a capacitor with the common plate.

[0039] At least two common substrates are connected via isolation plates to form multiple isolated regions. Each independent plate is surrounded by the common substrate and isolation plates within the corresponding region. The independent plates in each region form an interdigitated structure with the isolation plates and finger plates within the region.

[0040] Still taking the first independent plate 220a as an example, Figure 3 As shown, the common substrates 211a, 211b and the isolation plates 212a and 212b form a first area to accommodate the first independent plate 220a. In the first area, the isolation plates 212a, 212b or the finger plates 213a, 213b and 213c are evenly arranged with equal intervals from the metal strips 222 to form an interdigitated structure, that is, the distance between each finger plate and its adjacent metal strip or isolation plate is equal.

[0041] Furthermore, in some embodiments, each capacitor bank includes multiple metal layers, with adjacent metal layers isolated by insulating layers. The metal layers are arranged so that the projections of corresponding regions along the direction of the metal layer stacking overlap. The capacitor bank also includes multiple through-holes for connecting common plates between the metal layers or connecting identical independent plates between the metal layers. The multi-layer metal layer design facilitates increased capacitance density.

[0042] It should be noted that the common substrate and the isolation plate of each metal layer common electrode are connected through through holes, or the independent substrate connecting the independent plates is connected (that is, the projection of the through hole in the stacking direction falls on the common substrate, the isolation plate or the independent substrate), so as to avoid the influence of the through hole on the capacitance of the capacitor.

[0043] In addition, it should be understood that an opening should be provided in at least one metal layer in each region to facilitate voltage access to the common plate 210 and each independent plate 220 .

[0044] According to the capacitor coupling structure provided in the present application, isolation between independent plates in the same capacitor group and isolation between independent plates between different capacitor groups are achieved by surrounding the common plate with the independent plate, which effectively reduces the cross-parasitic capacitance between independent plates during multi-capacitor matching and is conducive to improving circuit performance.

[0045] Based on the actual demand for the number of capacitors in analog circuits (such as ADCs and DACs), this application also provides a second embodiment for matching an even number of capacitors. Specifically, for each capacitor group, the independent plates include a first independent plate and a second independent plate. The first independent plate and the common plate form a first capacitor, and the second independent plate and the common plate form a second capacitor.

[0046] Figure 4 A schematic diagram of a common centroid distribution is shown. In some embodiments, the first independent plate is split into multiple first sub-plates, and the second independent plate is split into multiple second sub-plates, with one first sub-plate or one second sub-plate provided in each region. Distributing the regions corresponding to the first and second sub-plates using a common centroid layout method helps reduce the impact of process gradient differences, thereby improving capacitance matching accuracy.

[0047] It should be noted that in Figure 4 In the figure, the first independent plate and the second independent plate are each divided into four sub-plates as an example. However, it should be understood that the first independent plate and the second independent plate can also be divided into a smaller number of sub-plates (for example, two, which will be described in detail below) or a larger number of sub-plates (for example, 8, etc.). The more sub-plates there are, the higher the matching accuracy of the capacitor.

[0048] Furthermore, in the second embodiment of the present application, multiple metal layers can also be provided to increase the capacitance value. Accordingly, the capacitor bank further includes a first through-hole, a second through-hole, and a third through-hole. The first through-hole is used to connect the first independent plates of each metal layer to form a first capacitor plate; the second through-hole is used to connect the second independent plates of each metal layer to form a second capacitor plate; and the third through-hole is used to connect the common plate of each metal layer to form a third capacitor plate. The first capacitor plate and the third capacitor plate form a first capacitor, and the second capacitor plate and the third capacitor plate form a second capacitor.

[0049] Figure 5 FIG2 shows a schematic three-dimensional diagram of the capacitor layout of the second embodiment of the present application. Figure 5 In the embodiment, the first independent plate and the second independent plate each include two sub-plates as an example.

[0050] Furthermore, in a second embodiment of the present application, the common substrate of the common plate includes a first common substrate and a second common substrate, and the isolation plate of the common plate includes a first isolation plate and a second isolation plate. In each metal layer, the first common substrate and the first isolation plate are located on four sides of the capacitor bank, the second common substrate is located between two first common substrates to isolate adjacent regions in the second direction, and the second isolation plate is located between adjacent first isolation plates to isolate adjacent regions in the first direction.

[0051] like Figure 5 As shown, each metal layer is surrounded by a common electrode plate of that metal layer to form a 2×2 area, with the first and second areas diagonally distributed, and the third and fourth areas diagonally distributed. The corresponding areas of different metal layers overlap in the projected areas along the metal layer stacking direction. The first independent electrode plate of each metal layer includes two comb-shaped first sub-plates located in the first and second areas, and the second independent electrode plate of each metal layer includes two comb-shaped second sub-plates located in the third and fourth areas.

[0052] To facilitate the connection of the common electrode plates or corresponding independent electrode plates of each metal layer, and to facilitate the isolation of the first independent electrode plates and the second independent electrode plates of adjacent metal layers, the metal layer includes a first metal layer 310, a second metal layer 320, and a third metal layer 330. In the stacking direction of the metal layers, the first metal layer 310 and the third metal layer 330 are only adjacent to the second metal layer 320.

[0053] Figure 6 shows a schematic plan view of the first metal layer in the stacking direction, Figure 7 shows a schematic plan view of the second metal layer in the stacking direction, Figure 8 The schematic diagram of the third metal layer in the stacking direction is shown below. Figure 6-8 Each metal layer is further described.

[0054] like Figure 6 As shown, in the first metal layer 310, the common plate includes a common substrate, an isolation plate, and finger plates. The common substrate includes first common substrates 11a and 11b and second common substrates 12a and 12b; the isolation plates include first isolation plates 13a, 13b, 13c, and 13d, and second isolation plates 14a and 14b. The finger plates are not specifically labeled in the figure.

[0055] The common substrate and the isolation plate enclose the first region A to the fourth region D. The two first sub-plates 21a and 21b of the first independent plate are located in the diagonally distributed first region A and the second region B, respectively; the two second sub-plates 31a and 31b of the second independent plate are located in the diagonally distributed third region C and the fourth region D, respectively.

[0056] Specifically, two first common substrates 11a and 11b are arranged in parallel. The two ends of the first common substrate 11a are connected to first isolation plates 13a and 13c, respectively. The two ends of the first common substrate 11b are connected to first isolation plates 13b and 13d, respectively. First isolation plates connected to the same first common substrate extend in the same direction, while first isolation plates connected to different first common substrates extend in opposite directions. This ensures that the first common substrates 11a and 11b and the first isolation plates 13a to 13d form the four sides of the capacitor bank in the first metal layer.

[0057] Second common substrates 12a and 12b are located between first common substrates 11a and 11b. Second common substrate 12a is connected to first isolation plate 13, isolating first region A from fourth region D in the second direction. Second common substrate 12b is connected to first isolation plate 13c, isolating third region C from second region B in the second direction.

[0058] The second isolation plate 14a is connected to the first common substrate 11a and is located between the first isolation plates 13a and 13c, and is used to isolate the first region A from the third region C in the first direction. The second isolation plate 14b is connected to the first common substrate 11b and is located between the first isolation plates 13d and 13b, and is used to isolate the fourth region D from the second region B in the first direction.

[0059] Furthermore, in order to achieve connection between corresponding plates of each metal layer, in the first metal layer 310 , the first region A is connected to the second region B, and is isolated from the third region C and the fourth region D.

[0060] The common plate also includes an extension plate extending from the second isolation plate. The extension plate extends in the same direction as the second isolation plate to which it is connected. The extension plates connected to different second isolation plates are connected to the isolation plates on both sides of the same first common substrate via the corresponding second common substrate, thereby forming a connection channel between different areas. Figure 6 The extension plate 15a extending from the second isolation plate 14a is connected to the second common substrate 12b; the extension plate 15b extending from the second isolation plate 14b is connected to the second common substrate 12a, thereby forming a connection channel between the first area A and the second area B between the two extension plates 15a and 15b.

[0061] The first independent electrode plate further includes a first connecting plate 22 for connecting the first sub-plate 21a in the first region A and the first sub-plate 21b in the second region B.

[0062] like Figure 7As shown, in the second metal layer 320, the common plate includes a common substrate, an isolation plate, and a finger plate. The common substrate includes first common substrates 41a and 41b and a second common substrate 42; the isolation plate includes first isolation plates 43a and 43b and a second isolation plate 44. The finger plates are not specifically labeled in the figure.

[0063] The common substrate and the isolation plate enclose a mutually isolated first region A, a second region B, a third region C, and a fourth region D. The two first sub-plates 51a and 51b of the first independent plate are located in the diagonally distributed first region A and second region B, respectively; the two second sub-plates 61a and 61b of the second independent plate are located in the diagonally distributed third region C and fourth region D, respectively.

[0064] Specifically, the two first common substrates 41a and 41b are distributed in parallel, the two first isolation plates 43a and 43b are distributed in parallel, and both ends of the first isolation plates 43a and 43b are connected to the first common substrates 41a and 41b respectively, so that the first common substrates 41a and 41b and the first isolation plates 43a and 43b form the four sides of the capacitor group in the second metal layer.

[0065] A second common substrate 42 is positioned between first common substrates 41a and 41b, with its ends connected to first isolation plates 43a and 43b, respectively. A second isolation plate 44 is positioned between first isolation plates 43a and 43b, with its ends connected to first common substrates 41a and 41b, respectively. The second isolation plate 44 is also connected to the second common substrate 42, thereby forming mutually isolated first to fourth regions A, D, and D.

[0066] like Figure 8 As shown, in the third metal layer 330, the common plate includes a common substrate, an isolation plate, and finger plates. The common substrate includes first common substrates 71a and 71b and second common substrates 72a and 72b; the isolation plates include first isolation plates 73a, 73b, 73c, and 73d, and second isolation plates 74a and 74b. The finger plates are not specifically labeled in the figure.

[0067] The common substrate and the isolation plate enclose the first region A to the fourth region D. The two first sub-plates 81a and 81b of the first independent plate are located in the diagonally distributed first region A and second region B, respectively; the two second sub-plates 91a and 91b of the second independent plate are located in the diagonally distributed third region C and fourth region D, respectively.

[0068] Specifically, two first common substrates 71a and 71b are arranged in parallel. The two ends of the first common substrate 71a are connected to first isolation plates 73a and 73c, respectively. The two ends of the first common substrate 71b are connected to first isolation plates 73b and 73d, respectively. The first isolation plates connected to the same first common substrate extend in the same direction, while the first isolation plates connected to different first common substrates extend in opposite directions. This ensures that the first common substrates 71a and 71b and the first isolation plates 73a to 73d form the four sides of the capacitor bank in the third metal layer.

[0069] The second common substrates 72a and 72b are located between the first common substrates 71a and 71b. The second common substrate 72a is connected to the first isolation plate 73d and is used to isolate the first region A from the fourth region D in the second direction. The second common substrate 72b is connected to the first isolation plate 73b and is used to isolate the third region C from the second region B in the second direction.

[0070] The second isolation plate 74a is connected to the first common substrate 71a and is located between the first isolation plates 73a and 73c, and is used to isolate the first region A from the third region C in the first direction. The second isolation plate 74b is connected to the first common substrate 71b and is located between the first isolation plates 73d and 73b, and is used to isolate the fourth region D from the second region B in the first direction.

[0071] Furthermore, in order to achieve connection between corresponding plates of each metal layer, in the third metal layer 330 , the third region C and the fourth region D are connected, and separated from the first region A and the second region B.

[0072] The common plate also includes an extension plate extending from the second isolation plate. The extension plate extends in the same direction as the second isolation plate to which it is connected. The extension plates connected to different second isolation plates are connected to the isolation plates on both sides of the same first common substrate via the corresponding second common substrate, thereby forming a connection channel between different areas. Figure 8 In the third metal layer 330, the extension plate 75a extending from the second isolation plate 74a is connected to the second common substrate 72a; the extension plate 75b extending from the second isolation plate 74b is connected to the second common substrate 72b, thereby forming a connection channel between the third area C and the fourth area D between the two extension plates 75a and 75b.

[0073] The second common plate further includes a second connecting plate 92 for connecting the second sub-plate 91 a in the third region C and the second sub-plate 91 b in the fourth region D.

[0074] It should be noted that the width of the overlapping projections of the common plates and independent plates in each metal layer along the stacking direction is the same. For example, the first common substrate 11a in the first metal layer 310, the first common substrate 41a in the second metal layer 320, and the first common substrate 71a in the third metal layer 330 are the same width. The second isolation plates 14a and 14b in the first metal layer 310, the second isolation plate 44 in the second metal layer 320, and the second isolation plates 74a and 74b in the third metal layer 330 are the same width.

[0075] In some embodiments, to improve capacitance matching accuracy, the spacing between any adjacent common plates and independent plates in the first and second directions is equal. For example, within each region, the distance between any two adjacent fingers in the interdigital structure is equal and equal to f. The distance from the first connecting plate 22 to the extension plates 15a and 15b is also equal and equal to f. The distance from the second common substrate 12a / 12b to the first and second sub-plates on either side of it is also f, where f is a positive number.

[0076] To allow the connection channel between the first region A and the second region B in the first metal layer 310 to accommodate the first connection plate, the distance between the extension plates 15a and 15b should be greater than the width of the first connection plate. Similarly, to allow the connection channel between the third region C and the fourth region D in the third metal layer 330 to accommodate the second connection plate, the distance between the extension plates 75a and 75b should be greater than the width of the second connection plate.

[0077] For example, since the extension plates 15a and 15b in the first metal layer 310 extend from the sides of the second isolation plates 14a and 14b respectively close to different sides of the capacitor group in the first direction, the widths of the extension plates 15a and 15b and the connecting plate 22 in the first direction are both d, and the spacing between any adjacent common plates and independent plates in the first direction / second direction is equal and f. Accordingly, the width of the second isolation plates 14a and 14b in the first direction is at least 3d+2f, where d is a positive number.

[0078] It should be understood that in the second embodiment provided in this application, only three metal layers are used as an example. However, this application may also include more metal layers stacked in sequence to achieve a higher capacitance. At the same time, in order to achieve isolation between the first independent electrode plate and the second independent electrode plate in different metal layers, in the stacking direction of the metal layers, the first metal layer and the third metal layer can only be adjacent to the second metal layer.

[0079] Figure 9 Show Figure 5 Schematic diagram of the projection of the through hole on the first metal layer; Figure 10 Show Figure 5 Schematic diagram of the projection of the through hole on the third metal layer. Figure 9 and10 As shown, in the embodiment of the present application, the projection of the first through hole 341 in the stacking direction falls on the independent substrate of the first independent electrode plate of each metal layer; the projection of the second through hole 342 in the stacking direction falls on the independent substrate of the second independent electrode plate of each metal layer; and the projection of the third through hole 343 in the stacking direction falls on the common substrate and isolation plate of the common electrode plate of each metal layer. The through holes connect the common substrate and isolation plate of the common electrode plates of each metal layer or connect the independent substrates of the corresponding independent electrodes, thereby preventing the through holes from affecting the capacitor.

[0080] According to the capacitor coupling structure provided in the present application, isolation between independent plates in the same capacitor group and isolation between independent plates between different capacitor groups are achieved by surrounding the common plate with the independent plate, which effectively reduces the cross-parasitic capacitance between independent plates during multi-capacitor matching and is conducive to improving circuit performance.

[0081] Furthermore, by splitting each independent plate into multiple sub-plates, the areas corresponding to the sub-plates of different independent plates are distributed using a common centroid method to reduce the impact of process gradient differences, which is conducive to improving capacitance matching accuracy.

[0082] Furthermore, the present application also provides a chip, which can be used to provide analog circuits such as ADC or DAC. The chip includes the capacitive coupling structure provided by the present application, and thus the chip also has any beneficial effects of the above-mentioned capacitive coupling structure.

[0083] Furthermore, the present application also provides an electronic device, which includes the capacitive coupling structure provided by the present application. Therefore, the electronic device also has any of the above-mentioned beneficial effects, which will not be described in detail here.

[0084] The embodiments of the present application are as described above, and these embodiments do not describe all details in detail, nor do they limit the present application to specific embodiments. Obviously, based on the above description, many modifications and variations can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The scope of protection of the present application shall be based on the scope defined by the claims of the present application.

Claims

1. A capacitive coupling structure, characterized in that: The capacitive coupling structure includes at least one capacitor group, and the capacitor group is used to provide multi-capacitance matching. Each of the capacitor groups includes at least one metal layer, and each of the metal layers includes: A common plate, the common plate comprising a common substrate extending along a first direction, and an isolation plate and a finger plate extending along a second direction and connected to the common substrate; and A plurality of comb-shaped independent plates, each of which forms a capacitor with the common plate. Among them, at least two of the common substrates are connected through the isolation plates to enclose a plurality of mutually isolated areas, and each of the independent plates is surrounded by the common substrate and the isolation plates in the corresponding area, and forms an interdigitated structure with the isolation plates and the finger plates in the area.

2. The capacitive coupling structure according to claim 1, wherein: The independent plate comprises: A first independent electrode plate, forming a first capacitor with the common electrode plate, wherein the first independent electrode plate includes a plurality of comb-shaped first sub-electrode plates; and A second independent electrode plate forms a second capacitor with the common electrode plate, wherein the second independent electrode plate includes a plurality of comb-shaped second sub-electrode plates. The region corresponding to the first sub-plate and the region corresponding to the second sub-plate are distributed with a common centroid.

3. The capacitive coupling structure according to claim 2, wherein: The capacitor group includes a plurality of metal layers, and projection areas of corresponding regions of the metal layers in the stacking direction of the metal layers overlap. The capacitor bank further comprises: a first through hole, for connecting the first independent plates of each of the metal layers to form a first capacitor plate; a second through hole, for connecting the second independent plates of each of the metal layers to form a second capacitor plate; and The third through hole is used to connect the common plates of the metal layers to form a third capacitor plate. The first capacitor plate and the third capacitor plate form the first capacitor, and the second capacitor plate and the third capacitor plate form the second capacitor.

4. The capacitive coupling structure according to claim 3, wherein: The regions of each metal layer are arranged in an array, and the regions include a first region and a second region that are diagonally distributed, and a third region and a fourth region that are diagonally distributed. The first sub-plate is located in the first region and the second region, and the second sub-plate is located in the third region and the fourth region.

5. The capacitive coupling structure according to claim 4, wherein: The metal layer comprises: a first metal layer, wherein the first region and the second region of the first metal layer are connected and separated from the third region and the fourth region; a second metal layer, wherein the regions of the second metal layer are isolated from each other; and a third metal layer, wherein the third region of the third metal layer is connected to the fourth region and is isolated from the first region and the second region; In the stacking direction of the metal layers, the first metal layer or the third metal layer is adjacent to only the second metal layer.

6. The capacitive coupling structure according to claim 5, wherein: The first independent plate further includes a first connecting plate, which connects the first sub-plates in the first region and the second region on the first metal layer. The second independent electrode plate further includes a second connecting plate. On the third metal layer, the second connecting plate connects the second sub-plates in the third region and the fourth region.

7. The capacitive coupling structure according to claim 5, wherein: The common substrate includes a first common substrate and a second common substrate, The isolation plate includes a first isolation plate and a second isolation plate, On each of the metal layers, the first common substrate and the first isolation plate are located on four sides of the capacitor group. The second common substrate is located between adjacent first common substrates and separates adjacent areas in the second direction. The second isolation plate is located between adjacent first isolation plates and separates adjacent regions in the first direction.

8. The capacitive coupling structure according to claim 7, wherein: The common plate further includes an extension plate extending from the second isolation plate, and the extension plates connected to different second isolation plates are connected to the isolation plates on both sides of the same first common substrate via corresponding second common substrates, so as to form different connection channels between the different extension plates. Wherein, in the first metal layer and the third metal layer, the first common substrate to which the second isolation plate is connected is different.

9. A chip, characterized in that: The chip includes the capacitive coupling structure according to any one of claims 1 to 8.

10. The chip according to claim 9, characterized in that The chip includes a digital-to-analog converter or an analog-to-digital converter.

11. An electronic device, characterized in that: The electronic device comprises the capacitive coupling structure according to any one of claims 1 to 8.

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