Single photon avalanche photodiode and electronic device including same

Abstract

The utility model provides a single photon avalanche photodiode and an electronic device comprising the same, and the single photon avalanche photodiode comprises a P-type substrate layer, an N-type buried layer, a P-type epitaxial layer arranged on the P-type substrate layer, a P-type trap arranged on the N-type buried layer, a P-type groove arranged in the P-type epitaxial layer, a P-type groove arranged in the P-type epitaxial layer, and an N-type groove arranged in the N-type epitaxial layer, the upper surface of the P-type trap is lower than the upper surface of the P-type epitaxial layer, and the upper surface of the N-type buried layer is lower than the upper surface of the N-type epitaxial layer. The lower surface of the P-type well is in contact with the N-type buried layer, the P-type well and the N-type buried layer form a PN junction, the P + region is arranged in the P-type epitaxial layer, the lower surface of the P + region is higher than the upper surface of the N-type buried layer, the P + region surrounds the P-type well and the N + region and is in contact with the N-type buried layer, the lower surface of the N + region is below the upper surface of the N-type buried layer, and the N + region surrounds the P-type well.

Description

Technical Field

[0001] The utility model relates to the field of radio frequency integrated circuits, and in particular to a single-photon avalanche photodiode and an electronic device comprising the same. Background Art

[0002] A single-photon detector is a photoelectric detection device that counts incident single photons and can detect extremely weak light signals. The input light intensity that a single-photon detector can detect can reach the lowest level of single photons, thereby enabling the detection and counting of single photons. Single-photon detection technology can be applied to medical diagnosis, astronomical observation, spectral measurement, quantum communication and other fields. Among single-photon detectors, the single-photon avalanche diode (SPAD) detector is a very sensitive detector that achieves internal signal amplification through the avalanche process and is the most commonly used photosensitive unit in lidar.

[0003] When a SPAD detector operates in Geiger mode, the absorption of a photon or the generation of an electron-hole pair by thermal fluctuations can trigger a strong avalanche, multiplying the photocurrent. Geiger mode refers to the situation where the SPAD detector operates at a bias voltage slightly higher than its avalanche voltage. The avalanche current of the SPAD detector is amplified and read out by subsequent circuitry to produce a counting pulse output.

[0004] The structural design of a single-photon avalanche diode requires comprehensive consideration of various parameters, including basic parameters such as PN junction depth, ion implantation concentration, breakdown voltage, and edge breakdown. Furthermore, performance parameters such as detection efficiency, duty cycle, and dark count must be considered, along with production indicators such as fill factor, yield rate, and manufacturing cost.

[0005] Currently, SPAD detectors come in a wide variety of structural forms, including single-ended and dual-ended P-on-N and N-on-P structures, as well as a range of new and innovative back-illuminated and stacked structures. However, SPAD detectors' dark count, fill factor, and yield remain technical challenges that require continuous improvement. Dark count refers to the possibility that a single-photon detector, such as a SPAD, misinterprets stray light (non-signal light) and noise as valid light signals. This misoperation is known as dark counting. The fill factor refers to the ratio of the area of ​​the photosensitive region of a single-photon detector, such as a SPAD, to the total area of ​​the single-photon detector. The yield rate refers to the ratio of the number of qualified products that ultimately pass testing on a production line to the theoretical output of the input material. With continuous technological advancements, the size of SPAD detectors continues to shrink. However, because SPAD detectors must operate in high-voltage environments, the positive and negative electrodes must maintain a certain distance to avoid breakdown and other issues. Therefore, the fill factor of traditional SPAD detectors cannot be further improved while ensuring breakdown prevention. Existing technology can improve the fill factor of small-size SPAD detectors through 3D stacking technology, but the 3D stacking process is complex, the manufacturing cost is high, and the yield rate is low.

[0006] Therefore, a SPAD detector with high fill ratio, low dark count, high yield and low cost is desired. Summary of the Invention

[0007] The present invention optimizes the structure of the SPAD detector, fabricates the multiplication zone at a depth far away from the substrate surface, and reduces dark counts caused by surface defects. The photon detection efficiency (PDE) is improved by means of light trapping structures, and the anode and cathode are designed in the substrate (such as on the N-type buried layer) and on the incident light surface of the substrate, respectively, so that the two electrodes maintain a long distance in the vertical direction, thereby avoiding the premature breakdown effect. Since the incident light surface does not require a guard ring structure, the fill factor of small-sized SPADs is effectively improved. The technical solution of the present invention can be directly applied to the front-illuminated process. The front-illuminated process is more stable than the 3D stacking process, has lower difficulty, higher production yield, and lower cost investment.

[0008] One aspect of the present invention provides a single-photon avalanche photodiode, comprising: a P-type substrate layer, an N-type buried layer, arranged on the P-type substrate layer, a P-type epitaxial layer, arranged on the N-type buried layer, a P-type well, arranged in the P-type epitaxial layer, wherein the upper surface of the P-type well is lower than the upper surface of the P-type epitaxial layer, the lower surface of the P-type well contacts the N-type buried layer, and the P-type well and the N-type buried layer form a PN junction; a P+ region, arranged in the P-type epitaxial layer, the lower surface of the P+ region is higher than the upper surface of the N-type buried layer, and the P+ region surrounds the P-type well; and an N+ region contacts the N-type buried layer, the lower surface of the N+ region is below the upper surface of the N-type buried layer, and the N+ region surrounds the P-type well.

[0009] According to the single-photon avalanche photodiode of one aspect of the present invention, the upper surface of the P+ region is aligned with the upper surface of the P-type epitaxial layer.

[0010] According to the single-photon avalanche photodiode of one aspect of the present invention, a multiplication region is formed between the P-type well and the N-type buried layer.

[0011] According to the single-photon avalanche photodiode of one aspect of the present invention, the N+ region is farther away from the P-type well than the P+ region in the radial direction.

[0012] The single-photon avalanche photodiode according to one aspect of the present invention further includes a negative electrode and a positive electrode, wherein the P+ region is connected to the negative electrode, and the N+ region is connected to the positive electrode.

[0013] According to one aspect of the present invention, the single-photon avalanche photodiode further includes a dielectric layer and a transition layer, wherein the dielectric layer is disposed on the P-type epitaxial layer, and the transition layer is disposed between the dielectric layer and the P-type epitaxial layer.

[0014] The single-photon avalanche photodiode according to one aspect of the present invention further includes a trench surrounding the P-type well and penetrating the P-type epitaxial layer.

[0015] According to the single-photon avalanche photodiode of one aspect of the present invention, the trench is provided above the N+ region, and the N+ region is connected to the positive electrode provided in the trench.

[0016] According to the single-photon avalanche photodiode of one aspect of the present invention, the trench is filled with a dielectric, and the dielectric isolates the positive electrode from the P-type extension layer.

[0017] According to an aspect of the single-photon avalanche photodiode of the present invention, the dielectric comprises silicon dioxide.

[0018] According to one aspect of the present invention, the single-photon avalanche photodiode further includes a light trapping structure, which is disposed in the P-type epitaxial layer and has an upper surface aligned with an upper surface of the P-type epitaxial layer.

[0019] According to the single-photon avalanche photodiode according to one aspect of the present invention, the light trapping structure comprises silicon dioxide.

[0020] According to one aspect of the present invention, the single-photon avalanche photodiode further includes a P-rich region, which is arranged in the P-type epitaxial layer and between the trench and the P-type well, and the doping concentration of the P-rich region is higher than the doping concentration of the P-type well.

[0021] According to the single-photon avalanche photodiode of one aspect of the present invention, the upper surface of the P-rich region is lower than the upper surface of the P-type epitaxial layer, and the lower surface of the P-rich region is higher than the lower surface of the P-type epitaxial layer.

[0022] According to the single-photon avalanche photodiode of one aspect of the present invention, the thickness of the P-type epitaxial layer is approximately 3 micrometers.

[0023] According to the single-photon avalanche photodiode of one aspect of the present invention, the upper surface of the N+ region is aligned with the upper surface of the N-type buried layer or is above the upper surface of the N-type buried layer.

[0024] One aspect of the present invention provides an electronic device including the single-photon avalanche photodiode described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 1 is a schematic diagram showing a cross-sectional structure of a conventional single-photon avalanche diode photodetector;

[0026] Figure 2 is a schematic cross-sectional structural diagram of a SPAD detector according to an embodiment of the present disclosure;

[0027] Figure 3 is an example top view of a SPAD detector according to an embodiment of the present disclosure;

[0028] Figure 4 is a schematic cross-sectional structural diagram of another SPAD detector according to an embodiment of the present disclosure;

[0029] Figure 5 An electronic device including a SPAD detector according to at least one embodiment of the present disclosure;

[0030] Figure 6 is an example method for manufacturing a SPAD detector according to at least one embodiment of the present disclosure;

[0031] Figure 7 is a flow chart of an example method for manufacturing another SPAD detector according to at least one embodiment of the present disclosure;

[0032] Figure 8 FIG. 4 is a schematic diagram of a fabrication process of a single-photon avalanche diode according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] Before proceeding with the detailed description below, it may be helpful to set forth the definitions of certain words and phrases used throughout this patent document. The terms "couple," "connect," and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmit," "receive," and "communicate," and their derivatives, encompass both direct and indirect communication. The terms "include," "comprise," and their derivatives, mean including, but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives mean including, included within, interconnected, containing, contained within, connected or connected with, coupled or coupled with, communicate with, cooperate with, intertwine, juxtapose, approach, bound or bound with, have, have an attribute of, have a relationship with, or have a relationship with, etc. The term "controller" refers to any device, system, or portion thereof that controls at least one operation. Such a controller may be implemented using hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one of," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be needed. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0034] Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0035] In this patent document, the application combination of modules and the division level of sub-modules are only used for illustration. Without departing from the scope of this disclosure, the application combination of modules and the division level of sub-modules can have different forms.

[0036] Figure 1 FIG is a schematic diagram showing the cross-sectional structure of a conventional single-photon avalanche diode photodetector. Figure 1As shown, a conventional single-photon avalanche diode photodetector may include a substrate, an N+ region 103, a P-type well 104, a P+ region 105, a positive electrode 106, a negative electrode 107, a transition layer 108, a dielectric layer 109, and trapezoidal shallow trench isolation trenches arranged on both sides of the P+ region 105. The N+ region 103 and the P-type well 106 may form a PN junction, and a multiplication region may be formed at the PN junction interface. The substrate may include a P-type substrate layer 101 and a P-type epitaxial layer 102. The N+ region 103 may be connected to the positive electrode 106, and the P+ region 105 may be arranged around the PN structure, and the P+ region 105 may connect the substrate to the negative electrode. The trapezoidal shallow trench isolation trench may be filled with a dielectric such as silicon dioxide. In practical applications, the voltage between the positive and negative electrodes is greater than 20V. To prevent high-voltage breakdown, a guard ring must be placed between the P+ region 105 and the N+ region 103. As the size of SPAD detectors continues to shrink, the guard ring's share of the overall size of the SPAD detector is increasing. For example, a 10μm SPAD detector typically has a guard ring size of approximately 6μm, accounting for 60% of the total size of the SPAD detector. Consequently, the maximum fill factor is only 40%. Clearly, the presence of the guard ring has a significant negative impact on the fill factor of small-sized SPAD detectors.

[0037] Figure 2 Schematic diagram of the cross-sectional structure of a SPAD detector according to an embodiment of the present disclosure.

[0038] like Figure 2 As shown, the SPAD detector according to an embodiment of the present disclosure may include a substrate 201 , an N+ region 205 , a P-type well 206 , a P+ region 207 , a positive electrode 208 , a negative electrode 209 , a transition layer 120 , and a dielectric layer 211 .

[0039] Substrate 201 may be a silicon substrate and may include an upper surface 201a and a lower surface 201b. Upper surface 201a may be the light incident surface. Substrate 201 includes, stacked from bottom to top, a P-type substrate layer 202, an N-type buried layer 203, and a P-type epitaxial layer 204. Specifically, substrate 201 includes a P-type substrate layer 202 disposed at the bottom, an N-type buried layer 203 disposed above the P-type substrate layer 202, and a P-type epitaxial layer 204 disposed above the N-type buried layer 203. The P-type substrate layer 202 is generally doped with a high concentration of P-type and has a low resistivity. The N-type buried layer 203 is generally formed by implanting a high concentration of N-type ions. The P-type epitaxial layer 204 is generally doped with a low concentration of P-type and has a high resistivity. The P-type epitaxial layer 204 is the primary active region for photoelectric conversion. The thickness of the P-type epitaxial layer 204 may be approximately 3 microns, for example, but those skilled in the art will appreciate that other thicknesses are possible.

[0040] The P-type well 206 may be disposed in the P-type epitaxial layer 204. The upper surface of the P-type well 206 may be lower than the upper surface 201a of the P-type epitaxial layer, and the lower surface of the P-type well 206 may contact the N-type buried layer 203. The P-type well 206 and the N-type buried layer 204 may form a PN junction. A multiplication region (indicated by a dotted line) may be formed between the P-type well 206 and the N-type buried layer 203. Figure 2 As shown, a depletion region (indicated by a dotted line) can be formed in the P-type epitaxial layer 204 above the P-type well 206. Assuming that the thickness of the P-type epitaxial layer 204 is about 3 microns, the depth of the multiplication region in the N-type buried layer 203 from the upper surface 201a is also about 3 microns. In this way, the multiplication region is away from the upper surface 201a as the incident light surface, which will help reduce the electrons generated by surface defect impurities under the action of heat to enter the multiplication region, thereby reducing the dark counts generated by the surface. In addition, the N-type buried layer 203 can also isolate the SPAD detector from other low-voltage devices adjacent to the SPAD detector. Since the SPAD detector operates in high-voltage mode, it may cause interference to other devices adjacent to the SPAD. After isolation by the N-type buried layer 204, other low-voltage devices in the circuit are not affected by the high voltage of the SPAD detector, thereby reducing the difficulty of preparing devices other than the SPAD.

[0041] The P+ region 207 may be provided in the P-type epitaxial layer 204. The lower surface of the P+ region 207 may be higher than the upper surface of the N-type buried layer 203, and the upper surface of the P+ region 207 may be aligned with the upper surface of the P-type epitaxial layer 204. The positive electrode 208 may be connected to the P+ region 207, and the negative electrode 209 may be connected to the N+ region 205. Figure 1 The conventional SPAD detector shown requires a guard ring between the P+ region 205 and the N+ region 203 to prevent breakdown. However, the SPAD detector according to the embodiment of the present disclosure can fabricate an N+ region 205 connected to the positive electrode 208 in the N-type buried layer 203, and a P+ region 207 connected to the negative electrode 209 in the P-type epitaxial layer 204. Because the N+ region 205 and the P+ region 207 are vertically separated, the problem of premature breakdown outside the multiplication region can be effectively avoided. In this way, the guard ring can be omitted in the SPAD detector, thereby saving the area of ​​the SPAD detector and effectively improving the fill factor of the SPAD detector.

[0042] Despite Figure 2Although the embodiments of the present disclosure are shown in the form of , those skilled in the art will appreciate that the region of N attribute may be modified to the region of P attribute (for example, the P-type well 206, the P+ region 207, the P-type substrate layer 202, and the P-type epitaxial layer 204 may be correspondingly modified to the region of N attribute), and the region of N attribute may be modified to the region of P attribute accordingly (for example, the N+ region 205 and the N-type buried layer 2034 may be correspondingly modified to the region of P attribute), and the electrode polarity may be modified accordingly (for example, so that the potential of the N+ region is higher than the potential of the P+ region).

[0043] like Figure 2 As shown, the P+ region 207 and the positive electrode 208 can be shared with adjacent SPAD detectors. In this way, the size of the SPAD detector array can be further reduced, thereby further improving the fill factor.

[0044] The P+ region 207 may surround the P-type well 206 . For example, the P+ region 207 may be located above the P-type well 206 and may be in a circular shape. The inner diameter of the P+ region 207 may be larger or smaller than the diameter of the P-type well 206 .

[0045] The N+ region 205 may be disposed in the N-type buried layer 203. The N+ region 205 may be in contact with the N-type buried layer, and the lower surface of the N+ region may be below the upper surface of the N-type buried layer. The upper surface of the N+ region 205 may be aligned with or above the upper surface of the N-type buried layer 203. The N+ region 205 may surround the P-type well 206. The N+ region 205 may be radially farther from the P-type well 206 than the P+ region 207.

[0046] The transition layer 120 may be disposed on the P-type epitaxial layer 204 , and the dielectric layer 211 may be disposed on the transition layer 120 .

[0047] like Figure 2 As shown, the SPAD detector according to an embodiment of the present disclosure may also have a groove 212. The groove 212 may surround the P-type well 206 and pass through the P-type epitaxial layer 204. The groove 212 may be arranged above the N+ region 205, and the N+ region 205 may be connected to the positive electrode 208 arranged in the groove 212. The groove 212 may be filled with a dielectric, which may isolate the positive electrode 208 from the P-type extension layer 204. The dielectric includes silicon dioxide, etc., which may also act as a light trap. In addition, the groove 212 may also isolate the photosensitive area of ​​the current SPAD detector from other SPAD detectors, thereby effectively reducing crosstalk.

[0048] During operation, Figure 2A reverse bias voltage up to the breakdown voltage can be applied between the positive electrode 208 and the negative electrode 209 of the SPAD detector. Because the concentration of the P-type well 206 is much higher than that of the P-type epitaxial layer 204, a strong electric field is generated in the multiplication region formed between the P-type well 206 and the N-type buried layer 203. When electrons pass through the multiplication region, they can move at high speed under the action of the strong electric field and trigger an avalanche effect. Figure 2 The direction indicated by the middle arrow is the drift direction of electrons under the action of the electric field. A depletion region (indicated by the dotted line) is mainly formed in the P-type epitaxial layer 204 near the multiplication region.

[0049] Figure 2 The technical solution can be applied to front-illuminated photoelectric detection equipment. The front-illuminated photoelectric detection equipment using this technical solution has low cost and high yield rate.

[0050] Figure 3 is an example top view of a SPAD detector according to an embodiment of the present disclosure.

[0051] like Figure 3 As shown, a circular P+ region 207 can be formed between reference numerals 1 and 3. A negative electrode 209 made of a metal material (e.g., tungsten) can be extended from the P+ region 207. A circular P-type well 206 can be formed in reference numeral 2. The P-type well 206 can be disposed in the P-type epitaxial layer 204. The upper surface of the P-type well 206 can be lower than the upper surface 201a of the P-type epitaxial layer 204, and the lower surface of the P-type well 206 can be in contact with the N-type buried layer 203. A circular trench 212 can be formed between reference numerals 4 and 7. An N+ region 205 in a circular shape (e.g., a rounded square shape) formed by reference numerals 5 and 6 can be disposed in the trench 212. A negative electrode 209 made of a metal material (e.g., tungsten) can be extended from the N+ region 205. Although the above regions are shown as circular rings, such as rounded square shapes, other shapes are also possible, for example, commonly used shapes such as octagons.

[0052] Figure 4 Schematic diagram of the cross-sectional structure of another SPAD detector according to an embodiment of the present disclosure.

[0053] For the sake of brevity and to avoid redundancy, Figure 4 Zhongyu Figure 2 The same components will not be described again.

[0054] like Figure 4 As shown, the SPAD detector may further include a light trapping structure 213 and a P-rich region 214 .

[0055] The light-trapping structure 213 can be arranged in the P-type epitaxial layer 204 and the upper surface of the light-trapping structure 213 is aligned with the upper surface 201a of the P-type epitaxial layer 204. An inverted trapezoidal or inverted pyramidal light-trapping groove can be formed on the upper surface 201a by an etching process. The light-trapping structure 213 can be formed by filling silicon dioxide in the light-trapping groove. Under the effect of the silicon-silicon dioxide interface reflection in the light-trapping structure 213, the optical path of light in the SPAD detector can be increased, thereby improving the light absorption efficiency. This light-trapping structure is similar to the light-trapping structure used in the existing 3D stacking process and will not be described in detail here. However, in the 3D stacking process, the light-trapping structure needs to be fabricated on the back side of the substrate, which increases the research and development and processing technology of the back side process. However, the SPAD detector according to the present disclosure can use the shallow trench process of CMOS to realize the fabrication of the light-trapping structure 213. The shallow trench process of CMOS is mature and stable, and does not require additional research and development and production cost investment.

[0056] The P-rich region 214 can be arranged in the P-type epitaxial layer 204 and between the trench 212 and the P-type well 206. The doping concentration of the P-rich region 214 can be higher than the doping concentration of the P-type well 206. The upper surface of the P-rich region 214 can be lower than the upper surface of the P-type epitaxial layer 204, and the lower surface of the P-rich region 214 can be higher than the lower surface of the P-type epitaxial layer 204. A P-type epitaxial layer 204 can exist between the P-rich region 214 and the N-type buried layer 203. Since the P-rich region 214 can surround the area of ​​the outer circle of the P-type well 206, the higher concentration of P-type ions after adding the P-rich region 214 can form a potential barrier around the P-type well 206, and the depletion region boundary near the trench 212 can be formed in the P-rich region 214. Therefore, the electric field in the SPAD detector is funnel-shaped as a whole, as shown in FIG. Figure 4 In this way, electrons generated in the region of substrate 201 near trench 212 can drift toward the multiplication region under the action of the electric field. This allows electrons that originally entered N+ region 205 from the side of the PN junction to also enter the multiplication region under the action of the electric field, thereby increasing the probability of avalanche occurrence.

[0057] Figure 5 An electronic device including a SPAD detector according to at least one embodiment of the present disclosure is disclosed.

[0058] like Figure 5 As shown, the electronic device 500 includes a processor 510, a memory 520, and a SPAD detector 530. The SPAD detector 530 is a SPAD detector according to any embodiment of the present disclosure, which is, for example, connected to the processor 510 and controlled to detect light intensity, for example, to feed the light intensity back to a functional unit in the processor 510 responsible for detecting an image, and the functional unit can, for example, generate an image based on the detected light intensity.

[0059] The memory 520 includes one or more computer program modules 521. The one or more computer program modules 521 are stored in the memory 520 and can be configured to be read and executed by the processor 510. The one or more computer program modules 521 include instructions for driving the above-mentioned SPAD detector 530 according to at least one embodiment of the present disclosure to perform light intensity measurement. When executed by the processor 510, the one or more computer program modules 521 can drive the SPAD detector 530 to perform the above-mentioned light intensity measurement step.

[0060] The memory 520 and the processor 510 may be interconnected via a bus system and / or other forms of connection mechanisms (not shown). For example, the bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industrial Standard Architecture (EISA) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc.

[0061] For example, the processor 510 may be a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), or other processing units with data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA). The processor 510 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 500 to perform desired functions.

[0062] Exemplarily, the memory 520 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules 521 may be stored on the computer-readable storage medium, and the processor 510 may execute the one or more computer program modules 521 to implement various functions of the electronic device 500. Various applications and various data, as well as various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0063] For example, the electronic device 500 may also include input devices such as a camera, a touch screen, a touchpad, a keyboard, a mouse, a webcam, a microphone, an accelerometer, a gyroscope, etc.; output devices such as a liquid crystal display, a speaker, a vibrator, etc.; storage devices such as a magnetic tape, a hard disk (HDD or SDD), etc.; and communication devices such as a network interface card such as a LAN card, a modem, etc. The communication device may allow the electronic device 500 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. A drive is connected to the I / O interface as needed. A removable storage medium, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive as needed so that a computer program read therefrom can be installed into the storage device as needed.

[0064] For example, the electronic device 500 may further include a peripheral interface (not shown in the figure). The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication may use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.5a, IEEE 802.5b, IEEE 802.5g, and / or IEEE 802.5n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or short message service (SMS), or any other suitable communication protocol.

[0065] The electronic device 500 may be, for example, a system on a chip (SOC) or a device including the SOC, such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigation system, home appliance, communication base station, industrial controller, server, or any other device. It may also be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited thereto. The specific functions and technical effects of the electronic device 500 can be referred to the above description of the SPAD detector according to at least one embodiment of the present disclosure, and will not be repeated here.

[0066] Figure 6 is an example method for manufacturing a SPAD detector according to at least one embodiment of the present disclosure.

[0067] In 601, a substrate may be prepared. The substrate includes a P-type substrate layer, an N-type buried layer, and a P-type epitaxial layer stacked in sequence.

[0068] In 602, P ions may be implanted into the substrate to form a P-type well. The P-type well may be disposed in a P-type epitaxial layer, wherein an upper surface of the P-type well may be lower than an upper surface of the P-type epitaxial layer, and a lower surface of the P-type well may contact an N-type buried layer, thereby forming a PN junction with the N-type buried layer.

[0069] In 603, N ions may be implanted into the substrate to form an N+ region. The N+ region may be disposed in the N-type buried layer. The N+ region may contact the N-type buried layer, with the lower surface of the N+ region below the upper surface of the N-type buried layer. The upper surface of the N+ region may be aligned with or above the upper surface of the N-type buried layer. The N+ region may surround the P-type well.

[0070] In 604 , P ions may be implanted into the substrate to form a P+ region. The P+ region may be disposed in the P-type epitaxial layer, with an upper surface of the P+ region aligned with an upper surface of the P-type epitaxial layer, and the P+ region may surround a P-type well.

[0071] Figure 7 FIG. 1 is a flow chart of an exemplary method for manufacturing another SPAD detector according to at least one embodiment of the present disclosure. It should be understood by those skilled in the art that Figure 7 The flowchart shown in the figure is only illustrative and can be executed in a disrupted order, in reverse order, or in parallel without departing from the main purpose of the present invention. Figure 7 The various steps of the method shown in , in addition, some steps may be added, omitted.

[0072] Figure 8 FIG. 4 is a schematic diagram of a fabrication process of a single-photon avalanche diode according to at least one embodiment of the present disclosure.

[0073] In 701, a substrate may be prepared, the substrate including a P-type substrate layer, an N-type buried layer, and a P-type epitaxial layer stacked in sequence. Figure 8 As shown in (1), a substrate 804 including a P-type substrate layer 801, an N-type buried layer 802, and a P-type epitaxial layer 803 stacked in sequence can be prepared. The substrate 804 can include an upper surface 804a and a lower surface 804b. The upper surface 804a can be the incident light surface.

[0074] In 702, P ion implantation may be performed on the substrate to form a P-type well. For example, P ion implantation may be performed using a mask to generate a P-type well 804 in the P-type epitaxial layer 803. Figure 8As shown in (2), the P-type well 804 is set in the P-type epitaxial layer 803, the upper surface of the P-type well 804 is lower than the upper surface of the P-type epitaxial layer 803, the lower surface of the P-type well 804 is in contact with the N-type buried layer 802, and the P-type well 804 and the N-type buried layer 802 form a PN junction.

[0075] In 703, a trench may be etched around the P-type well 804. Figure 8 As shown in (3), the depth of the etched trench 805 is required to be close to (eg, equal to) the depth of the upper surface of the N-type buried layer 802. That is, the trench 805 can surround the P-type well 804 and penetrate the P-type epitaxial layer 803.

[0076] In 704, N ions may be implanted into the substrate to form an N+ region. For example, a high concentration of N ions may be implanted using a mask to form an N+ region 806 in the N-type buried layer 802. Figure 8 As shown in (4), the N+ region 806 can be disposed in the N-type buried layer 802, the N+ region 806 can be in contact with the N-type buried layer, and the lower surface of the N+ region 806 can be below the upper surface of the N-type buried layer. The upper surface of the N+ region 806 can be aligned with the upper surface of the N-type buried layer 802 or above the upper surface of the N-type buried layer 802, and the N+ region 806 can surround the P-type well 804.

[0077] In 705, P ion implantation can be performed on the substrate to form a P+ region. For example, a high concentration of P ion implantation can be performed using a mask. Figure 8 As shown in (5), the P+ region 807 can be set in the P-type epitaxial layer 803, the upper surface of the P+ region 807 can be aligned with the upper surface 804a of the P-type epitaxial layer 803, and the P+ region 807 can surround the P-type well 804. Figure 8 As shown in (5), the N+ region 806 is farther away from the P-type well 804 than the P+ region 807 in the radial direction.

[0078] In 706, a dielectric as an isolation layer 808 may be deposited in the trench 805. For example, the isolation layer may be deposited in the trench 805 using a high-density plasma chemical vapor deposition method to avoid leaving voids during the deposition process. The deposited isolation layer is typically silicon oxide. After the trench 805 is filled, a grinding process is required to remove excess silicon oxide from the wafer surface and flatten the surface. Figure 8 As shown in (6), the trench 805 is filled with an isolation layer 808.

[0079] In 707, a transition layer and a dielectric layer may be deposited on the surface of the wafer. The dielectric layer is usually a combination of silicon nitride and silicon oxide. Figure 8As shown in (7), a transition layer 809 and a dielectric layer 810 are deposited on the surface of the wafer. The dielectric layer 810 can be arranged on the P-type epitaxial layer 803, and the transition layer 809 can be arranged between the dielectric layer 810 and the P-type epitaxial layer 803.

[0080] In 708, the isolation layer 808 in the trench 805 may be hole-etched. For example, the isolation layer 808 in the trench 805, which is a dielectric such as silicon dioxide, and the transition layer and dielectric layer on the wafer surface may be hole-etched using an etching process. Figure 8 As shown in (8), for the region with the trench 805 (for example, above the N+ region 806), etching will proceed to the depth of the bottom of the trench 805 close to the N-type buried layer 802 (for example, the depth is equal to the upper surface of the N-type buried layer 802), and a portion of the isolation layer 808 is still retained between the etched hole 811 and the sidewall of the trench 805 to isolate the etched hole 811 from the sidewall of the trench 805. In one embodiment, for the region with the trench 805, the isolation layer 808 can be etched to the N-type buried layer only at the location where the electrode is expected to be filled, and the isolation layer 808 is not etched in other trench regions where the electrode is not expected to be filled. In another embodiment, for the region with the trench 805, the isolation layer 808 above the N+ region (including the region where the electrode is expected to be filled and the region where the electrode is not expected to be filled) can be etched to the N-type buried layer, and a circle of metal grooves can be formed in the entire etched region. The metal grooves can further reduce the crosstalk between adjacent SPAD detectors. For areas without trenches 805 (e.g., above P+ region 807), etching will proceed to a depth close to the P-type epitaxial layer 803 (e.g., a depth equal to the top surface 804a of the P-type epitaxial layer 803). In one embodiment, for areas without trenches 805, the transition layer 809 and dielectric layer 810 can be etched down to the P-type epitaxial layer 803 only at locations where electrodes are expected to be placed, while the transition layer 809 and dielectric layer 810 are not etched at other locations where electrodes are not expected to be placed. In another embodiment, for areas without trenches 805, the transition layer 809 and dielectric layer 810 above the P+ region (including both areas where electrodes are expected to be placed and areas where electrodes are not expected to be placed) can be etched down to the P-type epitaxial layer 803, forming a metal groove around the entire etched area. This metal groove can further reduce crosstalk between adjacent SPAD detectors. In other words, the isolation layer 808, which serves as a dielectric within the trench 805, can be etched to form a space to accommodate the positive electrode connected to the N+ region 806. The transition layer 809 and the dielectric layer 810 above the P+ region may be etched to form a space for accommodating the negative electrode connected to the P+ region 807 .

[0081] In 709, the etched hole may be filled with metal material to form an electrode 812. For example, tungsten metal may be filled in the etched hole 811 to form an electrode. Figure 8 As shown in (9), for the etched hole 811 in the trench 805, the isolation layer 808 retained on the sidewall of the trench 805 isolates the tungsten metal and the P-type epitaxial layer 803. The electrode 812 can contact the N+ region 806 and the P+ region 807 respectively, thereby forming an ohmic contact.

[0082] In one embodiment, after a trench is etched around the P-type well 804 in 703, P ions with a higher concentration and shallower depth than the P-type well 804 can be implanted into the substrate 804 to form a P-rich region ( Figure 8 For a detailed description of the P-rich region, please refer to Figure 4 .

[0083] In one embodiment, a light-trapping structure can also be formed on the upper surface 804a of the substrate 804. For example, an inverted trapezoidal or inverted pyramidal light-trapping groove can be formed on the upper surface 804a of the substrate 804 through an etching process. The light-trapping structure can be achieved by filling the light-trapping groove with silicon dioxide. Reflection at the silicon-silicon dioxide interface within the light-trapping structure increases the optical path length of light within the SPAD detector, thereby improving light absorption efficiency.

[0084] The present invention optimizes the structure of the SPAD detector, fabricates the multiplication zone at a depth far away from the substrate surface, and reduces dark counts caused by surface defects. The photon detection efficiency (PDE) is improved by means of light trapping structures, and the anode and cathode are designed in the substrate (such as on the N-type buried layer) and on the incident light surface of the substrate, respectively, so that the two electrodes maintain a long distance in the vertical direction, thereby avoiding the premature breakdown effect. Since the incident light surface does not require a guard ring structure, the fill factor of small-sized SPADs is effectively improved. The technical solution of the present invention can be directly applied to the front-illuminated process. The front-illuminated process is more stable than the 3D stacking process, has lower difficulty, higher production yield, and lower cost investment.

[0085] The text and drawings in this disclosure are provided as examples only to help understand the present disclosure. They should not be interpreted as limiting the scope of the present disclosure in any way. Although certain embodiments and examples have been provided, it will be clear to those skilled in the art based on what is disclosed herein that the embodiments and examples shown may be modified without departing from the scope of the present disclosure.

[0086] Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.

[0087] Nothing in this disclosure should be construed as implying that any particular element, step, or function is an essential element that must be included in the claims scope. The scope of the patented subject matter is defined solely by the claims.

Claims

1. A single-photon avalanche photodiode, characterized in that: include: P-type substrate layer, The N-type buried layer is arranged on the P-type substrate layer. The P-type epitaxial layer is placed on the N-type buried layer. A P-type well is provided in the P-type epitaxial layer, wherein the upper surface of the P-type well is lower than the upper surface of the P-type epitaxial layer, the lower surface of the P-type well contacts the N-type buried layer, and the P-type well and the N-type buried layer form a PN junction. A P+ region is provided in the P-type epitaxial layer, wherein the lower surface of the P+ region is higher than the upper surface of the N-type buried layer, and the P+ region surrounds the P-type well. The N+ region contacts the N-type buried layer, a lower surface of the N+ region is below an upper surface of the N-type buried layer, and the N+ region surrounds the P-type well.

2. The single-photon avalanche photodiode according to claim 1, characterized in that The upper surface of the P+ region is aligned with the upper surface of the P-type epitaxial layer.

3. The single-photon avalanche photodiode according to claim 1, wherein: A multiplication region is formed between the P-type well and the N-type buried layer.

4. The single-photon avalanche photodiode according to claim 1, wherein: The N+ region is farther away from the P-type well than the P+ region in the radial direction.

5. The single-photon avalanche photodiode according to claim 1, wherein: A negative electrode and a positive electrode are also included, wherein the P+ region is connected to the negative electrode, and the N+ region is connected to the positive electrode.

6. The single-photon avalanche photodiode according to claim 1, wherein: It also includes a dielectric layer and a transition layer, wherein the dielectric layer is arranged on the P-type epitaxial layer, and the transition layer is arranged between the dielectric layer and the P-type epitaxial layer.

7. The single-photon avalanche photodiode according to claim 1, wherein: The invention also includes a trench, which surrounds the P-type well and penetrates the P-type epitaxial layer.

8. The single-photon avalanche photodiode according to claim 7, characterized in that: The trench is disposed above the N+ region, and the N+ region is connected to a positive electrode disposed in the trench.

9. The single-photon avalanche photodiode according to claim 8, characterized in that: The trench is filled with a dielectric, which isolates the positive electrode from the P-type extension layer.

10. The single-photon avalanche photodiode according to claim 9, characterized in that: The dielectric includes silicon dioxide.

11. The single-photon avalanche photodiode according to claim 1, wherein: The invention also includes a light trapping structure, which is arranged in the P-type epitaxial layer and has an upper surface aligned with an upper surface of the P-type epitaxial layer.

12. The single-photon avalanche photodiode according to claim 11, wherein: The light trapping structure includes silicon dioxide.

13. The single-photon avalanche photodiode according to claim 7, wherein: It also includes a P-rich region, which is arranged in the P-type epitaxial layer and between the trench and the P-type well. The doping concentration of the P-rich region is higher than the doping concentration of the P-type well.

14. The single-photon avalanche photodiode according to claim 7, characterized in that: An upper surface of the P-rich region is lower than an upper surface of the P-type epitaxial layer, and a lower surface of the P-rich region is higher than a lower surface of the P-type epitaxial layer.

15. The single-photon avalanche photodiode according to claim 1, wherein: The thickness of the P-type epitaxial layer is 3 microns.

16. The single-photon avalanche photodiode according to claim 1, wherein: The upper surface of the N+ region is aligned with the upper surface of the N-type buried layer or is above the upper surface of the N-type buried layer.

17. An electronic device, characterized in that: The method comprises the single-photon avalanche photodiode according to any one of claims 1 to 16.

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