Multi-channel power supply time sequence control device and testing machine

Abstract

The utility model relates to a multipath power supply time sequence control device and a test machine, a power supply control module in the multipath power supply time sequence control device comprises a time sequence controller and a peripheral circuit, and after the time sequence controller receives a control signal accessed by a control end, the time sequence controller determines a delay parameter according to an element in the peripheral circuit. And sequentially electrifying / de-electrifying the multiple paths of power supplies. Elements in a peripheral circuit can be arranged according to actual needs, the power-on / power-off time sequence of multiple power sources is adjusted, and the power source time sequence control convenience is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a multi-channel power supply timing control device and a testing machine. Background Art

[0002] In the resource board of the test machine, different power supplies are used to power each controller separately, requiring power-on and power-off management of multiple controllers. The traditional method of controlling the timing of multiple power supplies is to control them through the enable pin and PG (POWER GOOD) pin of the power supply chip. Specifically, the enable signal of the first power supply is connected to the power supply, and the enable pin of the second power supply is connected to the PG (POWER GOOD) pin of the first power supply. Similarly, the upper power supply pushes the lower power supply to achieve the power-on timing of multiple power supplies. This method cannot control the power-on time interval of the two power supplies, and the control of the power supply timing is limited, which has the disadvantage of low convenience of power supply timing control. Utility Model Content

[0003] Based on this, it is necessary to provide a multi-channel power supply timing control device and a tester that can improve the convenience of power supply timing control to address the above problems.

[0004] The first aspect of the present application provides a multi-power supply timing control device, including a power supply control module, the power supply control module including a timing controller and a peripheral circuit, the timing controller being connected to a control end, the peripheral circuit and multiple power supplies; after receiving a control signal input from the control end, the timing controller sequentially powers on / off the multiple power supplies according to delay parameters determined by components in the peripheral circuit.

[0005] In one embodiment, the timing controller is an ADM1186-2 chip; the peripheral circuit includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, the UP / DOWN pin of the timing controller receives the control signal, the DLY_EN_OUT2 pin of the timing controller is grounded through the first capacitor, the DLY_EN_OUT3 pin of the timing controller is grounded through the second capacitor, the DLY_EN_OUT4 pin of the timing controller is grounded through the third capacitor, and the BLANK_DLY pin of the timing controller is grounded through the fourth capacitor; the OUT1 pin, OUT2 pin, OUT3 pin and OUT4 pin of the timing controller are respectively connected to corresponding power supplies.

[0006] In one embodiment, the peripheral circuit further includes a first resistor, a second resistor, a third resistor and a fourth resistor, the OUT1 pin of the timing controller is connected to the power supply end through the first resistor, the OUT2 pin of the timing controller is connected to the power supply end through the second resistor, the OUT3 pin of the timing controller is connected to the power supply end through the third resistor, and the OUT4 pin of the timing controller is connected to the power supply end through the fourth resistor.

[0007] In one embodiment, the multi-power supply timing control device further includes a logic gate circuit, the number of the power supply control modules is more than two, the logic gate circuit is connected to the control end and each of the power supply control modules, and each of the power supply control modules is connected to the corresponding multi-power supply; the logic gate circuit transmits the control signal input by the control end to each of the power supply control modules, and controls each of the power supply control modules to sequentially power on / off the multi-power supply.

[0008] In one embodiment, the logic gate circuit includes logic gate units, the number of the logic gate units corresponds to the number of the power control modules, each of the logic gate units is connected to the control end, and each of the logic gate units is connected to the corresponding power control module so that each of the power control modules is connected in series in a power-on / power-off sequence.

[0009] In one embodiment, the logic gate unit corresponding to the power control module located at the head end includes an OR gate, the first input end of the OR gate is connected to the control signal, the output end of the OR gate is connected to the UP / DOWN pin of the timing controller in the power control module located at the head end, and the second input end of the OR gate is connected to the OUT1 pin of the timing controller in the next power control module; the logic gate unit corresponding to the power control module located at the tail end includes an AND gate, the first input end of the AND gate is connected to the OUT4 pin of the timing controller in the previous power control module, the second input end of the AND gate is connected to the control signal, and the output end of the AND gate is connected to the UP / DOWN pin of the timing controller in the power control module located at the tail end.

[0010] In one embodiment, the logic gate unit corresponding to the power control module located between the head end and the tail end includes an OR gate and an AND gate, the first input end of the AND gate is connected to the OUT4 pin of the timing controller in the previous power control module, the second input end of the AND gate is connected to the control signal, the output end of the AND gate is connected to the first input end of the OR gate, the second input end of the OR gate is connected to the OUT1 pin of the timing controller in the next power control module, and the output end of the OR gate is connected to the UP / DOWN pin of the timing controller in the corresponding power control module.

[0011] In one embodiment, the multi-channel power supply timing control device further includes a regulating module, which is connected to the control end and outputs the control signal to the control end.

[0012] In one embodiment, the regulating module includes a voltage dividing component and a dip switch, the voltage dividing component is connected to the power supply end and the dip switch, and the dip switch is connected to the control end.

[0013] A second aspect of the present application provides a testing machine, comprising the above-mentioned multi-channel power supply timing control device.

[0014] The power control module in the aforementioned multi-power supply timing control device and tester includes a timing controller and peripheral circuits. After receiving a control signal from a control terminal, the timing controller sequentially powers on and off the multiple power supplies based on delay parameters determined by components in the peripheral circuits. The components in the peripheral circuits can be configured as needed to adjust the timing of powering on and off the multiple power supplies, thereby enhancing the convenience of power supply timing control. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a structural block diagram of a multi-channel power supply timing control device in one embodiment;

[0016] Figure 2 A schematic diagram of the structure of an adjustment module in one embodiment;

[0017] Figure 3 is a structural schematic diagram of a power control module in one embodiment;

[0018] Figure 4 A schematic diagram of the structure of the ADM1186-2 chip in one embodiment;

[0019] Figure 5 is a schematic structural diagram of a power control module and a logic gate circuit in one embodiment;

[0020] Figure 6 A schematic structural diagram of a power control module and a logic gate circuit in another embodiment;

[0021] Figure 7 FIG. 4 is a schematic structural diagram of a power control module and a logic gate circuit in yet another embodiment. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0024] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0025] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, operations, components, parts, or combinations thereof.

[0026] In one embodiment, Figure 1 As shown, a multi-channel power supply timing control device is provided, including a power supply control module 120, the power supply control module 120 includes a timing controller 122 and a peripheral circuit 124, the timing controller 122 is connected to the control end, the peripheral circuit 124 and the multi-channel power supply; after receiving the control signal input by the control end, the timing controller 122 sequentially powers on / off the multi-channel power supply according to the delay parameters determined by the components in the peripheral circuit 124.

[0027] Among them, the elements in the peripheral circuit 124 may include resistors, capacitors, etc., and the delay parameters can be determined by setting the capacitance value of the relevant capacitor in the peripheral circuit 124, changing the time interval for the timing controller 122 to power on / off the multiple power supplies, thereby realizing power supply timing control. The timing controller 122 can sequentially power on the multiple power supplies when the rising edge of the control signal is detected, and sequentially power off the multiple power supplies when the falling edge of the control signal is detected. The order in which the timing controller 122 powers on / off the multiple power supplies is not unique. It can be to output a high level to the corresponding power supply in order from small to large in pin number, and power on the power supplies in sequence, and output a low level to the corresponding power supply in order from large to small in pin number, and power off the power supplies in sequence.

[0028] In addition, the multi-channel power supply timing control device may further include an adjustment module 110, which is connected to the control terminal and outputs a control signal to the control terminal, and can control the power on or off of the multi-channel power supply. Figure 2 As shown, the regulating module 110 includes a voltage dividing component 112 and a dial switch K1. The voltage dividing component 112 is connected to the power supply terminal VPRE And the code switch K1, the code switch K1 is connected to the control terminal. The voltage divider component 112 divides the power supply terminal V PRE The connected power supply is divided and then used to power the DIP switch K1. By adjusting the state of the DIP switch K1, a high level / low level is sent to the timing controller 122 in the power control module 120, thereby controlling the power on or off of multiple power supplies. Among them, the voltage divider component 112 may specifically include a resistor RA and a resistor RB. The resistors RA and RB are connected in series and the common end is connected to the DIP switch K1. The other end of the resistor RA is connected to the power supply terminal V PRE , the other end of resistor RB is grounded.

[0029] The specific type of the timing controller 122 is not unique. In this embodiment, the timing controller 122 is an ADM1186-2 chip. The number of timing controllers 122 is also not unique, and may include timing controller U1, timing controller U2, etc. Each timing controller 122 is correspondingly provided with a peripheral circuit 124 to form a corresponding power control module 120. Figure 3 As shown, the peripheral circuit 124 may include a first capacitor C2, a second capacitor C3, a third capacitor C4 and a fourth capacitor C5. The UP / DOWN pin of the timing controller U1 receives a control signal, the DLY_EN_OUT2 pin of the timing controller U1 is grounded through the first capacitor C2, the DLY_EN_OUT3 pin of the timing controller U1 is grounded through the second capacitor C3, the DLY_EN_OUT4 pin of the timing controller U1 is grounded through the third capacitor C4, and the BLANK_DLY pin of the timing controller U1 is grounded through the fourth capacitor C5; the OUT1 pin, OUT2 pin, OUT3 pin and OUT4 pin of the timing controller U1 are respectively connected to the corresponding power supply, output signal S1, signal S2, signal S3, signal S4, and power on / off the corresponding power supply. In addition, the VCC pin of the timing controller U1 is connected to the power supply terminal V pre .

[0030] Figure 4The figure shows the internal structure schematic of the ADM1186-2 chip, which can implement four-way power supply timing control. By pulling the control signal high, the OUT1 to OUT4 pins of the timing controller U1 are sequentially pulled high, thus achieving timing control of the four power supplies. Specifically, when the control signal is pulled high, the UP / DOWN pin of the timing controller U1 detects a rising edge and immediately pulls the OUT1 pin high. After the OUT1 pin is pulled high, the timing controller U1 charges the capacitors on the BLANK_DLY and DLY_EN_OUT2 pins to achieve a delay. When the delay time is reached, the OUT2 pin is pushed high, and so on, delaying the push-up of the OUT3 pin, and so on, ultimately achieving the sequential pull-up of the OUT1 to OUT4 pins. When the control signal is pulled low, the UP / DOWN pin of timing controller U1 detects the falling edge and immediately pulls OUT4 low. The chip then internally delays charging the DLY_EN_OUT4 pin. When the delay is reached, OUT3 is pulled low, and so on, with a delay before OUT2 is pulled low, and so on, until OUT4 and OUT1 are pulled low in sequence. The power-up and power-down delays between the power supplies are related to the capacitance of the grounded capacitors connected to the DLY_EN_OUT and BLANK_DLY pins of timing controller U1.

[0031] Further, continue to refer to Figure 3 The peripheral circuit 124 further includes a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The OUT1 pin of the timing controller U1 is connected to the power supply terminal V through the first resistor R1. pre , the OUT2 pin of the timing controller U1 is connected to the power supply terminal V through the second resistor R2 pre , the OUT3 pin of the timing controller U1 is connected to the power supply terminal V through the third resistor R3 pre , the OUT4 pin of the timing controller U1 is connected to the power supply terminal V through the fourth resistor R4 pre The first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 can be selected as large resistors and connected to the power supply terminal V as pull-up resistors. pre , a weak pull-up method is adopted to ensure that the OUT1 pin to the OUT4 pin can output a high level normally.

[0032] When power-up / down sequence control is required for more power supplies, the number of power control modules can be further expanded to meet actual needs. In one embodiment, the multi-power supply sequence control device further includes a logic gate circuit, the number of power control modules 120 being two or more, the logic gate circuit connecting the control terminal and each power control module 120, and each power control module 120 being connected to a corresponding multi-power supply; the logic gate circuit transmits the control signal received from the control terminal to each power control module 120, controlling each power control module 120 to sequentially power on / off the multiple power supplies.

[0033] It is understandable that the specific structure of the logic gate circuit will be different depending on the number of power control modules 120. Figures 5 to 7 As shown, the logic gate circuit 130 includes logic gate units 132, the number of logic gate units 132 corresponds to the number of power control modules 120, each logic gate unit 132 is connected to the control end, and each logic gate unit 132 is connected to the corresponding power control module 120 to connect each power control module 120 in series according to the power-on / power-off sequence.

[0034] Among them, the logic gate unit 132 corresponding to the power control module 120 at the head end includes an OR gate, the first input end of the OR gate is connected to the control signal, the output end of the OR gate is connected to the UP / DOWN pin of the timing controller in the power control module 120 at the head end, and the second input end of the OR gate is connected to the OUT1 pin of the timing controller in the next power control module 120; the logic gate unit 132 corresponding to the power control module 120 at the tail end includes an AND gate, the first input end of the AND gate is connected to the OUT4 pin of the timing controller in the previous power control module 120, the second input end of the AND gate is connected to the control signal, and the output end of the AND gate is connected to the UP / DOWN pin of the timing controller in the power control module 120 at the tail end.

[0035] Furthermore, the logic gate unit 132 corresponding to the power control module 120 located between the head end and the tail end includes an OR gate and an AND gate, the first input end of the AND gate is connected to the OUT4 pin of the timing controller in the previous power control module 120, the second input end of the AND gate is connected to the control signal, the output end of the AND gate is connected to the first input end of the OR gate, the second input end of the OR gate is connected to the OUT1 pin of the timing controller in the next power control module 120, and the output end of the OR gate is connected to the UP / DOWN pin of the timing controller in the corresponding power control module 120.

[0036] The following is an explanation with reference to several specific embodiments.

[0037] In one embodiment, Figure 5As shown, there are two power control modules 120, and the logic gate circuit 130 includes an OR gate A1 and an AND gate B1. Of the two power control modules 120, the first power control module 120 includes a timing controller U1, a first capacitor C2, a second capacitor C3, a third capacitor C4, a fourth capacitor C5, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The timing controller U1 outputs signals S1, S2, S3, and S4. The second power control module 120 includes a timing controller U2, a first capacitor C6, a second capacitor C7, a third capacitor C8, a fourth capacitor C9, a first resistor R5, a second resistor R6, a third resistor R7, and a fourth resistor R8. The timing controller U2 outputs signals S5, S6, S7, and S8. The internal connections of the two power control modules 120 are similar and will not be repeated here.

[0038] Among them, the first input end of the OR gate A1 is connected to the control signal, the output end of the OR gate A1 is connected to the UP / DOWN pin of the timing controller U1 in the first power control module 120, the second input end of the OR gate A1 is connected to the OUT1 pin of the timing controller U2 in the second power control module 120, the first input end of the AND gate B1 is connected to the OUT4 pin of the timing controller U1 in the first power control module 120, the second input end of the AND gate B1 is connected to the control signal, and the output end of the AND gate B1 is connected to the UP / DOWN pin of the timing controller U2 in the second power control module 120.

[0039] In this embodiment, two ADM1186-2 chips and logic gates are used to build a timing control circuit for eight power supplies. OR gate A1 is connected to the UP / DOWN pins of timing controller U1. OR gate A1's two inputs receive the control signal and the first output signal of timing controller U2, respectively. This connection ensures power-off timing. When the control signal is pulled high, OR gate A1 triggers a rising edge input to timing controller U1, allowing it to output the required power-on timing. During power-off, OR gate A1 triggers a falling edge on the power-on control pin of timing controller U1, prompting timing controller U1 to power down sequentially, only when the control signal and the first output signal of timing controller U2 are simultaneously pulled low. This ensures a consistent power-off sequence.

[0040] The UP / DOWN pins of timing controller U2 are connected via AND gate B1. The two inputs of AND gate B1 are connected to the control signal and the last output signal of timing controller U1, respectively. This connection ensures a consistent power-up sequence. Only when the control signal and the last output of timing controller U1 are simultaneously pulled high will the power-up control pin of timing controller U2 receive a rising edge, which will then drive the outputs of timing controller U2 to the output sequence, ensuring that the output timing of timing controller U2 is output after the last output of timing controller U1. During power-down, due to AND gate B1, when the control signal is pulled low, a falling edge is applied to the power-up control pin of timing controller U2, which in turn drives timing controller U2 to power down sequentially.

[0041] In one embodiment, Figure 6 As shown, there are three power control modules 120, and the logic gate circuit 130 includes an OR gate A1, an OR gate A2, an AND gate B1, and an AND gate B2. Among the three power control modules 120, the newly added third power control module 120 includes a timing controller U3, a first capacitor C10, a second capacitor C11, a third capacitor C12, a fourth capacitor C13, a first resistor R9, a second resistor R10, a third resistor R11, and a fourth resistor R12. The timing controller U3 outputs signals S9, S10, S11, and S12.

[0042] Among them, the first input end of the OR gate A1 is connected to the control signal, the output end of the OR gate A1 is connected to the UP / DOWN pin of the timing controller U1 in the first power control module 120, the second input end of the OR gate A1 is connected to the OUT1 pin of the timing controller U2 in the second power control module 120, the first input end of the AND gate B1 is connected to the OUT4 pin of the timing controller U1 in the first power control module 120, the second input end of the AND gate B1 is connected to the control signal, the output end of the AND gate B1 is connected to the first input end of the OR gate A2, the second input end of the OR gate A2 is connected to the OUT1 pin of the timing controller U3 in the third power control module 120, the output end of the OR gate A2 is connected to the UP / DOWN pin of the timing controller U2 in the second power control module 120, the first input end of the AND gate B2 is connected to the OUT4 pin of the timing controller U2 in the second power control module 120, the second input end of the AND gate B2 is connected to the control signal, and the output end of the AND gate B2 is connected to the UP / DOWN pin of the timing controller U3 in the third power control module 120.

[0043] Take, for example, the power sequencing circuit built with three ADM1186-2 chips and logic gates. The UP / DOWN pins of sequencer U1 are connected via OR gate A1. OR gate A1's two inputs receive the control signal and the first output signal of sequencer U2, respectively. This connection ensures power-off sequencing. When the control signal is high, OR gate A1 triggers a rising edge on sequencer U1's input, allowing it to output the desired power-up sequence. During power-off, OR gate A1 prevents the power-on control pin of sequencer U1 from receiving a falling edge, triggering a sequential power-down of sequencer U1, only when the control signal and the first output signal of sequencer U2 are simultaneously low. This ensures a consistent power-down sequence.

[0044] The UP / DOWN pins of timing controller U2 are connected using an OR gate A2 and an AND gate B1. The two inputs of AND gate B1 are connected to the control signal and the last output of timing controller U1, respectively. This ensures that AND gate B1 outputs high only after the control signal and all outputs of timing controller U1 are pulled high, ensuring that timing controller U2 powers up after timing controller U1. OR gate A2's function is to control the power-down sequence. During power-down, due to the low control signal, AND gate B1 outputs low. Only after the output of signal S9 of timing controller U3 is pulled low will the power-up control pin of timing controller U2 receive a falling edge, allowing the power-down operation to proceed, thus ensuring the power-down sequence.

[0045] The UP / DOWN pins of timing controller U3 are connected via AND gate B2. The two inputs of AND gate B2 are connected to the control signal and the last output signal of timing controller U2, respectively. This connection ensures a consistent power-up sequence. Only when the control signal and the last output of timing controller U2 are simultaneously pulled high will the UP / DOWN pins of timing controller U3 receive a rising edge, which in turn will cause the outputs of timing controller U3 to be output sequentially. This ensures that the output timing of timing controller U3 is output after the last output of timing controller U2. During power-down, due to AND gate B2, when the control signal is pulled low, a falling edge is applied to the power-up control pin of timing controller U3, causing timing controller U3 to power down sequentially.

[0046] In one embodiment, Figure 7As shown, there are four power control modules 120, and the logic gate circuit 130 includes OR gates A1, A2, and A3, AND gates B1, B2, and B3. The newly added fourth power control module 120 includes a timing controller U4, a first capacitor C14, a second capacitor C15, a third capacitor C16, a fourth capacitor C17, a first resistor R13, a second resistor R14, a third resistor R15, and a fourth resistor R16. The timing controller U7 outputs signals S13, S14, S15, and S16.

[0047] Among them, the first input end of the OR gate A1 is connected to the control signal, the output end of the OR gate A1 is connected to the UP / DOWN pin of the timing controller U1 in the first power control module 120, the second input end of the OR gate A1 is connected to the OUT1 pin of the timing controller U2 in the second power control module 120, the first input end of the AND gate B1 is connected to the OUT4 pin of the timing controller U1 in the first power control module 120, the second input end of the AND gate B1 is connected to the control signal, the output end of the AND gate B1 is connected to the first input end of the OR gate A2, the second input end of the OR gate A2 is connected to the OUT1 pin of the timing controller U3 in the third power control module 120, and the output end of the OR gate A2 is connected to the UP / DOWN pin of the timing controller U2 in the second power control module 120. Pin, the first input end of the AND gate B2 is connected to the OUT4 pin of the timing controller in the second power control module U2, the second input end of the AND gate B2 is connected to the control signal, the output end of the AND gate B2 is connected to the first input end of the OR gate A3, the second input end of the OR gate A3 is connected to the OUT1 pin of the timing controller U4 in the fourth power control module 120, and the output end of the OR gate A3 is connected to the UP / DOWN pin of the timing controller U3 in the third power control module 120; the first input end of the AND gate B3 is connected to the OUT4 pin of the timing controller U3 in the third power control module 120, the second input end of the AND gate B3 is connected to the control signal, and the output end of the AND gate B3 is connected to the UP / DOWN pin of the timing controller U4 in the fourth power control module 120.

[0048] Take, for example, the power sequencing circuit built with four ADM1186-2 chips and logic gates. The UP / DOWN pins of sequencer U1 are connected via OR gate A1. OR gate A1's two inputs receive the control signal and the first output signal of sequencer U2, respectively. This connection ensures power-off sequencing. When the control signal is high, OR gate A1 triggers a rising edge on sequencer U1's input, allowing it to output the desired power-up sequence. During power-off, OR gate A1 prevents the power-on control pin of sequencer U1 from receiving a falling edge, triggering a sequential power-down of sequencer U1, only when the control signal and the first output signal of sequencer U2 are simultaneously low. This ensures a consistent power-down sequence.

[0049] The UP / DOWN pins of timing controller U2 are connected using an OR gate A2 and an AND gate B1. The two inputs of AND gate B1 are connected to the control signal and the last output of timing controller U1, respectively. This ensures that AND gate B1 outputs high only after the control signal and all outputs of timing controller U1 are pulled high, ensuring that timing controller U2 powers up after timing controller U1. OR gate A2's role is reflected in power-down sequence control. During power-down, due to the low control signal, AND gate B1 outputs low. Only after the output of signal S9 of timing controller U3 is pulled low will the power-up control pin of timing controller U2 receive a falling edge, and power-down will occur, thus ensuring the power-down sequence.

[0050] The UP / DOWN pins of timing controller U3 are connected using an OR gate A3 and an AND gate B2 (similar to timing controller U2). The two inputs of AND gate B2 are connected to the control signal and the last output of timing controller U2, respectively. This ensures that the AND gate B2 output will not be high until the control signal and all outputs of timing controller U2 are pulled high, ensuring that timing controller U3 is powered on after timing controller U2. The role of OR gate A3 is reflected in the power-off sequence control. When powering off, due to the low control signal, the output of AND gate B2 is low. Only after the output of signal S13 of timing controller U4 is pulled low will the power-on control pin of timing controller U3 receive a falling edge and the power-off operation will be performed, thus ensuring the power-off sequence.

[0051] The UP / DOWN pins of timing controller U4 are connected via AND gate B3. The two inputs of AND gate B3 are connected to the control signal and the last output signal of timing controller U3, respectively. This connection ensures a consistent power-up sequence. Only when the control signal and the last output of timing controller U3 are simultaneously pulled high will the UP / DOWN pins of timing controller U4 receive a rising edge, which in turn will cause the outputs of timing controller U4 to be sequentially output. This ensures that the outputs of timing controller U4 are output after the last output of timing controller U3. During power-down, due to AND gate B3, when the control signal is pulled low, a falling edge is applied to the power-up control pin of timing controller U4, causing the timing controller U4 to power down sequentially.

[0052] It is understood that if there are more than 16 power supplies that need to be sequenced, Figure 7 On the basis of the present invention, an AND gate, an OR gate and a power control module 120 are further added to meet the actual multi-channel power supply timing control requirements.

[0053] In one embodiment, a test machine is further provided, comprising the above-mentioned multi-channel power supply timing control device.

[0054] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A multi-channel power supply timing control device, characterized in that: The power supply control module includes a timing controller and a peripheral circuit. The timing controller is connected to a control terminal, the peripheral circuit and multiple power supplies. After receiving a control signal input from the control terminal, the timing controller sequentially powers on / off the multiple power supplies according to delay parameters determined by components in the peripheral circuit.

2. The device according to claim 1, characterized in that The timing controller is an ADM1186-2 chip; the peripheral circuit includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, the UP / DOWN pin of the timing controller receives the control signal, the DLY_EN_OUT2 pin of the timing controller is grounded through the first capacitor, the DLY_EN_OUT3 pin of the timing controller is grounded through the second capacitor, the DLY_EN_OUT4 pin of the timing controller is grounded through the third capacitor, and the BLANK_DLY pin of the timing controller is grounded through the fourth capacitor; the OUT1 pin, OUT2 pin, OUT3 pin and OUT4 pin of the timing controller are respectively connected to corresponding power supplies.

3. The device according to claim 2, characterized in that The peripheral circuit also includes a first resistor, a second resistor, a third resistor and a fourth resistor. The OUT1 pin of the timing controller is connected to the power supply end through the first resistor, the OUT2 pin of the timing controller is connected to the power supply end through the second resistor, the OUT3 pin of the timing controller is connected to the power supply end through the third resistor, and the OUT4 pin of the timing controller is connected to the power supply end through the fourth resistor.

4. The device according to claim 1, characterized in that It also includes a logic gate circuit, the number of the power control modules is more than two, the logic gate circuit is connected to the control end and each of the power control modules, and each of the power control modules is connected to a corresponding multi-way power supply; the logic gate circuit transmits the control signal connected to the control end to each of the power control modules, and controls each of the power control modules to sequentially power on / off the multi-way power supply.

5. The device according to claim 4, characterized in that The logic gate circuit includes logic gate units, the number of which corresponds to the number of the power control modules. Each logic gate unit is connected to the control end, and each logic gate unit is connected to the corresponding power control module so that each power control module is connected in series in a power-on / power-off sequence.

6. The device according to claim 5, characterized in that The logic gate unit corresponding to the power control module at the head end includes an OR gate, wherein the first input end of the OR gate is connected to the control signal, the output end of the OR gate is connected to the UP / DOWN pin of the timing controller in the power control module at the head end, and the second input end of the OR gate is connected to the OUT1 pin of the timing controller in the next power control module; The logic gate unit corresponding to the power control module at the tail end includes an AND gate, the first input end of the AND gate is connected to the OUT4 pin of the timing controller in the previous power control module, the second input end of the AND gate is connected to the control signal, and the output end of the AND gate is connected to the UP / DOWN pin of the timing controller in the power control module at the tail end.

7. The device according to claim 5, characterized in that The logic gate unit corresponding to the power control module located between the head end and the tail end includes an OR gate and an AND gate. The first input end of the AND gate is connected to the OUT4 pin of the timing controller in the previous power control module, the second input end of the AND gate is connected to the control signal, the output end of the AND gate is connected to the first input end of the OR gate, the second input end of the OR gate is connected to the OUT1 pin of the timing controller in the next power control module, and the output end of the OR gate is connected to the UP / DOWN pin of the timing controller in the corresponding power control module.

8. The device according to any one of claims 1 to 7, characterized in that: It also includes a regulating module, which is connected to the control end and outputs the control signal to the control end.

9. The device according to claim 8, characterized in that The regulating module includes a voltage dividing component and a dial switch, the voltage dividing component is connected to the power supply end and the dial switch, and the dial switch is connected to the control end.

10. A testing machine, characterized in that: The device comprises a multi-channel power supply timing control device as described in any one of claims 1 to 9.

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