Bipolar constant-voltage current-limiting and constant-current voltage-limiting control circuit

Abstract

The utility model discloses a bipolar constant-voltage current-limiting, constant-current voltage-limiting control circuit, which comprises a first setting terminal, a second setting terminal and a third setting terminal, the first setting terminal is connected in series with a first operational amplifier unit through a resistor R1, the second setting terminal is connected in series with a second operational amplifier unit through a resistor R3, and the third setting terminal is connected in series with a second operational amplifier unit through a resistor R3. And the third setting terminal is connected in series with the third operational amplifier unit through a resistor R5. The bipolar constant-voltage current-limiting and constant-current voltage-limiting control circuit has the function of limiting the magnitude of output or well-in current in a constant-voltage mode and also has the function of limiting the upper and lower limits of open-circuit voltage in a constant-current mode, the well-in current function of the bipolar constant-voltage current-limiting and constant-current voltage-limiting control circuit can enable the bipolar constant-voltage current-limiting and constant-current voltage-limiting control circuit to serve as an active load to be used for measuring the loading capacity of a power supply type chip, the application is wide, and the reliability is high. The practicability is high.

Description

Technical Field

[0001] The utility model relates to a circuit, more precisely, to a bipolar constant voltage and current limiting and constant current and voltage limiting control circuit. Background Art

[0002] During semiconductor testing, it is necessary to limit the maximum current that the test equipment can provide in voltage mode and the maximum open-circuit voltage in current mode to prevent damage to the product under test in the event of an abnormality. However, existing test circuits rarely have both constant voltage current limiting and constant current voltage limiting control functions. Utility Model Content

[0003] Based on this, it is necessary to provide a bipolar constant voltage and current limiting, constant current and voltage limiting control circuit to address the above technical problems.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0005] A bipolar constant voltage current limiting, constant current voltage limiting control circuit, characterized in that the bipolar constant voltage current limiting, constant current voltage limiting control circuit comprises a first setting terminal, a second setting terminal and a third setting terminal,

[0006] The first setting terminal is connected in series with the first operational amplifier unit via the resistor R1.

[0007] The second setting terminal is connected in series with the second operational amplifier unit via the resistor R3.

[0008] The third setting terminal is connected in series with the third operational amplifier unit via the resistor R5.

[0009] The first operational amplifier unit includes an operational amplifier U1, and the output end of the operational amplifier U1 is connected to the Q point through the resistor R7.

[0010] The second operational amplifier unit includes an operational amplifier U2. The output end of the operational amplifier U1 is connected to the Q point through the anode of the diode D1.

[0011] The third operational amplifier unit includes an operational amplifier U3, the output end of the operational amplifier U3 is connected to the Q point through the cathode of the diode D2,

[0012] The inverting input terminals of the operational amplifier U1, operational amplifier U2 and operational amplifier U3 are all connected to point Q.

[0013] The Q point is connected to the positive output terminal through the resistor R8 and the fourth operational amplifier unit.

[0014] The non-inverting input terminal of the operational amplifier U1 is connected to the second branch of the single-pole double-throw switch via the resistor R2, and the second branch is connected to the negative output terminal.

[0015] The non-inverting input terminal of the operational amplifier U2 is connected to the first branch of the single-pole double-throw switch via the resistor R4, and the non-inverting input terminal of the operational amplifier U3 is connected to the first branch of the single-pole double-throw switch via the resistor R6. The first branch is connected to the positive output terminal.

[0016] As a preferred embodiment of the present invention, the fourth operational amplifier unit includes an error amplifier U4 and a capacitor C1.

[0017] As a preferred embodiment of the present invention, a power amplifier AMP1 is provided between the fourth operational amplifier unit and the positive output terminal.

[0018] As a preferred embodiment of the present invention, a differential amplifier PGA1 is provided between the first branch and the positive output terminal, and a differential amplifier PGA2 is provided between the second branch and the negative output terminal.

[0019] As a preferred embodiment of the present invention, the output end of the differential amplifier PGA1 is connected to the first branch, a resistor R9 is provided between the non-inverting input end and the inverting input end of the differential amplifier PGA1, the inverting input end of the differential amplifier PGA1 is connected to the positive output terminal, the non-inverting input end of the differential amplifier PGA2 is connected to the positive output terminal, and the inverting input end of the differential amplifier PGA2 is connected to the negative output terminal.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The utility model provides a bipolar constant voltage current limiting and constant current voltage limiting control circuit. The bipolar constant voltage current limiting and constant current voltage limiting control circuit has the function of limiting the output or sink current in the constant voltage mode, and also has the function of limiting the upper and lower limits of the open circuit voltage in the constant current mode. Its sink current function can make it act as an active load, and is used to measure the load capacity of power supply chips. The bipolar constant voltage current limiting and constant current voltage limiting control circuit has a wide range of uses and strong practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the solutions in the present invention, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 This is a connection diagram of the bipolar constant voltage current limiting and constant current voltage limiting control circuit of the utility model. At this time, it is the constant voltage current limiting mode;

[0024] Figure 2 This is a connection diagram of the bipolar constant voltage current limiting and constant current voltage limiting control circuit of the utility model. At this time, it is the constant current voltage limiting mode. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0026] like Figure 1 As shown, the bipolar constant voltage and current limiting, constant current and voltage limiting control circuit includes a first setting terminal FDAC, a second setting terminal C+_DAC and a third setting terminal C-_DAC.

[0027] It should be noted that the first setting terminal FDAC is used to set the output voltage or current of the system. The output of the second setting terminal C+_DAC is a negative voltage, which is used to set the magnitude of the positive clamping current or positive clamping voltage of the system. The output of the third setting terminal C-_DACC-_DAC is a positive voltage, which is used to set the magnitude of the negative clamping current or negative clamping voltage of the system.

[0028] The first setting terminal FDAC is connected in series to the first operational amplifier unit L1 via the resistor R1 , the second setting terminal C+_DAC is connected in series to the second operational amplifier unit L2 via the resistor R3 , and the third setting terminal C−_DAC is connected in series to the third operational amplifier unit L3 via the resistor R5 .

[0029] In addition, the first operational amplifier unit L1 includes an operational amplifier U1, the output end of which is connected to point Q via a resistor R7. The second operational amplifier unit L2 includes an operational amplifier U2, the output end of which is connected to point Q via an anode of a diode D1. The third operational amplifier unit L3 includes an operational amplifier U3, the output end of which is connected to point Q via a cathode of a diode D2.

[0030] In addition, the inverting input terminals of the operational amplifier U1 , the operational amplifier U2 , and the operational amplifier U3 are all connected to the Q point.

[0031] The Q point is connected to the positive output terminal OUT+ through the resistor R8 and the fourth operational amplifier unit L4. The fourth operational amplifier unit L4 includes an error amplifier U4 and a capacitor C1.

[0032] In addition, the non-inverting input terminal of the operational amplifier U1 is connected to the second branch K2 of the single-pole double-throw switch S1 via the resistor R2, and the second branch K2 is connected to the negative output terminal OUT-.

[0033] This bipolar constant-voltage current-limiting and constant-current voltage-limiting control circuit also includes a single-pole double-throw switch S1, which is used to directly switch the system output between voltage mode and current mode. This will be further explained later.

[0034] The non-inverting input terminal of the operational amplifier U2 is connected to the first branch K1 of the single-pole double-throw switch S1 via the resistor R4. The non-inverting input terminal of the operational amplifier U3 is connected to the first branch K1 of the single-pole double-throw switch S1 via the resistor R6. The first branch K1 is connected to the positive output terminal OUT+.

[0035] In addition, a power amplifier AMP1 is provided between the fourth operational amplifier unit L4 and the positive output terminal OUT+.

[0036] A differential amplifier PGA1 is provided between the first branch K1 and the positive output terminal OUT+, and a differential amplifier PGA2 is provided between the second branch K2 and the negative output terminal OUT−.

[0037] The output end of the differential amplifier PGA1 is connected to the first branch K1.

[0038] A resistor R9 is provided between the non-inverting input and the inverting input of the differential amplifier PGA1. Resistor R9 is used for current sampling to measure the actual output current of the system. The voltage difference between its two ends is differentially amplified by the amplifier PGA1 and then sent back to the feedback system.

[0039] The inverting input terminal of the differential amplifier PGA1 is connected to the positive output terminal OUT+, the non-inverting input terminal of the differential amplifier PGA2 is connected to the positive output terminal OUT+, and the inverting input terminal of the differential amplifier PGA2 is connected to the negative output terminal OUT-. The actual voltage output of the system is differentially amplified by the differential amplifier PAG2 and then sent to the feedback system.

[0040] The specific working principle of the system is further explained below.

[0041] Mode 1

[0042] Assume that the system operates in the output voltage clamp current mode, that is, the double-pole double-throw switch S1 is turned to Figure 1The output of the first setting terminal FDAC is Uf, the output of the second setting terminal C+_DAC is Ua, and the output of the third setting terminal C-_DAC is Ub. The gain of amplifier PGA1 is gain1, and the gain of amplifier PAG2 is gain2. The actual output voltage of the system is Uo, and the actual output current is Io. Then the following equation holds:

[0043] Fb_A=Im=Io*gain1:

[0044] Fb_B=Vm=Uo*gain2:

[0045] The output of the second setting terminal C+_DAC is Ua and the system feedback voltage Fb_A will be summed through resistors R3 and R4. The sum voltage is When the voltage of V2 is less than 0 (i.e., the current clamp is not triggered), since the voltage of the inverting terminal of the operational amplifier U2 is 0 and the voltage of the non-inverting terminal of the operational amplifier U2 is less than the voltage of the inverting terminal, the output of the operational amplifier U2 is negative, and the diode D1 is in the reverse cut-off state. At this time, the operational amplifier U2 does not play a controlling role in the circuit.

[0046] Similarly, the output of the second setting terminal C+_DAC is Ub and the system feedback voltage Fb_A will be summed through resistors R5 and R6, and the sum voltage is When the voltage of V3 is greater than 0 (i.e. the current clamp is not triggered), the output of the operational amplifier 3 is positive, and the diode D2 is also in a reverse cutoff state. At this time, the operational amplifier U3 does not play a controlling role in the circuit.

[0047] The output Uf of the first setting terminal FDAC and the system feedback voltage Fb_B are summed through resistors R1 and R2. When V1 is greater than 0, the output of the operational amplifier U1 will output a positive voltage. Since the operational amplifier U3 is an inverting integrator, it will force the power amplifier AMP1 to output a voltage in the opposite direction until the system reaches stability when V1 is 0. When V1 is less than 0, the output of the operational amplifier U1 will output a negative voltage. After the inversion of the operational amplifier U3, AMP1 also outputs a voltage in the opposite direction until the system reaches stability when V1 is 0. At this time, the system current clamp is not triggered because Fb_B=Uo*gain2: Therefore, the output voltage of the system is

[0048] Let's explore the working principle of current clamping.

[0049] Assuming that the system output voltage is positive, the system output current Io value increases to the voltage of the summing point V2 of the operational amplifier U2 is greater than 0. At this time, the operational amplifier U2 outputs a positive voltage, and the diode D1 enters the forward conduction state. It will reduce the system output voltage through the inverting terminal of the error amplifier U4 until the actual output current Io of the system makes V2 = 0. At this time, the system is in the current positive clamping state. so And Fb_A=Io*R9*gain1, so The clamping current can be adjusted by adjusting the value of Ua. In addition, the voltage of V3 is still greater than 0 in this state, so the operational amplifier U3 and the diode D2 still do not work in the system control.

[0050] At this point, if the system is sunk by a current Ii whose direction is opposite to the system output current, then the output voltage of the external load will be higher than the system output voltage. At this time, the value of Fb_A is negative, and D1 is still in the reverse cutoff state. At this time, it and the operational amplifier U2 do not play a role in system control. When the sunk current continues to increase to V3<0, the diode D2 begins to conduct forward, and the voltage of V4 will decrease, so the output voltage of the system will increase until the system enters a stable state when V3=0. At this time, the output current of the system This function allows the system to absorb external power, that is, to act as an electronic load.

[0051] Assuming the system output voltage is negative, the system output current Io value increases to the point where the voltage of the summing point V3 of the operational amplifier U3 is less than 0, the diode D2 starts to conduct forward, and the voltage of V4 will decrease, so the system output voltage will increase, that is, the absolute value of the output voltage will decrease. Until V3 = 0, the system enters a stable state, at which time the system output current The clamping current can be adjusted by adjusting the value of Ub. In addition, the voltage of V2 is still less than 0 in this state, so the operational amplifier U2 and the diode D1 still do not work in the system control.

[0052] At this time, if the system is sunk by current Ii, and its direction is opposite to the system output current, it means that the output voltage of the external load is lower than the output voltage of the system. At this time, the value of Fb_A is positive, and the voltage of V3 is still greater than 0, so the operational amplifier U3 and diode D2 still do not work in the system control. When the sunk current continues to increase to V2>0, the diode D1 starts to conduct forward, and the voltage of V4 will increase, so the output voltage of the system will decrease until V3=0. The system enters a stable state. At this time, the output current of the system This function allows the system to absorb external power, that is, to act as an electronic load.

[0053] Therefore, the circuit system can clamp bipolar current in bipolar voltage output mode.

[0054] Mode 2

[0055] Now let's discuss the system working in output current clamp voltage mode. The double-pole double-throw switch is switched to Figure 2 In the position shown, the first setting terminal FDAC of the system is used to set the output current of the system, the second setting terminal C+_DAC is used to set the positive clamping voltage of the system, and the third setting terminal C-_DAC is used to set the negative clamping voltage of the system.

[0056] Assume that the output of the first setting terminal FDAC is Uf, the output of the second setting terminal C+_DAC is Ua, the output of the third setting terminal C-_DAC is Ub, the gain of amplifier PGA1 is gain1, the gain of amplifier PAG2 is gain2, the current actual output voltage of the system is Uo, and the actual output current is Io. Then the following equation holds:

[0057] Fb_A=Vm=Uo*gain2:

[0058] Fb_B=Im=Io*gain1:

[0059] The output of the second setting terminal C+_DAC is Ua and the system feedback voltage Fb_A will be summed through resistors R3 and R4. The sum voltage is When the voltage of V2 is less than 0 (i.e., the voltage clamp is not triggered), since the voltage at the inverting terminal of the operational amplifier U2 is 0 and the voltage at the non-inverting terminal of the operational amplifier U2 is less than the voltage at the inverting terminal, the output of the operational amplifier U2 is negative, and the diode D1 is in a reverse cutoff state. At this time, the operational amplifier U2 does not play a controlling role in the circuit.

[0060] Similarly, the output of the second setting terminal C+_DAC is Ub and the system feedback voltage Fb_A will be summed through resistors R5 and R6, and the sum voltage is When the voltage of V3 is greater than 0 (ie, the voltage clamp is not triggered), the output of the operational amplifier U3 is positive, and the diode D2 is also in a reverse cutoff state. At this time, the operational amplifier U3 does not play a controlling role in the circuit.

[0061] The output Uf of the first setting terminal FDAC and the system feedback voltage Fb_B are summed through resistors R1 and R2. When V1 is greater than 0, the output of the operational amplifier U1 will output a positive voltage. Since the operational amplifier U3 is an inverting integrator, it will force the power amplifier AMP1 to output a voltage in the opposite direction until the system reaches stability when V1 is 0. When V1 is less than 0, the output of the operational amplifier U1 will output a negative voltage. After the inversion of the operational amplifier U3, AMP1 also outputs a voltage in the opposite direction until the system reaches stability when V1 is 0. At this time, the system voltage clamp is not triggered. Fb_B=-1*Uf*R1 / R2,Fb_B=Io*R9*gain1, so the output current of the system is

[0062] When the system outputs positive current, the system is open or the load resistance is too large, causing the system output voltage to increase and the voltage at Vf to be positive. When its voltage makes the voltage at the summing point V2 of the operational amplifier U2 greater than 0, the operational amplifier U2 outputs a positive voltage and the diode D1 is turned on, causing the voltage at V4 to increase and the system output voltage Uo to decrease until the voltage at V2 is equal to 0 and the system is in a stable state. Fb_A = -1*Ua*R4 / R3; and Fb_A = Uo*gain2. At this time, the system clamping voltage is Uo = -1*Ua*R4 / R3 / gain2.

[0063] When the system outputs negative current, the system is open or the load resistance is too large, causing the system output voltage to continue to drop, so the voltage at Vf is also negative. When its voltage makes the voltage at the summing point V3 of the operational amplifier U3 less than 0, the operational amplifier U3 outputs a negative voltage, and the diode D2 is turned on, causing the voltage at V4 to decrease and the system output voltage Uo to rise until the voltage at V2 is equal to 0 and the system is in a stable state. Fb_A = -1*Ua*R4 / R3; and Fb_A = Uo*gain2. At this time, the system clamping voltage is Uo = -1*Ub*R6 / R5 / gain2.

[0064] When the system is operating in constant-current and voltage-limited mode, if another current source is connected to the system's output, the voltage across it will be limited by the system's voltage clamping value. Specifically, if the external current source outputs a positive current, the voltage it produces will also be positive. The current it sinks through R9 is absorbed by AMP1, and its maximum output voltage will be clamped to -1*Ua*R4 / R3 / gain2. If the external current source outputs a negative current, the voltage it produces will also be negative. The current it sinks is provided by AMP1 through R9, and its minimum output voltage will be clamped to -1*Ub*R6 / R5 / gain2.

[0065] Therefore, the circuit system can clamp bipolar voltage in bipolar current output mode.

[0066] This bipolar constant voltage current limiting and constant current voltage limiting control circuit has the function of limiting the output or sink current in constant voltage mode, and also has the function of limiting the upper and lower limits of its open circuit voltage in constant current mode. Its sink current function can enable it to act as an active load to measure the load capacity of power supply chips. It has a wide range of uses and strong practicality.

[0067] Obviously, the embodiments described above are only part of the embodiments of the present application, rather than all the embodiments. The drawings provide preferred embodiments of the present application, but do not limit the patent scope of the present application.

Claims

1. A bipolar constant voltage current limiting and constant current voltage limiting control circuit, characterized in that: The bipolar constant voltage current limiting and constant current voltage limiting control circuit comprises a first setting terminal (FDAC), a second setting terminal (C+_DAC) and a third setting terminal (C-_DAC). The first setting terminal (FDAC) is connected in series with the first operational amplifier unit (L1) via the resistor R1. The second setting terminal (C+_DAC) is connected in series with the second operational amplifier unit (L2) via the resistor R3. The third setting terminal (C-_DAC) is connected in series with the third operational amplifier unit (L3) via the resistor R5. The first operational amplifier unit (L1) includes an operational amplifier U1, the output end of which is connected to the Q point via a resistor R7. The second operational amplifier unit (L2) includes an operational amplifier U2. The output end of the operational amplifier U1 is connected to the Q point through the anode of the diode D1. The third operational amplifier unit (L3) includes an operational amplifier U3, the output end of which is connected to the Q point via the cathode of the diode D2. The inverting input terminals of the operational amplifier U1, operational amplifier U2 and operational amplifier U3 are all connected to point Q. The Q point is connected to the positive output terminal (OUT+) through the resistor R8 and the fourth operational amplifier unit (L4). The non-inverting input terminal of the operational amplifier U1 is connected to the second branch (K2) of the single-pole double-throw switch (S1) via the resistor R2, and the second branch (K2) is connected to the negative output terminal (OUT-). The non-inverting input terminal of the operational amplifier U2 is connected to the first branch (K1) of the single-pole double-throw switch (S1) via the resistor R4, and the non-inverting input terminal of the operational amplifier U3 is connected to the first branch (K1) of the single-pole double-throw switch (S1) via the resistor R6, and the first branch (K1) is connected to the positive output terminal (OUT+).

2. The bipolar constant voltage and current limiting control circuit according to claim 1, characterized in that: The fourth operational amplifier unit (L4) includes an error amplifier U4 and a capacitor C1.

3. The bipolar constant voltage and current limiting control circuit according to claim 1, characterized in that: A power amplifier AMP1 is provided between the fourth operational amplifier unit (L4) and the positive output terminal (OUT+).

4. The bipolar constant voltage and current limiting control circuit according to claim 1, characterized in that: A differential amplifier PGA1 is provided between the first branch (K1) and the positive output terminal (OUT+), and a differential amplifier PGA2 is provided between the second branch (K2) and the negative output terminal (OUT-).

5. The bipolar constant voltage and current limiting control circuit according to claim 4, characterized in that: The output end of the differential amplifier PGA1 is connected to the first branch (K1), a resistor R9 is provided between the non-inverting input end and the inverting input end of the differential amplifier PGA1, the inverting input end of the differential amplifier PGA1 is connected to the positive output terminal (OUT+), the non-inverting input end of the differential amplifier PGA2 is connected to the positive output terminal (OUT+), and the inverting input end of the differential amplifier PGA2 is connected to the negative output terminal (OUT-).

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