High-power-consumption complex SoC anti-radiation test hardware system

Abstract

The utility model discloses a high-power-consumption complex SoC anti-radiation test hardware system. Current monitoring of a high-power-consumption complex SoC is realized through a programmable power supply, an LDO power supply chip and a current acquisition unit. Stable power supply of the high-power-consumption complex SoC is realized through the power supply negative feedback and overvoltage protection unit; in order to meet the requirement of an anti-radiation test on the function test of all peripheral controllers of the SoC, expensive peripheral devices such as a special transceiver and an interface are abandoned, and the function test of all peripheral controllers of the complex SoC under the miniaturized PCB area is realized through the loopback design of each peripheral. The problems that an existing SoC anti-radiation test system cannot stably supply power to a large-power-consumption SoC and monitor current, and cannot comprehensively test a complex SoC with multiple peripheral controllers at low cost are solved.

Description

Technical Field

[0001] The utility model relates to the field of embedded hardware applied to radiation resistance testing, in particular to a high-power consumption complex SoC radiation resistance testing hardware system. Background Art

[0002] Currently, SoC processors based on the SPARC architecture are widely used in embedded systems such as aerospace, aviation, and industrial control. With the continuous development of SPARC-based SoCs, the SoC frequency has increased to 1GHz, the number of cores has grown from a single core to eight, the core current has increased to 10A, the core voltage has dropped to 0.8V, and the processor is more sensitive to noise. This has greatly increased the power supply and stability requirements of the hardware system.

[0003] In the field of radiation resistance testing, in the radiation resistance testing hardware system based on the SPARC architecture, the objects to be tested, namely the peripheral controllers inside the SoC, are more abundant, with up to more than ten types. Given that radiation resistance testing requires comprehensive testing, and the space of the radiation resistance test site is limited, the PCB area cannot be too high. This requires the hardware system design to not only meet the normal operation of the SoC, but also to test all peripheral controllers while keeping the PCB area as small as possible.

[0004] Traditional SoC radiation-hardening hardware system designs are minimalist, ensuring only the proper functioning of the SoC processor while inadequately testing peripheral controllers for radiation-hardening. For the current monitoring required for radiation-hardening testing, the traditional method involves directly supplying power to each SoC power source through a programmable power supply and monitoring the current. However, for complex, high-power SoCs, the voltage drop from a programmable power supply can be significant, leading to unstable system operation. Furthermore, voltage settings can be incorrect, potentially damaging the system. Utility Model Content

[0005] The technical problem solved by the utility model is: to overcome the shortcomings of the existing technology, provide a high-power complex SoC radiation resistance test hardware system, solve the problem of safe and stable power supply of high-power complex SoC, and the problem of comprehensive peripheral controller testing with the smallest PCB area possible.

[0006] The technical solution of the utility model is: a high-power consumption complex SoC radiation resistance test hardware system, including a SoC processor, a peripheral module, a storage module and a configuration module connected to the SoC processor, and also including a power module, one end of the power module is connected to an external programmable power supply, and the other end is connected to the SoC processor, for supplying power to the SoC processor and monitoring the supply current; the power module includes an overvoltage protection unit, a current acquisition unit, a SoC core power supply unit, and a SoC IO power supply unit; the overvoltage protection unit is connected between the programmable power supply and the current acquisition unit, the current acquisition unit is respectively connected to the SoC core power supply unit and the SoC IO power supply unit, and the SoC core power supply unit and the SoC IO power supply unit are both connected to the SoC processor; the SoC core power supply unit includes multiple parallel LDO power supply chips, which jointly supply power to the SoC processor core; the SoC IO power supply unit includes multiple LDO power supply chips, each LDO power supply chip supplies power to each IO power domain of the SoC processor; the peripheral modules include 1553B and CAN, which are all connected to the SoC processor in an external loopback manner.

[0007] Furthermore, the output end of each LDO power chip of the SoC core power supply unit is respectively connected in series with a ballast resistor, so that the voltage drops of the parallel LDO power chips are reduced to the same voltage.

[0008] Furthermore, the SENSE pin of each LDO power chip of the SoC core power supply unit is wired to the input end of the SoC processor to form negative feedback to compensate for the voltage drop.

[0009] Furthermore, the SoC core power supply unit includes three parallel LDO power chips, all of which use LDOTPS7A57 power chips; the SoC IO power supply unit includes three LDO power chips, all of which use LDOTPS7440 power chips.

[0010] Furthermore, the current acquisition unit includes a core current monitor and an IO current monitor; the core current monitor is connected to the SoC core power supply unit and uses a current detection chip based on the Hall effect to monitor the power supply current of the SoC core power supply unit; the IO current monitor is connected to the SoC IO power supply unit and uses a sampling resistor plus an operational amplifier to monitor the power supply current of the SoC IO power supply unit; the core current monitor and the IO current monitor are also connected to the ADC, and the ADC is connected to the SoC processor through the SPI interface. The monitoring results of the core current monitor and the IO current monitor are converted from analog to digital by the ADC and then transmitted to the SoC processor through the SPI interface.

[0011] Furthermore, each power pin of the SoC processor is connected to a decoupling capacitor to ground to filter out high-frequency noise interference.

[0012] Furthermore, the external loopback connection method of 1553B in the peripheral module is as follows: the inputs of the two 1553B controllers integrated inside the SoC processor are interconnected to form a 1553B bus architecture, and the output of each 1553B is connected to the input of the other through a three-state gate.

[0013] Furthermore, the external loopback connection method of CAN in the peripheral module is as follows: the inputs of the two CAN controllers integrated inside the SoC are interconnected to form a CAN bus architecture, and the output of each CAN is connected to the CAN bus through a NOT gate and an OD gate.

[0014] Furthermore, the storage module includes three FLASH chips. The two chip select signals of the SoC processor for the FLASH are ANDed through an AND gate and output to the three FLASH chips. The DIP switch controls whether the high address line of the FLASH is connected to the low address line pin of the SoC processor, and controls the FLASH to 8 / 16 / 32-bit width.

[0015] The advantages of this utility model compared with the prior art are:

[0016] (1) The utility model improves the safety and stability of power supply for complex SoC with large power consumption through the design of power module transfer, overvoltage protection and high current power supply negative feedback, and better meets the requirements of anti-radiation latch test for power consumption current test and stability.

[0017] (2) The current acquisition unit of the utility model is designed with a sampling resistor + operational amplifier circuit for small current of SoC, and a Hall effect current acquisition circuit for large current of SoC; the acquisition result is then converted by ADC and transmitted to the SoC processor through the SPI interface to realize real-time monitoring of current, making current monitoring more convenient, fast and simple.

[0018] (3) The peripheral module of the utility model adopts a loopback design, abandoning the traditional transceiver and interface that takes up a large PCB area and is expensive, and realizes the testing of all SoC peripheral controller functions using the minimum PCB area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the hardware system composition of the utility model;

[0020] Figure 2 This is a composition diagram of the power module of the utility model;

[0021] Figure 3 This is the circuit diagram of the overvoltage protection unit of the utility model;

[0022] Figure 4 This is a schematic diagram of the current monitoring method of the utility model;

[0023] Figure 5This is the circuit diagram of the IO current monitor of the utility model. DETAILED DESCRIPTION

[0024] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] This embodiment shows a high power consumption complex SoC radiation resistance test hardware system, such as Figure 1 As shown, the system consists of a SoC processor, power module, peripheral module, storage module, and configuration module. The configuration module implements basic configurations such as the SoC clock, reset, and PLL. The storage module stores and reads and writes SoC programs and data. The peripheral module implements loopback processing for each SoC peripheral controller, allowing testing of the corresponding peripheral controllers in the SoC processor. The power module relays the programmable power supply, providing stable power to the SoC processor and monitoring the supply current.

[0026] Power modules, such as Figure 2 As shown, it includes a power supply selection unit, a DC-DC conversion unit, an overvoltage protection unit, a SoC core power supply unit, a SoC IO power supply unit, and a current acquisition unit.

[0027] In one possible implementation, the power supply selection unit provides two power supply options for the system. During radiation resistance testing, a programmable power supply is used to power the LDO power chip through the COM port. The LDO power chip then acts as a relay to power the SoC processor. This avoids the problem of excessive voltage drop and unstable power supply caused by the programmable power supply directly powering the high-power SoC processor. The input current of the LDO power chip is equal to the output current, so the current of each power supply of the SoC can be obtained by monitoring the input current of the LDO power chip. During daily debugging, a power adapter is used to provide power input.

[0028] In a possible implementation, the DC-DC conversion unit is used to perform DC conversion on the input current, and preferably uses a DCDCLTM4644 chip.

[0029] In a possible implementation, the overvoltage protection unit is provided between the COM port and the current acquisition unit, such as Figure 3As shown, the circuit consists of a Zener diode, a PNP diode, and a PMOS diode. When the input voltage is less than the Zener diode's reverse breakdown voltage, the Zener diode does not conduct. The PNP diode's base (pole b) is at the input voltage, and the voltage difference between the e and b electrodes is 0, causing the PNP diode to not conduct. When the PMOS diode's VGS is less than 0, the PMOS diode conducts, allowing the input voltage to be transmitted to the subsequent circuitry. When the input voltage exceeds the Zener diode's reverse breakdown voltage, the Zener diode conducts. When the PNP diode's b electrode is grounded and its Vbe is greater than 0.7V, the PNP diode conducts. When the PMOS diode's VGS = 0, the PMOS diode does not conduct, preventing the input voltage from being transmitted to the subsequent circuitry. Thus, by selecting Zener diodes with different reverse breakdown voltages, overvoltage protection for different voltages can be achieved.

[0030] In one possible implementation, the SoC core power supply unit uses multiple LDO power chips connected in parallel to collectively provide the current required by the SoC core. In this embodiment, the core current of a high-power, complex SoC can reach as high as 10A, so the core power supply requires a higher power supply capacity. Three LDO power chips are connected in parallel to provide a 15A power supply capacity. A 2mΩ ballast resistor is connected in series with the power output terminals of the three LDO power chips to ensure that the parallel LDOs drop to the same voltage and output current. Due to the excessive core current, there will be a significant voltage drop between the power chip output and the processor input. Therefore, the SENSE pin of the LDO power chip is routed to the processor input to form negative feedback to avoid far-end voltage drop. Different voltage divider resistors are selected through the pins to achieve high and low biasing of the SoC core power supply voltage. Preferably, the three parallel LDO power chips in the SoC core power supply unit all use LDOTPS7A57 power chips.

[0031] In one possible implementation, the SoC IO power supply unit includes multiple LDO power chips, each of which provides the current required by each SoC IO. Different voltage divider resistors are selected via pins to achieve high and low biasing of the SoC IO supply voltage. Preferably, the SoC IO power supply unit includes three LDO power chips, all of which are LDOTPS7440 power chips.

[0032] In one possible implementation, the current acquisition unit monitors the supply current of the SoC core power supply unit and the SoC IO power supply unit. The current acquisition unit includes a core current monitor and an IO current monitor. The SoC in this system has four power supplies (three IO power supplies and one core power supply). For the three IO power supplies with lower current (10mA to 100mA), the IO current monitor uses a sampling resistor plus an op amp to monitor the supply current of the three IO power supplies. For the SoC's core power supply (15A), the core current monitor uses a Hall-effect current detection chip to monitor the supply current of the single core power supply. The measurement range is -20A to 20A, the impedance is 1.2mΩ, the voltage drop is very small, and the accuracy is 100mV / 1A.

[0033] Among them, the IO current monitor converts the current into a voltage signal through a sampling resistor, and then amplifies the voltage signal through a current detection circuit constructed by an operational amplifier (the current sampling point is at the power supply end of the load).

[0034] From the operational amplifier positive terminal virtual disconnection, we can know that: V+ / R7=(V2-V+) / R5;

[0035] From the negative terminal of the op amp, we can know that: (V--VOUT) / R1=(V1-V-) / R2;

[0036] From the virtual short circuit of the op amp, we can know that: V+=V-;

[0037] Let R1 = R7, R2 = R5;

[0038] In summary, VOUT = I*R1*R4 / R2;

[0039] R1 is the precision control resistor. The above formula is used to set the appropriate resistance value so that the measurement accuracy is 5V / 1A and the measurement accuracy is 0~1A.

[0040] like Figure 4 As shown, the voltage signal collected by the sampling resistor + op amp circuit and the Hall-effect-based current detection chip is converted into a digital signal via an ADC analog-to-digital conversion circuit. The digital signal containing current information obtained by the ADC chip is connected to the SoC processor via an SPI interface, enabling complete current monitoring. A first-order RC low-pass filter circuit with a cutoff frequency of 480kHz is installed at the ADC analog signal input to filter out MHz-level DC-DC switching noise and crystal oscillator signals.

[0041] The peripheral module implements the external loopback and basic configuration of the 1553B, SpaceWire, CAN, PCIe, SRI, MAC, I2C, SPI and other peripheral controllers integrated within the SoC processor. Specifically includes:

[0042] (1) 1553B: The inputs of the two 1553B controllers integrated within the SoC are interconnected to form a 1553B bus architecture. The output of each 1553B is connected to the input of the other through a tri-state gate under the action of a control signal.

[0043] (2) CAN: The inputs of the two CAN controllers integrated inside the SoC are interconnected to form a bus architecture, and the output of each CAN is connected to the CAN bus through a wired-AND (NOT gate + OD gate).

[0044] (3) MAC: Provides clock to the MAC controller of the SoC through the transceiver PHY chip, and performs loopback processing on the input and output interconnections.

[0045] (4) SPACEWIRE: A 10MHz crystal oscillator provides clock to the SoC's SPACEWIRE controller, and the input and output interconnections are looped back.

[0046] (4) PCIe / Srio: Provides a homologous differential clock to the PCIe / Srio controller of the SoC through a homologous clock buffer, and performs loopback processing on the input and output interconnections.

[0047] The storage module implements the storage, reading and writing of SoC programs and data, including FLASH, SRAM, and DDR. The specific methods are:

[0048] (1) FLASH: used to store non-volatile programs and data such as power-on self-start.

[0049] Chip select control: The SoC processor in this embodiment supports a maximum of 256MB of flash memory, divided into two chip selects, supporting 8, 16, and 32-bit widths and EDAC functionality. A 32-bit implementation with one-check-one-correction requires a set of three flash memories. Traditional designs with two chip selects require a total of six flash memories. This embodiment uses an AND gate to combine the chip select signals from the SoC processor's two memory modules and then provides them to the three flash memories, allowing them to fully utilize the two chip selects for a total of 256MB.

[0050] Bit width control: The DIP switch controls whether the high-order address line of FLASH is connected to the low-order address line A0 / A1 of the processor SoC to determine the 8 / 16 / 32-bit width mode of FLASH.

[0051] (2) SRAM: used to run programs.

[0052] Bit width control: The bit width mode of the SRAM device is determined by controlling whether the high-order address line of the SRAM is connected to the low-order address line A0 / A1 of the SoC processor through the pin.

[0053] (3)DDR4: used to run programs.

[0054] It occupies the entire 2GB space of the SoC processor, supports the one-correction-two-detection function, 3200MT / s, and adopts the FLY-BY topology PCB design.

[0055] Configuration module, used to implement basic configurations such as reset, PLL, signal indication, etc. The specific method is:

[0056] (1) Reset: There are four reset modes: system reset, SoC internal reset, button reset, and watchdog reset.

[0057] The system reset uses a reset chip. When the system is powered on, the reset chip starts to generate a 200ms low-level reset signal when the voltage is higher than the operating voltage. After stabilizing at the threshold voltage, the reset signal maintains a high level.

[0058] SoC internal reset is set to POR (power-on reset) mode through the SoC configuration pin. When powered on, a low-level reset signal of 10ms is generated.

[0059] Push button reset: Connect the button to the MR pin of the reset chip and ground, and manually press the button to provide a reset signal.

[0060] Watchdog reset: The watchdog output signal of the SoC and the reset signal of the reset chip are output through an AND gate and provided to the reset pin of the SoC.

[0061] (2) PLL configuration: The PLL needs to start working for a period of time after the SoC is powered on. That is, the PLL powerdown signal needs to maintain a high level for a period of time after the processor is powered on.

[0062] The PLL's powerdown signal, a low-level continuous signal, is generated by an RC charging circuit with a set RC time constant of 2ms. The RC circuit is powered by the SoC's I / O power supply. The core power chip's powergood signal controls the MOS transistors that supply power to the RC circuit, ensuring that it generates a low-level signal only after the SoC is powered. The RC circuit generates a gradually rising analog signal waveform, which is then converted into a high-level continuous digital signal of 2 to 4ms via a NOT gate circuit with a Schmitt trigger.

[0063] The bypass pin, frequency multiplication pin, and frequency division pin of the PLL module enable the 25MHz peripheral crystal oscillator to generate the required SoC main frequency through appropriate pull-up and pull-down.

[0064] SoC signal indication: SoC error signal, watchdog signal, and PLL lock signal control the LED light through the MOS tube to avoid current injection. Since these signals are open-drain outputs, they are pulled up.

[0065] It is understood that the present invention is described by way of examples, and those skilled in the art will appreciate that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the guidance of the present invention, these features and embodiments may be modified to suit specific circumstances without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and any embodiments that fall within the scope of the claims of this application are intended to be protected by the present invention.

[0066] The contents not described in detail in the specification of the present utility model belong to the common knowledge of those skilled in the art.

Claims

1. A high-power complex SoC radiation resistance test hardware system, comprising an SoC processor, a peripheral module connected to the SoC processor, a storage module, and a configuration module, characterized in that: It also includes a power module, one end of which is connected to an external programmable power supply and the other end is connected to the SoC processor to power the SoC processor and monitor the power supply current; the power module includes an overvoltage protection unit, a current acquisition unit, a SoC core power supply unit, and a SoC IO power supply unit; the overvoltage protection unit is connected between the programmable power supply and the current acquisition unit, and the current acquisition unit is respectively connected to the SoC core power supply unit and the SoC IO power supply unit, and the SoC core power supply unit and the SoC IO power supply unit are both connected to the SoC processor; the SoC core power supply unit includes multiple parallel LDO power supply chips to jointly power the SoC processor core; the SoC IO power supply unit includes multiple LDO power supply chips, each LDO power supply chip respectively supplies power to each IO power domain of the SoC processor; the peripheral modules include 1553B and CAN, both of which are connected to the SoC processor in an external loopback manner.

2. The high-power complex SoC radiation resistance test hardware system according to claim 1 is characterized by: The output end of each LDO power chip of the SoC core power supply unit is connected in series with a ballast resistor to make the voltage drop of the parallel LDO power chips to the same voltage.

3. The high-power complex SoC radiation resistance test hardware system according to claim 2 is characterized in that: The SENSE pin of each LDO power chip in the SoC core power supply unit is wired to the input end of the SoC processor to form negative feedback and compensate for the voltage drop.

4. The high-power complex SoC radiation resistance test hardware system according to any one of claims 1 to 3, characterized in that: The SoC core power supply unit includes three parallel LDO power chips, all of which use the LDOTPS7A57 power chip; the SoC IO power supply unit includes three LDO power chips, all of which use the LDOTPS7440 power chip.

5. The high-power complex SoC radiation resistance test hardware system according to claim 1 is characterized in that: The current acquisition unit includes a core current monitor and an IO current monitor. The core current monitor is connected to the SoC core power supply unit and uses a Hall effect-based current detection chip to monitor the supply current of the SoC core power supply unit. The IO current monitor is connected to the SoCIO power supply unit and uses a sampling resistor plus an op amp to monitor the supply current of the SoCIO power supply unit. The core current monitor and IO current monitor are also connected to the ADC, which is connected to the SoC processor through the SPI interface. The monitoring results of the core current monitor and IO current monitor are converted from analog to digital by the ADC and then transmitted to the SoC processor through the SPI interface.

6. The high-power complex SoC radiation resistance test hardware system according to claim 1, characterized in that: Each power pin of the SoC processor is connected to a decoupling capacitor to ground to filter out high-frequency noise interference.

7. The high power consumption complex SoC radiation resistance test hardware system according to claim 1, characterized in that: The external loopback connection method of the 1553B in the peripheral module is as follows: the inputs of the two 1553B controllers integrated inside the SoC processor are interconnected to form a 1553B bus architecture, and the output of each 1553B is connected to the input of the other through a tri-state gate.

8. The high-power complex SoC radiation resistance test hardware system according to claim 1, characterized in that: The external loopback connection method of CAN in the peripheral module is as follows: the inputs of the two CAN controllers integrated in the SoC are interconnected to form a CAN bus architecture, and the output of each CAN is connected to the CAN bus through a NOT gate and an OD gate.

9. The high power consumption complex SoC radiation resistance test hardware system according to claim 1, characterized in that: The storage module includes three FLASH chips. The two chip select signals of the SoC processor for the FLASH are ANDed through the AND gate and output to the three FLASH chips. The DIP switch controls whether the high address line of the FLASH is connected to the low address line pin of the SoC processor, and controls the FLASH width to 8 / 16 / 32 bits.

Images