Semiconductor device including seal ring structure

Abstract

The utility model provides a semiconductor device comprising a sealing ring structure. In one embodiment, a semiconductor device including a seal ring structure includes: a first package component including a first passivation layer; an electronic connector extending through the first passivation layer; a second passivation layer located over the first passivation layer; a first metal pad and a second metal pad embedded in the first passivation layer and the second passivation layer, the first metal pad including a first U-shaped shape, and the second metal pad having a first stepped shape; a first plurality of dielectric layers over the second passivation layer; a first plurality of metallization layers and a second plurality of metallization layers embedded in the first plurality of dielectric layers, the second metal pad and the second plurality of metallization layers being electrically connected with the first metal pad and the first plurality of metallization layers; and an active device over the first plurality of metallization layers and electrically connected to the first plurality of metallization layers.

Description

Technical Field

[0001] The utility model relates to a semiconductor device comprising a sealing ring structure. Background Art

[0002] In wafer-level packaging technology, multiple seal ring structures are formed in the peripheral area of ​​multiple device dies and are used to provide protection for multiple circuits surrounded by the multiple seal rings. The seal rings can prevent moisture from penetrating into the multiple device dies and degrading the multiple circuits surrounded by the multiple seal rings. The multiple seal rings can extend into multiple layers of the integrated circuit structure, such as multiple low-dielectric layers and multiple overlying passivation layers. Utility Model Content

[0003] In one embodiment, a semiconductor device including a seal ring structure includes: a first package component including a first passivation layer; an electronic connector extending through the first passivation layer; a second passivation layer located above the first passivation layer; a first metal pad and a second metal pad embedded in the first passivation layer and the second passivation layer, the first metal pad including a first U-shape and the second metal pad having a first stepped shape; a first plurality of dielectric layers located above the second passivation layer; a first plurality of metallization layers and a second plurality of metallization layers embedded in the first plurality of dielectric layers, the second metal pad and the second plurality of metallization layers being electrically connected to the first metal pad and the first plurality of metallization layers; and an active device located above the first plurality of metallization layers and electrically connected to the first plurality of metallization layers.

[0004] In one embodiment, a semiconductor device including a seal ring structure includes: an active device formed along a front side of a semiconductor substrate; a first plurality of dielectric layers located above the semiconductor substrate; a first plurality of metallization layers located within the first plurality of dielectric layers, the first plurality of metallization layers forming an interconnect structure; a second plurality of metallization layers located within the first plurality of dielectric layers, the second plurality of metallization layers forming a ring surrounding the first plurality of metallization layers; a first metal pad located above and electrically connected to the first plurality of metallization layers, wherein in a cross-sectional view, the first metal pad comprises a U-shape having a left arm and a right arm; a second metal pad located above and electrically connected to the second plurality of metallization layers, the second metal pad forming a ring surrounding the first metal pad; in a cross-sectional view, the second metal pad includes a left portion adjacent to the left arm and a right portion adjacent to the right arm, the left portion having a first stepped shape, the right portion having a second stepped shape, the first stepped shape being a reflection of the second stepped shape, and the U-shaped shape being different from the first stepped shape and the second stepped shape; and a second plurality of dielectric layers located above the first plurality of dielectric layers and encapsulating the first metal pad and the second metal pad.

[0005] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with the attached Figure 1 The following detailed description will best illustrate the present invention and the drawings. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased for clarity of discussion.

[0007] Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A ,as well as Figure 8B Various cross-sectional views are shown of various intermediate stages in the formation of a device die including multiple seal rings, according to various embodiments.

[0008] Figure 6C 、 Figure 7C 、 Figure 8C A top view of a device die and a plurality of seal rings therein is shown according to various embodiments.

[0009] Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 ,as well as Figure 15 Various cross-sectional views are shown illustrating various intermediate stages in the formation of a semiconductor package according to various embodiments.

[0010] Description of Reference Numerals

[0011] 20, 120: packaging components

[0012] 22: Device die

[0013] 24, 124: semiconductor substrate

[0014] 26, 126: Integrated circuit devices

[0015] 28: Interlayer dielectric

[0016] 30, 30SR: Contact plug

[0017] 32, 132: Interconnection

[0018] 34, 34SR, 134, 134SR: Metal wire

[0019] 36, 36SR, 58, 92V, 136, 136SR: perforated

[0020] 38: Dielectric layer

[0021] 40, 140: passivation layer

[0022] 42, 142: Sealing ring

[0023] 46, 46SR, 52, 52SR: Open

[0024] 48:Metal seed layer

[0025] 50: Electroplating mask

[0026] 54, 54SR: conductive material

[0027] 54L: lip shape

[0028] 56:Metal pad

[0029] 56SR:Metal washer / metal washer

[0030] 58SR: Perforated ring / perforated part

[0031] 60: Pad part

[0032] 60SR: Metal ring / gasket part

[0033] 62: passivation layer

[0034] 64: substrate perforation

[0035] 70, 170: carrier

[0036] 72, 74, 86, 172, 186: bonding film

[0037] 76, 176: dielectric packaging layer

[0038] 78, 178: Redistribution layer structure

[0039] 80, 180: polymer layer

[0040] 82, 182: Conductive characteristics

[0041] 84, 184: Joint structure

[0042] 88P, 188P: Bonding pad

[0043] 88V, 188V: Joint through-hole

[0044] 90: rear passivation layer

[0045] 92P:Metal column

[0046] 94:Electrical connector

[0047] 100: Area

[0048] H1, H2, H3, H4: Height

[0049] W1, W2, W3: width DETAILED DESCRIPTION

[0050] The present invention provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0051] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0052] A seal ring for a package component (e.g., a semiconductor device or an integrated circuit die) and a method for forming the same are provided. For example, a plurality of active devices may be formed along a semiconductor substrate, an interconnect structure (e.g., a plurality of metallization layers in a plurality of low dielectric layers) may be formed above the plurality of active devices and electrically connected to the plurality of active devices, and a metal pad layer (e.g., a plurality of metal pads in a plurality of passivation layers). The plurality of active devices, the interconnect structure, and the plurality of metal pads are electrically connected components of the integrated circuit. According to some embodiments of the present invention, the seal ring includes a plurality of lower portions in a plurality of low dielectric layers and an upper portion in the passivation layer. The plurality of lower portions of the seal ring may be formed simultaneously with the interconnect structure, and the plurality of upper portions of the seal ring may be formed simultaneously with the metal pad layer. In some embodiments, the seal ring forms a ring surrounding the plurality of metallization layers and the plurality of metal pads of the integrated circuit. The upper portion of the sealing ring may be located in a plurality of high stress regions of the package component that are susceptible to cracking, delamination, or other types of damage during the manufacture, testing, and / or functional use of the electronic device. The embodiments discussed herein provide a plurality of examples of using the subject matter of the present invention to form a sealing ring (e.g., the upper portion of the sealing ring) to reduce stress in these high stress regions. In addition, a person having ordinary skill in the art will readily understand the modifications that may be made while maintaining the same principles in different embodiments.

[0053] In the various views and illustrative embodiments, the same reference numerals are used to indicate the same components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0054] Figures 1 to 8C Several cross-sectional views and top views are shown showing various intermediate stages of forming a device die and a seal ring therein according to some embodiments of the present invention.

[0055] Figure 1 A cross-sectional view of a package assembly 20 is depicted. According to some embodiments of the present invention, the package assembly 20 is or includes a device wafer that includes a plurality of active devices and possibly a plurality of passive components, which are represented as a plurality of integrated circuit devices 26. A corresponding package assembly 20 may include a plurality of integrated circuit dies or chips 22 therein, with one of the plurality of chips 22 being shown. According to an alternative embodiment of the present invention, the package assembly 20 is an interposer wafer that has no active devices and may or may not include passive devices. According to another alternative embodiment, the package assembly 20 is or includes a package substrate strip that includes a core-less package substrate or a cored package substrate having a core therein. According to another alternative embodiment of the present invention, the package assembly 20 is a reconstructed wafer that includes a plurality of separated device dies and a molding in which the plurality of device dies are molded. In the subsequent discussion, multiple device wafers are used as an example of the package assembly 20, and the package assembly 20 may also be referred to as a wafer 20. The embodiments of the present invention may also be applied to interposer wafers, package substrates, packages, etc.

[0056] According to some embodiments of the present invention, a wafer 20 includes a semiconductor substrate 24 and a plurality of features formed at a top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be formed from or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. The semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. A plurality of shallow trench isolation (STI) regions (not specifically shown) may be formed in the semiconductor substrate 24 to isolate a plurality of active regions in the semiconductor substrate 24. Although not shown, a plurality of through-vias may (or may not) be formed to extend into the semiconductor substrate 24, wherein the plurality of through-vias are used to electrically inter-couple a plurality of features on opposite sides of the wafer 20.

[0057] According to some embodiments of the present invention, wafer 20 includes a plurality of integrated circuit devices 26 formed along a top surface (e.g., a front side surface) of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal-oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit devices 26 are not shown here. According to alternative embodiments, wafer 20 is used to form a plurality of interposers (which do not have active devices), and substrate 24 may be a semiconductor substrate or a dielectric substrate.

[0058] An inter-layer dielectric (ILD) 28 is formed over semiconductor substrate 24 and fills spaces between gate stacks of transistors (not specifically shown) in integrated circuit devices 26. According to some embodiments, ILD 28 is formed from or includes phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, silicon nitride, silicon oxynitride (SiOxNy), a low-K material, or the like. ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or the like.

[0059] A plurality of contact plugs 30 are formed in the interlayer dielectric 28 and are used to electrically connect the plurality of integrated circuit devices 26 to the overlying plurality of metal lines and a plurality of through-vias. According to some embodiments of the present invention, the plurality of contact plugs 30 are formed from or include a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of the plurality of contact plugs 30 may include forming a plurality of contact openings in the interlayer dielectric 28, filling (a plurality of) conductive materials into the plurality of contact openings, and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical polishing process) to level the plurality of top surfaces of the plurality of contact plugs 30 with the top surface of the interlayer dielectric 28.

[0060] A plurality of metal lines 34 and a plurality of through-holes 36 are formed above the interlayer dielectric 28 and the contact plugs 30. The plurality of contact plugs and the overlying plurality of metal lines and the plurality of through-holes are collectively referred to as an interconnect structure 32. The plurality of metal lines 34 and the plurality of through-holes 36 are formed in a plurality of dielectric layers 38 (also referred to as inter-metal dielectrics (IMD)). The plurality of metal lines of the same layer are collectively referred to as metal layers hereinafter. According to some embodiments of the present invention, the interconnect structure 32 includes a plurality of metal layers, which include a plurality of metal lines 34 interconnected with a plurality of through-holes 36. The various layers of metal lines 34 and through-holes 36 may be collectively referred to as metallization layers. The metal lines 34 and through-holes 36 may be formed of copper or copper alloys, or they may be formed of other metals. According to some embodiments of the present invention, the dielectric layer 38 is formed of a low dielectric material. For example, the dielectric constant (k value) of the low dielectric material may be lower than about 3.0. Dielectric layer 38 may include a carbon-containing low-k dielectric material, Hydrogen Silses Quioxane (HSQ), Methyl Silses Quioxane (MSQ), etc. According to some embodiments of the present invention, the formation of multiple dielectric layers 38 includes depositing a porogen-containing dielectric material in the multiple dielectric layers 38 and then performing a curing process to drive off the porogen, so that the remaining dielectric layers 38 are porous.

[0061] The formation of multiple metal lines 34 and multiple through-holes 36 in multiple dielectric layers 38 can include single damascene processes and / or dual damascene processes. In a single damascene process for forming metal lines or through-holes, a trench or through-hole opening (not shown separately) is first formed in one of the multiple dielectric layers 38, and then the trench or through-hole opening is filled with a conductive material. A planarization process such as a chemical mechanical polishing process is then performed to remove excess conductive material above the top surface of the dielectric layer, thereby leaving metal lines or through-holes in the corresponding trenches or through-hole openings. In a dual damascene process, both trenches and through-hole openings are formed in the dielectric layer, with the through-hole openings located below and connected to the trenches. Conductive material is then filled into the trenches and through-hole openings to form metal lines and through-holes, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material located above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0062] The plurality of metal lines 34 and the plurality of through-vias 36 comprise a plurality of top conductive (metal) features, such as a plurality of metal lines, a plurality of metal pads, and / or a plurality of through-vias, in a top dielectric layer 38. According to some embodiments, the top dielectric layer 38 is composed of a low-dielectric material similar to the material of the plurality of lower dielectric layers of the plurality of dielectric layers 38. According to other embodiments, the top dielectric layer 38 is formed of a non-low-dielectric material, which may include silicon nitride, undoped silicate glass (USG), silicon oxide, etc. The top dielectric layer 38 may also have a multi-layer structure, including, for example, two undoped silicate glass layers and a silicon nitride layer therebetween. The top metal features 34, 36 may also be formed of copper or a copper alloy and may have a dual damascene structure or a single damascene structure.

[0063] A passivation layer 40 (sometimes referred to as protection 1 or protection 1) is formed over the interconnect structure 32. According to some embodiments, the passivation layer 40 is formed of a non-low-K and dense dielectric material having a dielectric constant equal to or greater than that of silicon oxide. The passivation layer 40 may be formed of or include an inorganic dielectric material, which may include, but is not limited to, undoped silicate glass, silicon nitride (SiNx), silicon oxide (SiO2), silicon oxynitride (SiONx), silicon oxycarbide (SiOCx), the like, combinations thereof, and / or multilayers thereof. The "x value" represents a relative atomic ratio. According to some embodiments, the top surfaces of the top dielectric layer 38 and the top metal lines 34 are coplanar. Thus, the passivation layer 40 may be a planar layer. According to alternative embodiments, the top conductive features protrude above the top surface of the top dielectric layer 38, and the passivation layer 40 is non-planar.

[0064] The package assembly 20 may also include a plurality of through substrate vias (TSVs) 64 (or a plurality of through substrate vias) formed in the semiconductor substrate 24 and electrically connected to, for example, a plurality of metal lines 34 or a plurality of through vias 36 (e.g., a plurality of metallization layers) of the interconnect structure 32. As shown, the plurality of through substrate vias 64 are embedded in the semiconductor substrate 24 and the interconnect structure 32, and at this stage, the plurality of through substrate vias 64 do not emerge from the backside surface of the semiconductor substrate 24. The through substrate vias 64 may include Cu, Ti, Ta, W, Ru, Co, Ni, or the like, alloys thereof, or combinations thereof. In some embodiments, the through substrate vias 64 are formed by an electroplating process and may include one or more layers (not shown separately), such as a barrier layer, an adhesive layer, a filler material, or the like. In addition, a dielectric liner layer (not specifically shown) may separate the plurality of through substrate vias 64 from the semiconductor substrate 24.

[0065] Please still refer to Figure 1 , the lower portion of seal ring 42 includes a number of contact plugs 30 (also indicated as 30SR), a number of metal lines 34 (also indicated as 34SR), and a number of through-vias 36 (also indicated as 36SR). The plurality of contact plugs 30SR, the plurality of metal lines 34S, and the plurality of through-vias 36SR are formed simultaneously and share the same formation process as the various other contact plugs 30, metal lines 34, and through-vias 36 used for the various electrical connections of the integrated circuit. Each contact plug 30SR, metal line 34SR, and through-via 36SR in seal ring 42 can be physically connected to the features above and below these features to form an integrated seal ring. In addition, when viewed from the top, each contact plug 30SR, metal line 34SR, and through-via 36SR can form a complete ring with no interruptions therein.

[0066] According to some embodiments, the plurality of contact plugs 30SR are electrically connected to the semiconductor substrate 24. A plurality of silicide regions may or may not be present between the plurality of contact plugs 30SR and the semiconductor substrate 24, and physically bond the plurality of contact plugs 30SR and the semiconductor substrate 24. The plurality of plugs 30SR are in physical contact with the semiconductor substrate 24. According to another alternative embodiment, the plurality of contact plugs 30SR are separated from the semiconductor substrate 24 by a dielectric layer, such as a contact etch stop layer (located below the interlayer dielectric layer 28, not shown), the interlayer dielectric layer 28, or the like.

[0067] Figure 2The passivation layer 40 is depicted as being patterned during an etching process to form a plurality of openings 46. The etching process may include a dry etching process, which includes forming a patterned etch mask (not shown), such as a patterned photoresist, and then etching the passivation layer 40. The patterned etch mask is then removed. The plurality of metal lines 34 are exposed through the plurality of openings 46, and the plurality of metal lines 34SR are exposed through the plurality of openings 46SR.

[0068] Figure 3A and Figure 3B A metal seed layer 48 is shown deposited onto the package component 20 . Figure 3B Shown is an enlarged view of region 100. According to some embodiments, metal seed layer 48 includes a titanium layer and a copper layer above the titanium layer. According to alternative embodiments, metal seed layer 48 includes a copper layer in contact with passivation layer 40. The deposition process can be performed using physical vapor deposition, chemical vapor deposition, metal organic chemical vapor deposition, etc.

[0069] Next, a patterned plating mask 50 is formed. According to some embodiments, the plating mask 50 is formed of or includes a photoresist. A plurality of openings 52 are formed in the patterned plating mask 50 to expose the metal seed layer 48.

[0070] Conductive material (features) 54 is then deposited in the plurality of openings 52 and on the metal seed layer 48. According to some embodiments of the present invention, the formation of the conductive material 54 includes an electroplating process, which may include an electrochemical plating process, an electroless plating process, etc. The electroplating is performed in an electroplating chemical solution. The conductive material 54 may include copper, aluminum, nickel, tungsten, etc., or alloys thereof. According to some embodiments, the conductive material 54 includes copper and does not contain aluminum.

[0071] For example, the plating mask 50 is formed to align the sidewalls of the plurality of openings 46SR. As shown, the plating mask 50 can be aligned with one sidewall of each opening 46SR. The resulting conductive material 54SR formed in the plurality of openings 52SR can have a step shape. In some embodiments (as shown), misalignment of the plating mask 50 may cause the conductive material 54SR to have a lip 54L. Even if the plating mask 50 is aligned, multiple lips 54L may be formed because the sidewalls of the openings 46SR have a slope less than vertical. As discussed in more detail below, subsequent process steps may be performed to remove the multiple lips 54L in order to give the conductive material 54SR the desired step shape. In other embodiments, the lip 54L is not formed, and the conductive material 54SR may be formed as shown. Figures 5A to 5BThe resulting conductive material 54SR is formed as shown in subsequent figures.

[0072] Figure 4A and 4B The resulting structure is depicted after removing the plating mask 50 , according to various embodiments. Figure 4B An enlarged view of region 100 is depicted. According to various embodiments, one or more directional (e.g., anisotropic) etching processes may be performed to remove the plurality of lips 54L (if present) from the conductive material 54SR. For example, the directional etching process may be a laterally directional etching process or any suitable etching process. In some embodiments, the etching process includes plasma or laser etching of the lips 54L to avoid over-etching other portions of the conductive material 54SR. Figure 4B The result of removing the plurality of lips 54L is depicted in dashed lines. In some embodiments, the conductive material 54 (and seed layer 48) may have a flat surface after removing the plurality of lips 54L. In other embodiments, the conductive material (and seed layer 48) may have an uneven or non-uniform surface after removing the lips 54L.

[0073] Figure 5A and Figure 5B It is depicted that after removing the plurality of lips 54L from the conductive material 54SR (if necessary), an etching process is performed to remove portions of the plurality of metallic seed layers 48 that are no longer protected by the overlying conductive material 54 . Figure 5B An enlarged view of region 100 is depicted. Throughout the description, the remaining conductive material 54 and the corresponding lower portion of the metal seed layer 48 are collectively referred to as metal pads 56, which include a plurality of through-hole portions 58 (also referred to as a plurality of through-holes) extending to the passivation layer 40 and a plurality of pad portions 60 (also referred to as metal lines) above the passivation layer 40. Some metal pads 56 are used to electrically connect to the interconnect structure 32. These metal pads 56 also include a plurality of through-hole portions 58 and a plurality of pad portions 60, wherein the plurality of through-hole portions 58 physically contact the plurality of top metal features 34.

[0074] Among the plurality of metal pads 56 is a metal ring 56SR, which includes a perforated ring 58SR and a metal ring 60SR, forming the upper portion of seal ring 42. Perforated ring 58SR is in physical contact with underlying metal line 34SR. In some embodiments, each of perforated ring 58SR and metal ring 60SR forms a complete ring without breaks therein and surrounds the interior region of device die 22. Thus, metal ring 56SR is electrically connected to the lower portions of seal ring 42 while being electrically insulated from interconnect structure 32 and integrated circuit device 26.

[0075] Figures 6A to 6C Deposition of a passivation layer 62 is depicted. Figure 6Bis shown as an enlarged view of region 100, and Figure 6C A plan view of chip 22 is shown. A passivation layer 62 (sometimes referred to as protect 2 or protect 2) is formed as a blanket layer over the plurality of metal pads 56. According to some embodiments, passivation layer 62 is formed of or includes an inorganic dielectric material, which may include, but is not limited to, silicon nitride, silicon oxide, oxynitride, silicon oxycarbide, or the like, combinations thereof, or multiple layers thereof. The material of passivation layer 62 may be the same as or different from the material of passivation layer 40. Deposition may be performed using a conformal deposition process such as high-density plasma chemical vapor deposition, atomic layer deposition, chemical vapor deposition, or the like. In some embodiments, passivation layer 62 may conform to the vertical and horizontal portions having the same thickness or substantially the same thickness (e.g., with a variation of less than approximately 20% or 10%). In various embodiments, a planarization process (such as a chemical mechanical polishing process or a mechanical polishing process) is performed to flatten the top surface of passivation layer 62. It should be understood that regardless of whether the passivation layer 62 is formed of the same material as the passivation layer 40, there may be a distinguishable interface, which may be visible, for example, in a transmission electron microscopy (TEM) image, an X-ray diffraction (XRD) image, or an electron backscatter diffraction (EBSD) image structure.

[0076] In various embodiments, the metal pad 56SR may be formed to have a step-like shape (e.g., a stair-step shape). For example, the step-like shape may include a lower step (e.g., the perforation portion 58SR) embedded in the passivation layer 40 and an upper step (e.g., the pad portion 60SR) embedded in the passivation layer 62. As discussed in more detail below, the step-like shape of the metal pad 56SR may have an outward direction toward the multiple post-singulation sidewalls of the device die 22 (as shown), an inward direction away from the multiple post-singulation sidewalls of the device die 22 (see FIG. 2 ), and a vertical direction (e.g., the vertical direction) away from the multiple post-singulation sidewalls of the device die 22. 7A to 7C ), or a hill step consisting of two lower steps and a higher step in the middle (see Figures 8A to 8C ).

[0077] During various subsequent processes, areas of the device die 22 near the metal pads 56SR of the seal ring 42 may experience high stress. Consequently, the passivation layer 62 in these areas may be susceptible to cracking, delamination, or other types of damage. Examples of such subsequent processes may include, but are not limited to, singulating the device die 22 from the wafer 24, bonding multiple package assemblies 20 to a carrier, bonding multiple other package assemblies to multiple package assemblies 20, testing completed or partially completed packages, and singulating completed or partially completed packages. Specifically, the stepped shape of the multiple metal pads 56SR reduces stress in these specific locations, compared to a U-shaped or bowl-shaped shape. For example, the stepped shape allows the material used to deposit the passivation layer 62 to fill the areas surrounding the multiple metal pads 56SR without voids. Additionally, the stepped shape reduces the amount of passivation layer 62 material that resides within the corners or crevices of the metal pads 56SR. This allows more of the passivation layer 62 material to adhere to the body of the passivation layer 62, reducing stress in these locations by up to approximately 60%.

[0078] Note that the various stepped shapes of metal pads 56SR differ from the plurality of metal pads 56 having a bowl or U shape in a cross-sectional view. The stress near the plurality of metal pads 56 tends to be lower than that of the metal pads 56SR. Therefore, the embodiment will be described with respect to forming the plurality of metal pads 56 into a bowl or U shape while the metal pads 56SR have a stepped shape.

[0079] According to various embodiments, the stepped shape of metal pad 56SR can have a number of dimensions as labeled and discussed herein. In some embodiments, the width W1 of the lower step can be in a range of 1.8 micrometers (μm) to 3.2 μm, and the width W2 of the upper step can be in a range of 1.8 μm to 7.0 μm. For example, widths W1 and W2 can be substantially the same or different within the aforementioned dimensions. The total width W3 of metal pad 56SR can be in a range of 3.6 μm to 10 μm. Additionally, the height H1 of the lower step can be in a range of 0.5 μm to 1.5 μm, the height H2 of the upper step above the lower step can be in a range of 0.5 μm to 1.5 μm, and the height H3 of the upper step above passivation layer 40 can be in a range of 1.4 μm to 2.8 μm. The total height H4 of metal pad 56SR can be in a range of 1.0 μm to 3.0 μm. However, any suitable dimensions may be utilized. Widths and heights less than these upper limits help reduce the amount of metal pad 56SR protruding into passivation layer 62, thereby achieving the aforementioned benefits. Widths and heights greater than these lower limits improve the effectiveness of seal ring 42 in protecting the multiple integrated circuit components disposed within device die 22.

[0080] Figure 6CA top view of device die 22 is shown. As shown, metal pad 56SR of seal ring 42 surrounds multiple metal pads 56 without interruption (e.g., as a full ring), although interruptions may be included according to other embodiments. Furthermore, metal pad 56SR includes perforated portion 58SR and pad portion 60SR. Note that the illustrated edges represent the multiple segmented sidewalls of chip 22.

[0081] 7A to 7C Another embodiment of the package assembly 20 is shown, wherein the metal pad 56SR has a stepped shape with an inward direction away from the plurality of segmented rear sidewalls of the device die 22. Figures 6A to 6C As described above, similar or similar dimensions can be used to achieve similar benefits. The illustrated embodiment can achieve the additional benefit of having the upper step (e.g., pad portion) of the metal pad 56SR further away from the plurality of segmented rear sidewalls. Thus, further stress reduction can be achieved. It should be understood that if the metal pad 56SR is very close to the plurality of metal pads 56, then Figures 6A to 6C As a result, less interference or parasitic capacitance can be achieved between metal pad 56SR and the plurality of metal pads 56 .

[0082] Figure 7C A top view of device die 22 is shown. As shown, metal pad 56SR of seal ring 42 surrounds multiple metal pads 56 without interruption (e.g., as a full ring), although interruptions may be included according to other embodiments. Furthermore, metal pad 56SR includes perforated portion 58SR and pad portion 60SR. Note that the illustrated edges represent the multiple segmented sidewalls of chip 22.

[0083] Figures 8A to 8C Another embodiment of the package assembly 20 is shown, wherein the metal pad 56SR has a stepped shape, wherein the metal pad 56SR has a stepped shape with a mountain-shaped step having a plurality of lower steps (e.g., a plurality of through-hole portions 58SR) on opposite sides of an upper step (e.g., a pad portion 60SR). As shown in the figure, the above-mentioned combination can be used. Figures 6A to 6C Similar benefits are achieved with similar dimensions as described.The illustrated embodiment may achieve additional benefits by having stronger attachment within the passivation layer 40, thereby further reducing the risk of delamination or other types of damage.

[0084] Figure 8CA top view of device die 22 is shown. As shown, metal pad 56SR of seal ring 42 surrounds multiple metal pads 56 without interruption (e.g., as a full ring), although interruptions may be included according to other embodiments. Furthermore, metal pad 56SR includes perforated portion 58SR and pad portion 60SR. Note that the illustrated edges represent the multiple segmented sidewalls of chip 22.

[0085] Figures 9 to 15 The diagram shows the subsequent steps of attaching multiple package components 20 to form a semiconductor package. Figures 6A to 6C However, it is also possible to use 7A to 7C and / or Figures 8A to 8C For example, in Figure 13 Multiple package assemblies 120 are attached to the package assembly 120, and the multiple package assemblies 120 may also include the sealing ring 42 described in any of the above embodiments. Thus, multiple package assemblies 20 and 120 may be attached to any combination of embodiments of the sealing ring 42. In addition, although a layer of multiple package assemblies 20 and a layer of multiple package assemblies 120 are shown and described, any suitable number of layers may be utilized. In addition, any suitable combination of embodiments of the sealing ring 42 may be utilized.

[0086] Figure 9 A carrier 70 including a bonding film 72 is shown provided thereon. The carrier 70 may be a semiconductor wafer such as a silicon wafer, and the bonding film 72 may be a bonding layer prepared for fusion bonding. In some embodiments, the bonding film 72 is a deposited layer formed above the top surface of the carrier 70. In other embodiments, the bonding film 72 is the portion of the carrier 70 used for fusion bonding. In some embodiments, the bonding film 72 comprises silicon (Si), silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0), or other suitable bonding materials.

[0087] A plurality of package components 20 are attached to a carrier 70. In some embodiments, the passivation layer 62 of the package component 20 is first covered with a bonding film 74. In some embodiments, the bonding film 74 comprises silicon (Si), silicon oxide (SiOx, where x>0), silicon nitride SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0), or other suitable bonding materials. In some embodiments, the bonding film 72 and the bonding film 74 comprise the same material, such as silicon oxide. In other embodiments, the bonding film 72 and the bonding film 74 comprise different materials. The plurality of package components 20 are then flipped over and placed on the carrier 70 so that the plurality of bonding films 74 are in contact with the bonding film 72. Specifically, the plurality of package components 20 are picked up and placed on the bonding film 72 in a side-by-side manner so that the plurality of package components 20 are arranged in an array and spaced apart from each other. In some embodiments, each package component 20 is placed on the top surface of the bonding film 72 so that the plurality of front sides of the plurality of package components 20 face the bonding film 72 of the carrier 70.

[0088] After picking up a plurality of package components 20 and placing them on the bonding film 72, a chip-to-wafer fusion bonding process may be performed to form a fusion bonding interface between the bonding film 72 and the bonding film 74. For example, the fusion bonding process of bonding the bonding film 72 and the bonding film 74 is performed at a temperature of about 100°C to about 290°C. The bonding film 72 may be directly bonded to the bonding film 74. In other words, no intermediate layer is formed between the bonding film 72 and the bonding film 74. The fusion bonding interface formed between the bonding film 72 and the bonding film 74 may be a Si-Si fusion bonding interface, a Si-SiOx fusion bonding interface, a SiOx-SiOx fusion bonding interface, a SiOx-SiNx fusion bonding interface, or other suitable fusion bonding interfaces.

[0089] Figure 10The diagram shows that after multiple package components 20 are bonded to carrier 70 via bonding film 72 and bonding films 74, a dielectric encapsulation layer 76 is formed over carrier 70 and covers the multiple package components 20. In some embodiments, dielectric encapsulation layer 76 is formed by an overmolding process or a film deposition process, such that a top surface portion of bonding film 72, multiple side surfaces of bonding film 74, and multiple backside surfaces and multiple side surfaces of the multiple package components 20 are encapsulated by dielectric encapsulation layer 76. In some embodiments, dielectric encapsulation layer 76 includes a molding compound, a molding underfill, a resin, a combination thereof, or the like. In some embodiments, dielectric encapsulation layer 76 includes a polymer material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof, or the like. In some embodiments, dielectric encapsulation layer 76 includes an insulating material such as silicon oxide, silicon nitride, or a combination thereof.

[0090] Figure 11 As shown, after the overmolding process or the film deposition process is performed, a grinding process or a planarization process may be performed to reduce the thickness of the dielectric packaging material 76 and the thickness of the plurality of package components 20 until the plurality of through-substrate vias 64 are exposed. In some embodiments, the grinding process includes a mechanical grinding process, a chemical mechanical grinding process, or a combination thereof.

[0091] In some embodiments, the thickness of the plurality of package components 20 is equal to the thickness of the dielectric packaging layer 76. In some embodiments, the dielectric packaging layer 76 contacts the plurality of side surfaces of the plurality of package components 20 and the plurality of bonding films 74, and the plurality of back surfaces of the plurality of semiconductor substrates 24 can be easily exposed through the thinned dielectric packaging layer 76. In other words, the top surface of the dielectric packaging layer 76 is substantially flush with the plurality of exposed surfaces of the plurality of package components 20 within process variations. However, the present invention is not limited thereto. In some embodiments, due to the polishing selectivity of the polishing process, the top surface of the dielectric packaging layer 76 may be slightly higher or slightly lower than the plurality of exposed surfaces of the plurality of package components 20.

[0092] Figure 12A redistribution layer structure 78 is shown formed over the backsides of the plurality of package components 20 and the exposed surface of the dielectric packaging layer 76. The redistribution layer structure 78 includes at least one polymer layer 80 and a plurality of conductive features 82 embedded in the polymer layer 80. The plurality of conductive features 82 include a plurality of metal pads, a plurality of metal lines, and / or a plurality of metal vias configured to electrically connect to various components. In some embodiments, the polymer layer 80 comprises a photosensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), combinations thereof, and the like. The polymer layer 80 of the redistribution layer structure 78 can be replaced with a dielectric layer or an insulating layer as desired. In some embodiments, the plurality of conductive features 82 can comprise Cu, Ti, Ta, W, Ru, Co, Ni, alloys thereof, combinations thereof, and the like. In some embodiments, a seed layer and / or a barrier layer can be disposed between each conductive feature 82 and the polymer layer 80. The seed layer can comprise Ti / Cu. The barrier layer may include Ta, TaN, Ti, TiN, CoW, combinations thereof, etc. The seed layer and the barrier layer may be considered part of the plurality of conductive features 82 .

[0093] In some embodiments, a bonding structure 84 is formed over the redistribution layer structure 78. In some examples, the bonding structure 84 is referred to as a "blanket bonding structure" because it is formed across multiple package components 20 and extends between and beyond the multiple package components 20. For example, the bonding structure 84 may include at least one bonding film 86 and a plurality of bonding metal features embedded in the bonding film 86. In some embodiments, the bonding film 86 comprises an insulating material, a dielectric material, a polymer material, or a combination thereof. For example, the bonding film 86 comprises silicon (Si), silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0), or other suitable adhesive materials. The bonding metal features may include Cu, Ti, Ta, W, Ru, Co, Ni, alloys thereof, combinations thereof, and the like. In some embodiments, a seed layer and / or a barrier layer may be disposed between each bonding metal feature and the bonding film 86. The seed layer may comprise Ti / Cu or any other suitable material. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or a combination thereof.The seed layer and the barrier layer may be considered part of the plurality of bonding metal features.

[0094] In some embodiments, the plurality of bonding metal components include a plurality of bonding pads 88P and a plurality of bonding through-holes 88V. The plurality of bonding pads 88P and the plurality of bonding through-holes 88V are configured to bond and electrically connect to the plurality of package components 20 below and the plurality of package components subsequently attached thereto. In some embodiments, the plurality of bonding through-holes 88V are in physical contact with the plurality of substrate through-holes 64 and the plurality of bonding pads 88P. In some embodiments, some bonding pads 88P are configured to bond to the plurality of package components 20 below and the plurality of package components attached thereto, but are electrically insulated from the plurality of package components 20 and the other package components. These plurality of such bonding pads 88P are referred to as "dummy bonding pads" or "floating bonding pads" in some examples because they are provided only to enhance the bonding strength between the plurality of package components.

[0095] Figure 13 The diagram shows a plurality of package components 120 (e.g., memory dies, logic dies, or other suitable dies) placed on a plurality of bonding structures 84. Although two package components 120 are shown attached to two package components 20, the number of package components 20, 120 is not limited to that shown. In some embodiments, the plurality of package components 120 corresponds to the plurality of package components 20 below. The plurality of package components 120 and the plurality of package components 20 can be chips of the same type or different types.

[0096] As shown, multiple package assemblies 120 can be similarly formed and include similar features as described above in conjunction with multiple package assemblies 20. Identical features may be labeled with the same number, but starting with "1" in the hundreds place. For example, similar to multiple package assemblies 20, multiple package assemblies 120 may include multiple integrated circuit devices 126 formed along the front side of semiconductor substrate 124, an interconnect structure 132 formed above the multiple integrated circuit devices 126, and a plurality of metal pads 156 formed above and electrically connected to the interconnect structure 132. The interconnect structure 132 includes a plurality of metal lines 134 and a plurality of through-vias 136. A plurality of seal rings 142 may be formed simultaneously with the interconnect structure 132 and the plurality of metal pads 156. For example, the seal rings 142 may include a plurality of metal lines 134SR, a plurality of through-vias 136SR, and a plurality of metal pads 156SR electrically connected to each other, similar to the plurality of metal lines 34SR, the plurality of through-vias 36S, and the plurality of metal pads 56SR of the multiple package assemblies 20. Thus, metal lines 134SR, vias 136SR, and metal pads 156SR collectively form seal ring 42 for package assembly 120. Furthermore, passivation layers 140 and 162 are disposed over and around metal pads 156, similar to passivation layers 40 and 62 of package assembly 20, respectively.

[0097] In some embodiments, a redistribution layer structure 178 can be disposed over the passivation layer 162 and electrically connected to the plurality of metal pads 156. The redistribution layer structure 178 can be similarly formed and include features similar to the redistribution layer structure 78 formed over the package component 20. For example, the redistribution layer structure 178 can include a plurality of conductive features 182 embedded in at least one polymer layer 180. The plurality of conductive features 182 include a plurality of metal pads, a plurality of metal lines, and / or a plurality of metal vias configured to be electrically connected to different components.

[0098] In addition, a bonding structure 184 may be provided above the plurality of metal pads 156 and above the redistribution layer structure 178 (if present). The bonding structure 184 may be electrically connected to the plurality of metal pads 156 directly, through a redistribution layer, or a combination thereof. The bonding structure 184 may be formed similarly to the bonding structure 84, such as as a blanket bonding structure formed above a wafer before singulating the individual plurality of package components 120. The bonding structure 184 may include a plurality of bonding metal features extending through at least one bonding film 186. The plurality of bonding metal features may include a plurality of bonding pads 188P and a plurality of bonding through-holes 188V. The plurality of bonding pads 188P and the plurality of bonding through-holes 188V are configured to bond and electrically connect to a plurality of electronic features below the plurality of package components 120. Some bonding pads 188P may be dummy bonding pads or floating bonding pads to enhance bonding strength with the bonding pads 88P along the plurality of package components 20.

[0099] In some embodiments, to facilitate chip-to-wafer direct bonding between bonding structure 84 and bonding structure 184, surface preparation is performed on the bonding surfaces of bonding structure 84 and bonding structure 184. Surface preparation can include, for example, surface cleaning and activation. Surface cleaning can be performed on the bonding surfaces of bonding structure 84 and bonding structure 184 to remove particles and / or native oxides on the bonding surfaces of individual bonding pads and bonding films. The bonding surfaces of bonding structure 84 and bonding structure 184 are cleaned, for example, by wet cleaning.

[0100] After cleaning the multiple bonding surfaces of the multiple bonding structures 84 and the bonding structure 184, activation of the multiple top surfaces can be performed to develop high bonding strength. In some embodiments, plasma activation is performed to treat and activate the multiple bonding surfaces of the multiple bonding films 86 and 186. When the bonding surface of the activated bonding film 86 contacts the bonding surface of the activated bonding film 186, the multiple bonding films 86 and 186 are pre-bonded. The bonding structure 184 and the bonding structure 84 are pre-bonded via the pre-bonding of the multiple bonding films 86 and 186. After the pre-bonding of the multiple bonding films 86 and 186, the multiple bonding pads 88P contact the multiple bonding pads 188P.

[0101] After the pre-bonding process of the plurality of bonding films 86 and 186, dielectric-to-dielectric and metal-to-metal direct bonding of the package component 120 having the bonding structure 84 is performed. The direct bonding of the package component 120 and the bonding structure 84 may include a process for dielectric bonding and a thermal annealing for metal bonding. The process for dielectric bonding is performed to strengthen the bonding between the plurality of bonding films 86 and 186. For example, the process for dielectric bonding may be performed at a temperature in the range of about 100°C to about 150°C. After the process for dielectric bonding is performed, thermal annealing for metal bonding is performed to promote bonding between the plurality of bonding pads 88P and 188P. For example, the thermal annealing for metal bonding may be performed at a temperature in the range of about 300°C to about 400°C. The process temperature of the thermal annealing for metal bonding is higher than the process temperature of the process for dielectric bonding. Since thermal annealing for metal bonding is performed at a relatively high temperature, metal diffusion and grain growth may occur at the bonding interfaces between the bonding pads 88P and 188P. Metal bonding is not limited to pad-to-pad bonding. Via-to-via bonding or via-to-pad bonding may be applied as needed.

[0102] Figure 14The figure shows that after bonding the plurality of package components 120 to the plurality of package components 20 via bonding structures 84 and 184, a dielectric encapsulation layer 176 is formed to cover the bonding structures 84 and the plurality of package components 120. In some embodiments, dielectric encapsulation layer 176 is formed by an overmolding process or a film deposition process, such that portions of the top surfaces of the bonding structures 84, the side surfaces of the plurality of bonding structures 184, and the backside surfaces and side surfaces of the plurality of package components 120 are encapsulated by dielectric encapsulation layer 176. In some embodiments, dielectric encapsulation layer 176 comprises a molding compound, a molding underfill, a resin, or a combination thereof. In some embodiments, dielectric encapsulation layer 176 comprises a polymer material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or a combination thereof. In some embodiments, dielectric encapsulation layer 76 comprises an insulating material such as silicon oxide, silicon nitride, or a combination thereof.

[0103] After the overmolding process or the film deposition process is performed, a polishing process or a planarization process may be performed to reduce the thickness of the packaging material and the thickness of the plurality of package components 120 until the plurality of backside surfaces of the plurality of package components 120 are exposed. In some embodiments, the polishing process includes a mechanical polishing process, a chemical mechanical polishing process, or a combination thereof.

[0104] Please still refer to Figure 14 , attached to a carrier 170 including a bonding film 172 thereon. The carrier 170 may be a glass wafer, and the bonding film 172 may be an adhesive material. The bonding film 172 may include an oxide layer, a die attach tape (DAF), or a suitable adhesive. The carrier 170 is bonded to the multiple backside surfaces of the multiple package components 120 and the exposed surface of the dielectric encapsulation layer 176 through the bonding film 172. In some embodiments (not specifically shown), a blanket bonding film may be provided between the bonding film 172 and the semiconductor substrate 224 and between the bonding film 172 and the dielectric encapsulation layer 176, and the bonding film 172 may be bonded to the blanket bonding film by fusion bonding.

[0105] Figure 15It is depicted that a de-bonding process may be performed to debond the bonding film 72 and the underlying carrier 70 from the plurality of bonding films 74 and the dielectric encapsulation layer 76. This debonding process may be a laser lift-off process or other suitable debonding process. After removing the bonding film 72 and the carrier 70, a polishing process may be performed to thin the plurality of bonding films 74 and the dielectric encapsulation layer 76. In some embodiments, the plurality of bonding films 74 may be removed to expose the passivation layer 62. During the removal of the plurality of bonding films 74, the dielectric encapsulation layer 76 may be thinned. In some embodiments, the removal of the plurality of bonding films 74 and the thinning of the dielectric encapsulation layer 76 may be performed by the same polishing process (e.g., a chemical mechanical polishing process). After the polishing process is performed, the plurality of package components 20 are exposed, but at this stage the plurality of metal pads 56 of the plurality of package components 20 are not exposed and are still covered by the passivation layer 62.

[0106] According to various embodiments, a patterning process of the passivation layer 62 is then performed, so that a plurality of openings are formed in the passivation layer 62 to expose the plurality of metal pads 56. In some embodiments, a rear passivation layer 90 is first formed to cover the dielectric packaging layer 76 and the passivation layer 62 of the plurality of package components 20, and a plurality of openings are formed through the rear passivation layer 90 and the passivation layer 62. In some embodiments, a photolithography and etching process is performed to form the plurality of openings. However, the present invention is not limited thereto. In other embodiments, a laser drilling process is performed to form the openings.

[0107] Figure 15 The formation of a plurality of electrical connectors 94 and a plurality of through-vias 92 is depicted. According to some embodiments, the formation process includes depositing a blanket metal seed layer (not shown) that extends into a plurality of openings in the back passivation layer 90 and the passivation layer 62, forming a patterned plating mask, and electroplating a conductive material into the plurality of openings in the plating mask. According to some embodiments, the metal seed layer includes a titanium layer and a copper layer above the titanium layer. Alternatively, the metal seed layer is a single copper layer. The plated conductive material may include copper, nickel, palladium, aluminum, lead-free solder, alloys thereof, and / or multiple layers thereof. The plating mask is then removed, followed by an etching process to remove portions of the metal seed layer not covered by the plated conductive material, thereby forming a plurality of through-vias 92V and a plurality of electrical connectors 94. For example, the plurality of electrical connectors 94 may include a plurality of metal pillars 92P and a plurality of solder regions 94. A reflow process is performed to reflow the plurality of solder regions 94. In some embodiments, the plurality of electrical connectors 94 may be a plurality of microbumps or a plurality of controlled collapse of chip connection (C4) bumps.

[0108] Embodiments of the present invention have several advantageous features. By forming seal rings 42 with multiple metal pads 56SR having a stepped shape, stress on device dies 22 near metal pads 56SR can be reduced. Furthermore, the quality of passivation layer 62 can be improved, resulting in greater manufacturing yield and improved performance of the resulting semiconductor package.

[0109] In one embodiment, a method includes: forming a plurality of active devices above a semiconductor substrate; forming an interconnect structure above the plurality of active devices, the interconnect structure including a first portion of a seal ring above the semiconductor substrate, the seal ring electrically insulated from the plurality of active devices; forming a first passivation layer above the interconnect structure; forming a first metal pad and a second metal pad extending through the first passivation layer and above the interconnect structure, the first metal pad having a spherical shape and the second metal pad having a stepped shape; and depositing a second passivation layer over the first and second metal pads. In other embodiments, the first metal pad is electrically connected to the plurality of active devices. In other embodiments, the second metal pad is the second portion of the seal ring. In other embodiments, the stepped shape of the second metal pad includes a lower step embedded in the first passivation layer and an upper step along a major surface of the first passivation layer. In other embodiments, the upper step is closer to the first metal pad than the lower step. In other embodiments, the lower step is closer to the first metal pad than the upper step. In other embodiments, the stepped shape of the second metal pad includes an additional lower step embedded in the first passivation layer, and the upper step is laterally interposed between the lower step and the additional lower step. In other embodiments, the semiconductor substrate comprises a wafer, and the method further comprises: attaching a carrier substrate to the second passivation layer; attaching a package assembly to the back side of the semiconductor substrate, the package assembly being electrically connected to the plurality of active devices; removing the carrier substrate; and forming an electronic connector over the second passivation layer and electrically connected to the first metal pad.

[0110] In one embodiment, a semiconductor device includes: a first package assembly including a first passivation layer; an electronic connector extending through the first passivation layer; a second passivation layer located above the first passivation layer; a first metal pad and a second metal pad embedded in the first passivation layer and the second passivation layer, the first metal pad comprising a first U-shaped shape and the second metal pad having a first stepped shape; a first plurality of dielectric layers located above the second passivation layer; a first plurality of metallization layers and a second plurality of metallization layers embedded in the first plurality of dielectric layers, the second metal pad and the second plurality of metallization layers being electrically connected to the first metal pad and the first plurality of metallization layers; and an active device located above the first plurality of metallization layers and electrically connected to the first plurality of metallization layers. In other embodiments, the first metal pad is electrically connected to the electronic connector. In other embodiments, the first stepped shape of the second metal pad comprises a first step and a second step, wherein the first step is embedded in the first passivation layer and the second passivation layer, and wherein the second step is embedded in the second passivation layer. In other embodiments, the present invention further includes a second package component, the second package component comprising: a bonding film attaching the second package component to the first package component; a bonding pad embedded in the bonding film; a third passivation layer located above the bonding film; a fourth passivation layer located above the third passivation layer; a third metal pad and a fourth metal pad embedded in the third and fourth passivation layers, the third metal pad comprising a second U-shape and the fourth metal pad having a second stepped shape; a second plurality of dielectric layers located above the fourth passivation layer; and a third plurality of metallization layers and a fourth plurality of metallization layers embedded in the second plurality of dielectric layers, the fourth metal pad and the fourth plurality of metallization layers being electrically isolated from the third metal pad and the third plurality of metallization layers. In other embodiments, the first stepped shape and the second stepped shape have the same orientation. In other embodiments, the first stepped shape and the second stepped shape have different orientations.

[0111] In one embodiment, a semiconductor device includes: an active device formed along a front side of a semiconductor substrate; a first plurality of dielectric layers located above the semiconductor substrate; a first plurality of metallization layers located within the first plurality of dielectric layers, the first plurality of metallization layers forming an interconnect structure; a second plurality of metallization layers located within the first plurality of dielectric layers, the second plurality of metallization layers forming a ring surrounding the first plurality of metallization layers; a first metal pad located above and electrically connected to the first plurality of metallization layers, wherein, in a cross-sectional view, the first metal pad comprises a U-shape having a left arm and a right arm; and a second metal pad. , which is located above and electrically connected to the second plurality of metallization layers, the second metal pad forming a ring around the first metal pad, and in a cross-sectional view, the second metal pad includes a left portion adjacent to the left arm and a right portion adjacent to the right arm, the left portion having a first stepped shape, the right portion having a second stepped shape, the first stepped shape being a reflection of the second stepped shape, and the U-shaped shape being different from the first stepped shape and the second stepped shape; and a second plurality of dielectric layers located above the first plurality of dielectric layers and encapsulating the first and second metal pads. In other embodiments, the first stepped shape of the left portion has the same orientation as the left arm of the U-shape, and the second stepped shape of the right portion has the same orientation as the right arm of the U-shape. In other embodiments, the first stepped shape of the left portion has the same orientation as the right arm of the U-shape, and the second stepped shape of the right portion has the same orientation as the left arm of the U-shape. In other embodiments, each of the first stepped shape and the second stepped shape is a mountain-shaped step. In other embodiments, the device further includes an electronic connector located above and extending through the second plurality of dielectric layers, wherein the electronic connector is electrically connected to the first metal pad. In other embodiments, the device further includes: a through-via extending from the front side to the back side of the semiconductor substrate; and an integrated circuit die attached to the semiconductor substrate and electrically connected to the through-via.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device comprising a seal ring structure, characterized in that: include: A first packaging component includes a first passivation layer; an electronic connector extending through the first passivation layer; a second passivation layer located above the first passivation layer; A first metal pad and a second metal pad embedded in the first passivation layer and the second passivation layer, the first metal pad comprising a first U-shape, and the second metal pad comprising a first stepped shape; a first plurality of dielectric layers overlying the second passivation layer; a first plurality of metallization layers and a second plurality of metallization layers embedded in the first plurality of dielectric layers, the second metal pad and the second plurality of metallization layers being electrically connected to the first metal pad and the first plurality of metallization layers; as well as Active devices are located above and electrically connected to the first plurality of metallization layers.

2. The semiconductor device comprising a seal ring structure according to claim 1, wherein: The first stepped shape of the second metal pad includes a first step and a second step, wherein the first step is embedded in the first passivation layer and the second passivation layer, and wherein the second step is embedded in the second passivation layer.

3. The semiconductor device comprising a seal ring structure according to claim 1, wherein: Further comprising a second packaging component, the second packaging component comprising: a bonding film that attaches the second packaging component to the first packaging component; a bonding pad embedded in the bonding film; a third passivation layer located above the bonding film; a fourth passivation layer, located above the third passivation layer; a third metal pad and a fourth metal pad embedded in the third passivation layer and the fourth passivation layer, the third metal pad comprising a second U-shape, and the fourth metal pad having a second stepped shape; a second plurality of dielectric layers overlying the fourth passivation layer; and A third plurality of metallization layers and a fourth plurality of metallization layers are embedded in the second plurality of dielectric layers, the fourth metal pad and the fourth plurality of metallization layers being electrically isolated from the third metal pad and the third plurality of metallization layers.

4. The semiconductor device comprising a seal ring structure according to claim 3, wherein: The first stepped shape and the second stepped shape have the same direction.

5. The semiconductor device comprising a seal ring structure according to claim 3, wherein: The first stepped shape and the second stepped shape have different directions.

6. A semiconductor device comprising a seal ring structure, characterized in that: include: active devices formed along the front side of the semiconductor substrate; a first plurality of dielectric layers overlying the semiconductor substrate; a first plurality of metallization layers within the first plurality of dielectric layers, the first plurality of metallization layers forming an interconnect structure; a second plurality of metallization layers within the first plurality of dielectric layers, the second plurality of metallization layers forming a ring around the first plurality of metallization layers; a first metal pad positioned above and electrically connected to the first plurality of metallization layers, wherein in cross-sectional view, the first metal pad comprises a U-shape having a left arm and a right arm; a second metal pad located above and electrically connected to the second plurality of metallization layers, the second metal pad forming a ring surrounding the first metal pad, wherein in a cross-sectional view, the second metal pad includes a left portion adjacent to the left arm and a right portion adjacent to the right arm, the left portion having a first stepped shape, the right portion having a second stepped shape, the first stepped shape being a reflection of the second stepped shape, and the U-shaped shape being different from the first stepped shape and the second stepped shape; as well as A second plurality of dielectric layers is located above the first plurality of dielectric layers and encapsulates the first metal pad and the second metal pad.

7. The semiconductor device comprising a seal ring structure according to claim 6, wherein: Wherein the first stepped shape of the left portion has the same orientation as the left arm of the U-shape, and wherein the second stepped shape of the right portion has the same orientation as the right arm of the U-shape.

8. The semiconductor device comprising a seal ring structure according to claim 6, wherein: Wherein the first stepped shape of the left portion has the same orientation as the right arm of the U-shape, and wherein the second stepped shape of the right portion has the same orientation as the left arm of the U-shape.

9. The semiconductor device comprising a seal ring structure according to claim 6, wherein: Each of the first stepped shape and the second stepped shape is a mountain-shaped step.

10. The semiconductor device comprising a seal ring structure according to claim 6, wherein: Further included is an electronic connector located above and extending through the second plurality of dielectric layers, wherein the electronic connector is electrically connected to the first metal pad.

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