Package structure
By introducing a combined structure of multi-layer heat conducting parts and heat dissipation parts into the chip package structure, the problem of poor heat dissipation effect of PoP packaging is solved, efficient chip heat dissipation is achieved, and the temperature of the packaging structure is reduced.
Patent Information
- Application Number
- CN202422016117.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2025-08-29
- Estimated Expiration
- 2034-08-19
AI Technical Summary
The chip stacking of PoP packages results in poor heat dissipation effects, making it difficult to meet the heat dissipation needs of high-integration chips.
The combined structure of a multi-layer heat conducting member and a heat dissipation member is adopted, including a first heat dissipation member, a first heat conducting member, a storage chip, a processing chip, a substrate, a second heat conducting member and a second heat dissipation member. The third heat conducting member is provided through the through hole to achieve multi-layer transfer of heat and direct heat dissipation.
It improves the heat dissipation efficiency of the packaging structure, reduces the junction temperature of the packaging structure, and solves the heat dissipation problem of high-integration chips.
Smart Images
Figure CN223284977U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip packaging technology, and in particular to a packaging structure. Background Art
[0002] With the growing demand for heterogeneous computing power and intelligent computing power in the downstream market, as well as the large-scale development of Android native applications such as cloud games, more and more manufacturers are beginning to apply ARM architecture to the server field.
[0003] The ARM-based SoC (System on Chip) array server is an innovative heterogeneous server. SoC array server designs utilize a large number of chips in a stacked package called PoP (Package on Package). A PoP package is a highly integrated package typically constructed by stacking two or more BGA (Ball Grid Array) packages. Solder ball arrays interconnect the lower package with the upper package and the PCB substrate. While PoP packaging technology saves space and increases chip density, the stacking of chips reduces the heat dissipation performance of the PoP package. Utility Model Content
[0004] In order to solve the above technical problems, the present application provides a packaging structure.
[0005] The present application provides a packaging structure, which includes: a first heat sink, a first heat conductor, a memory chip, a processing chip, a substrate, a second heat conductor and a second heat sink stacked in sequence, and a plurality of through holes are provided on the substrate in the direction from the first heat sink to the second heat sink, and a third heat conductor is provided in the through holes, and the third heat conductor is connected to both the processing chip and the second heat conductor.
[0006] The technical solution provided by the embodiments of the present application has the following advantages over the prior art: by providing a first heat conductor and a first heat sink on one side of the memory chip, and providing a second heat conductor and a second heat sink on one side of the substrate, the first heat conductor can transfer heat from the memory chip to the first heat sink, which can dissipate heat from the memory chip, and the second heat conductor can transfer heat from the substrate to the second heat sink, which can dissipate heat from the substrate, thereby improving the heat dissipation effect of the packaging structure. In addition, by providing a through hole in the substrate and arranging a third heat conductor within the through hole, the second heat sink can directly dissipate heat from the processing chip through the third heat conductor, further improving the heat dissipation efficiency of the packaging structure.
[0007] In one possible implementation, the packaging structure also includes a first solder ball array and a first thermally conductive filler, the first solder ball array includes a plurality of first solder balls arranged at intervals, the first thermally conductive filler is arranged between two adjacent first solder balls, and the storage chip is connected to the processing chip through the first solder ball array and the first thermally conductive filler.
[0008] In a possible implementation, the orthographic projection of the memory chip on the plane where the first thermally conductive filling member is located is located within the outline of the first thermally conductive filling member.
[0009] In one possible implementation, the packaging structure also includes a second solder ball array, the second solder ball array includes a plurality of second solder balls arranged at intervals, the memory chip is connected to the substrate through the second solder ball array, the second solder balls are opposite to the through holes, and the third heat conductor is connected to the second solder balls.
[0010] In one possible implementation, the packaging structure further includes a second thermally conductive filler, which is disposed between two adjacent second solder balls. The memory chip is connected to the substrate via the second solder ball array and the second thermally conductive filler.
[0011] In a possible implementation, the orthographic projection of the processing chip on the plane where the second thermally conductive filling member is located is located within the outline of the second thermally conductive filling member.
[0012] In a possible implementation manner, the hole wall of the through hole is covered with a fourth heat conducting member.
[0013] In a possible implementation manner, the third heat conducting member abuts against the hole wall of the through hole.
[0014] In a possible implementation, a material of at least one of the third heat conducting member and the fourth heat conducting member includes copper.
[0015] In one possible implementation, the packaging structure further includes a heat conducting plate, and the first heat dissipating element is connected to the heat conducting plate; and / or the second heat dissipating element is connected to the heat conducting plate. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0018] Figure 1 Schematic diagram of the packaging structure provided for some embodiments of the present application.
[0019] Reference numerals:
[0020] 100. Packaging structure; 1. First heat sink; 2. First thermal conductor; 3. Memory chip; 31. First solder ball array; 311. First solder ball; 4. Processing chip; 41. Second solder ball array; 411. Second solder ball; 5. Substrate; 51. Through hole; 511. Fourth thermal conductor; 52. Third thermal conductor; 6. Second thermal conductor; 7. Second heat sink; 8. First thermally conductive filling member; 9. Second thermally conductive filling member. DETAILED DESCRIPTION
[0021] In order to more clearly understand the above-mentioned objectives, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.
[0022] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application can also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present application, not all of the embodiments.
[0023] See also Figure 1 , Figure 1 Schematic diagram of a package structure provided in some embodiments of the present application. Embodiments of the present application provide a package structure 100. The package structure 100 of the present application can be applied to fields such as cloud computing, the Internet of Things, intelligent transportation, and healthcare that utilize PoP packaged chips.
[0024] The package structure 100 includes a first heat sink 1, a first heat conductor 2, a memory chip 3, a processing chip 4, a substrate 5, a second heat conductor 6, and a second heat sink 7, which are stacked in sequence. The shapes and sizes of the first heat sink 1 and the second heat sink 7 can be determined based on the heat dissipation requirements of the package structure 100.
[0025] Specifically, in the height direction of the packaging structure 100, the first heat sink 1, the first heat conductor 2, the memory chip 3, the processing chip 4, the substrate 5, the second heat conductor 6, and the second heat sink 7 are stacked in sequence. The first heat conductor 2 is connected to the memory chip, so the first heat conductor 2 can transfer the heat generated by the memory chip 3 to the first heat sink 1, thereby dissipating the heat of the memory chip 3 through the first heat sink 1. The second heat conductor 6 is connected to the substrate 5, so the second heat conductor 6 can transfer the heat generated by the substrate 5 to the second heat sink 7, thereby dissipating the heat of the substrate 5 through the second heat sink 7. Thus, the memory chip 3 and the processing chip 4 can be dissipated through the first heat sink 1 and the second heat sink 7, thereby improving the heat dissipation effect of the packaging structure 100.
[0026] For example, the substrate 5 may be a PCB (Printed Circuit Board) substrate. The PCB substrate may be formed by combining multiple copper layers and multiple FR4 layers. The shape and size of the substrate 5 may be determined by the design requirements of the server product.
[0027] In the direction from the first heat sink 1 to the second heat sink 7, the substrate 5 may be provided with multiple through-holes 51. A third heat conducting member 52 may be disposed within each through-hole 51. Specifically, the multiple through-holes 51 may be spaced apart on the substrate 5 and extend through the substrate 5 in the thickness direction. There may be multiple third heat conducting members 52, and one through-hole 51 may be provided within the third heat conducting member 52. The shape and size of the through-holes 51 may be determined by the heat dissipation requirements of the package structure 100.
[0028] The third heat conducting member 52 is connected to both the processing chip 4 and the second heat conducting member 6. Thus, the heat generated by the processing chip 4 can be directly transferred to the second heat conducting member 6 through the third heat conducting member 52, and then dissipated from the processing chip 4 through the second heat dissipating member 7. This allows the processing chip 4 to be directly dissipated without passing through the substrate 5, thereby improving the heat dissipation effect of the package structure 100.
[0029] According to the package structure 100 of the embodiment of the present application, by providing a first heat conductor 2 and a first heat sink 1 on one side of the memory chip 3, and providing a second heat conductor 6 and a second heat sink 7 on one side of the substrate 5, the first heat conductor 2 can transfer heat from the memory chip 3 to the first heat sink 1, and the first heat sink 1 can dissipate heat from the memory chip 3. The second heat conductor 6 can transfer heat from the substrate 5 to the second heat sink 7, and the second heat sink 7 can dissipate heat from the substrate 5, thereby facilitating improved heat dissipation of the package structure 100. In addition, by providing a through hole 51 in the substrate 5 and disposing a third heat conductor 52 within the through hole 51, the second heat sink 7 can directly dissipate heat from the processing chip 4 through the third heat conductor 52, thereby further improving the heat dissipation efficiency of the package structure 100.
[0030] Please continue reading Figure 1 In some embodiments, the packaging structure 100 may further include a first solder ball array 31 and a first thermally conductive filler 8. The first solder ball array 31 may include a plurality of first solder balls 311 spaced apart. The first thermally conductive filler 8 may be disposed between two adjacent first solder balls 311. The memory chip 3 is connected to the processing chip 4 through the first solder ball array 31 and the first thermally conductive filler 8. Specifically, the gap between the two adjacent first solder balls 311 is filled with the first thermally conductive filler 8, one end of the first thermally conductive filler 8 is connected to the memory chip 3, and the other end is connected to the processing chip 4. The first thermally conductive filler 8 has viscosity, elasticity, and high thermal conductivity.
[0031] Thus, by filling the gap between the memory chip 3 and the processing chip 4 with the first thermally conductive filler 8 and utilizing its excellent thermal conductivity, the thermal resistance from the processing chip 4 to the first heat sink 1 can be reduced, thereby preventing the memory chip 3 from conducting heat through the air. At the same time, a portion of the heat generated by the processing chip 4 can be dissipated through the first thermally conductive filler 8, the memory chip 3, the first thermally conductive member 2, and finally the first heat sink 1, thereby improving the heat dissipation efficiency of the package structure 100.
[0032] Please continue reading Figure 1 In some embodiments, the orthographic projection of the memory chip 3 on the plane where the first thermally conductive filler 8 is located is located within the outline of the first thermally conductive filler 8. Specifically, the orthographic projection of the memory chip 3 on the plane where the first thermally conductive filler 8 is located can overlap with the first thermally conductive filler 8, or the orthographic projection of the outer outline of the memory chip 3 on the plane where the first thermally conductive filler 8 is located can be smaller than the outer outline of the first thermally conductive filler 8. As a result, the first thermally conductive member 2 can completely cover the memory chip 3, allowing the first thermally conductive filler 8 to better conduct heat to the memory chip 3 and the processing chip 4, thereby improving the heat dissipation efficiency of the packaging structure 100.
[0033] Please continue reading Figure 1 In some embodiments, the package structure 100 may further include a second solder ball array 41. The second solder ball array 41 may include a plurality of second solder balls 411 spaced apart. The memory chip 3 may be connected to the substrate 5 through the second solder ball array 41, and the second solder balls 411 are directly opposite to the through-holes 51. The third heat conductor 52 is connected to the second solder balls 411. The third heat conductor 52 may be connected to the second solder balls 411 through a solder pad. Thus, the heat generated by the processing chip 4 may pass through the second solder balls 411, the third heat conductor 52, the second heat conductor 6, and finally be dissipated through the second heat sink 7, thereby reducing the thermal resistance from the processing chip 4 to the second heat sink 7.
[0034] Please continue reading Figure 1 In some embodiments, the package structure 100 may further include a second thermally conductive filler 9. The second thermally conductive filler 9 is disposed between two adjacent second solder balls 411. The memory chip 3 may be connected to the substrate 5 via the second solder ball array 41 and the second thermally conductive filler 9. Specifically, the gap between the two adjacent second solder balls 411 is filled with the second thermally conductive filler 9. One end of the second thermally conductive filler 9 is connected to the substrate 5, and the other end is connected to the processing chip 4. The second thermally conductive filler 9 is viscous, elastic, and has high thermal conductivity.
[0035] Therefore, by filling the second thermally conductive filler 9 in the gap between the substrate 5 and the processing chip 4, and utilizing the good thermal conductivity of the second thermally conductive filler 9, the thermal resistance from the processing chip 4 to the substrate 5 can be reduced, thereby avoiding the processing chip 4 from conducting heat through the air, which is beneficial to improving the heat dissipation efficiency of the packaging structure 100.
[0036] Please continue reading Figure 1 In some embodiments, the orthographic projection of the processing chip 4 on the plane where the second thermally conductive filler 9 is located is located within the outline of the second thermally conductive filler 9. Specifically, the orthographic projection of the processing chip 4 on the plane where the second thermally conductive filler 9 is located can overlap with the second thermally conductive filler 9, or the orthographic projection of the outer outline of the processing chip 4 on the plane where the second thermally conductive filler 9 is located can be smaller than the outer outline of the second thermally conductive filler 9. As a result, the second thermally conductive member 6 can completely cover the processing chip 4, allowing the second thermally conductive filler 9 to better conduct heat to the processing chip 4, thereby improving the heat dissipation efficiency of the packaging structure 100.
[0037] In the related art, the total power consumption of the package structure is 9W, the size of the heat sink is 140×90×10mm, and the thermal conductivity of the thermal conductive material can be 10W / mK. Among them, the junction temperature of the package structure is 88.7°C.
[0038] For example, the total power consumption of the package structure 100 can be 9W, the size of the first heat sink 1 can be 140×90×10mm, the thermal conductivity of the first heat conductor 2 can be 10W / mK, the substrate 5 can be provided with 325 through holes 51, the size of the through hole 51 can be 0.089×0.089mm, the size of the second heat sink 7 can be 140×90×10mm, and the thermal conductivity of the second heat conductor 6 can be 10W / mK. Among them, the junction temperature of the package structure 100 is 80°C. It can be seen that the package structure 100 in the present application is conducive to reducing the junction-to-shell thermal resistance and junction-to-plate thermal resistance of the package structure 100, and the application of the through hole 51 to reduce the intra-board thermal resistance of the substrate 5, thereby achieving rapid cooling of both sides of the package structure 100, and the junction temperature of the package structure 100 is reduced by 8.7°C, which can effectively solve the heat dissipation problem of the high-power package structure 100.
[0039] Please continue reading Figure 1 In some embodiments, the through hole 51 is covered with a fourth heat conducting member 511. Thus, the processing chip 4 can also transfer heat to the second heat sink 7 through the fourth heat conducting member 511, thereby improving the heat dissipation efficiency of the processing chip 4.
[0040] Please continue reading Figure 1In some embodiments, the third heat conducting member 52 abuts against the wall of the through hole 51. Specifically, the third heat conducting member 52 completely fills the through hole 51. Thus, heat can be conducted to the processing chip 4 through the through hole 51 and the third heat conducting member 52, thereby improving the thermal conductivity of the substrate 5 and rapidly transferring a portion of the heat from the processing chip 4 to the second heat sink 7, which can then be quickly dissipated to the external environment.
[0041] Please continue reading Figure 1 In some embodiments, at least one of the third heat conductor 52 and the fourth heat conductor 511 is made of copper. Specifically, the third heat conductor 52 may be made of copper, the fourth heat conductor 511 may be made of copper, or both the third heat conductor 52 and the fourth heat conductor 511 may be made of copper. Since copper has a thermal conductivity of 385 W / mK, this helps improve the thermal conductivity of the substrate 5 and, in turn, the heat dissipation capability of the package structure 100.
[0042] Please continue reading Figure 1 In some embodiments, the package structure 100 may further include a thermally conductive plate, with the first heat sink 1 connected to the thermally conductive plate, and / or the second heat sink 7 connected to the thermally conductive plate. Specifically, the thermally conductive plate may be connected only to the first heat sink 1, or to the second heat sink 7, or both the first heat sink 1 and the second heat sink 7. This allows heat to be dissipated through the thermally conductive plate, thereby improving the heat dissipation capability of the package structure 100 and, in turn, enhancing the performance and power support of the package structure 100.
[0043] It should be noted that, in the description of the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. Among them, "fixed connection" means that the two are connected to each other and the relative position relationship after connection remains unchanged. In addition, the directional terms mentioned in the embodiments of the present application, such as "inside" and "outside", etc., are only reference to the directions of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.
[0044] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand and implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments described herein, but is intended to conform to the broadest scope consistent with the principles and novel features of the present application.
Claims
1. A packaging structure, characterized in that: The packaging structure includes: a first heat sink, a first heat conductor, a memory chip, a processing chip, a substrate, a second heat conductor and a second heat sink stacked in sequence; a plurality of through holes are provided on the substrate in the direction from the first heat sink to the second heat sink, a third heat conductor is provided in the through holes, and the third heat conductor is connected to both the processing chip and the second heat conductor.
2. The packaging structure according to claim 1, wherein: The packaging structure also includes a first solder ball array and a first thermally conductive filler. The first solder ball array includes a plurality of first solder balls arranged at intervals. The first thermally conductive filler is arranged between two adjacent first solder balls. The storage chip is connected to the processing chip through the first solder ball array and the first thermally conductive filler.
3. The packaging structure according to claim 2, wherein: The orthographic projection of the memory chip on the plane where the first thermally conductive filling member is located is located within the outline of the first thermally conductive filling member.
4. The packaging structure according to claim 1, wherein: The packaging structure also includes a second solder ball array, which includes a plurality of second solder balls arranged at intervals. The memory chip is connected to the substrate through the second solder ball array. The second solder balls are opposite to the through holes, and the third heat conductor is connected to the second solder balls.
5. The packaging structure according to claim 4, wherein: The packaging structure further includes a second thermally conductive filler, which is disposed between two adjacent second solder balls. The memory chip is connected to the substrate via the second solder ball array and the second thermally conductive filler.
6. The packaging structure according to claim 5, wherein: The orthographic projection of the processing chip on the plane where the second thermally conductive filling member is located is located within the outline of the second thermally conductive filling member.
7. The packaging structure according to claim 1, wherein: The hole wall of the through hole is covered with a fourth heat conducting member.
8. The packaging structure according to claim 7, wherein: The third heat conducting member abuts against the hole wall of the through hole.
9. The packaging structure according to claim 7, wherein: A material of at least one of the third heat conductor and the fourth heat conductor includes copper.
10. The packaging structure according to claim 1, wherein: The packaging structure further includes a heat conducting plate, and the first heat dissipating element is connected to the heat conducting plate; and / or the second heat dissipating element is connected to the heat conducting plate.