Driving circuit, converter and electronic equipment

Abstract

The utility model relates to the technical field of power electronics, in particular to a driving circuit, a converter and electronic equipment. The driving circuit comprises two driving units, each driving unit is configured to drive one power tube, each driving unit comprises a first input end and a second input end, the first input end of one driving unit and the second input end of the other driving unit are configured to input a first control signal, and the second input end of the other driving unit is configured to input a second control signal. Wherein the second input end of one driving unit and the first input end of the other driving unit are configured to input a second control signal, when the level of the first control signal is complementary with the second control signal, the driving unit drives the power tube to be complementarily conducted, and when the level of the first control signal is the same as the second control signal, the driving unit drives the power tube to be complementarily conducted. The driving unit drives the power tubes to be disconnected simultaneously. Therefore, no matter what level the two control signals input to the drive circuit are, the two power tubes needing to be complementarily conducted cannot be directly connected, and short circuit can be avoided.

Description

Technical Field

[0001] The utility model relates to the field of power electronics technology, and in particular to a drive circuit, a converter and an electronic device. Background Art

[0002] Power electronic converters are now developing towards high power, high power factor and high efficiency. Different circuit topologies are formed through different combinations of semiconductor devices, and energy transfer and conversion between AC (alternating current) and DC (direct current) are achieved by controlling the opening and closing of power tubes in the topology.

[0003] Typical converters utilize a bridge-type converter circuit, where a drive signal controls the complementary switching of power transistors within the bridge-type converter circuit to achieve input / output current conversion. In bridge-type converter circuits, such as full-bridge or half-bridge converters, the drive signal causes the power transistors in the upper and lower arms to change their switching states according to a specific control strategy. When the upper arm's power transistor is on, the lower arm's power transistor is off, causing the load current to flow from the upper arm to the load. When the lower arm's switch is on, the upper arm's switch is off, causing the load current to flow from the load to the lower arm. By continuously switching the switching states, load current can be controlled. Simultaneously turning on the upper and lower arm's power transistors can cause a short circuit, potentially damaging the power transistors. Therefore, to prevent simultaneous turning on of the upper and lower arm's power transistors, the drive signal for the upper arm's power transistor is typically complementary to the drive signal for the lower arm's power transistor. However, high-frequency drive signals are susceptible to interference, and an interfered drive signal can cause the upper and lower arm's power transistors to turn on directly, resulting in a short circuit. Utility Model Content

[0004] One purpose of this embodiment is to provide a drive circuit, a converter, and an electronic device to solve the technical problem in the prior art that power transistors that need to be complementary turned on are turned on at the same time.

[0005] In a first aspect, an embodiment of the present invention provides a driving circuit, comprising two driving units, each of the driving units being configured to drive a power tube, each of the driving units comprising a first input end and a second input end, wherein the first input end of one of the driving units and the second input end of the other driving unit are configured to input a first control signal, and the second input end of one of the driving units and the first input end of the other driving unit are configured to input a second control signal, when the level of the first control signal is complementary to the second control signal, the driving unit drives the power tubes to be complementary and turned on, and when the level of the first control signal is the same as the second control signal, the driving unit drives the power tubes to be disconnected simultaneously.

[0006] Optionally, the driving unit further includes:

[0007] an input signal conditioning circuit electrically connected to the first input terminal and the second input terminal, configured to condition the control signals input from the first input terminal and the second input terminal and output a first input conditioning signal and a second input conditioning signal respectively;

[0008] a driver chip, electrically connected to the input signal conditioning circuit, and configured to output a driving signal in response to the first input conditioning signal and the second input conditioning signal;

[0009] The output signal conditioning circuit is electrically connected to the driver chip and is configured to be electrically connected to the power tube, and is used for conditioning the drive signal and outputting the conditioned drive signal to the power tube.

[0010] Optionally, the input signal conditioning circuit includes:

[0011] a first signal conditioning unit, electrically connected to the first input terminal and the driver chip, for conditioning the control signal input from the first input terminal and outputting a first input conditioning signal to the driver chip;

[0012] The second signal conditioning unit is electrically connected to the second input terminal and the driver chip respectively, and is used for conditioning the control signal input from the second input terminal and outputting a second input conditioning signal to the driver chip.

[0013] Optionally, the first signal conditioning unit includes:

[0014] a first filtering circuit, electrically connected to the first input terminal and the driver chip, for filtering the control signal input from the first input terminal and outputting a first input conditioning signal;

[0015] The first pull-down circuit is electrically connected to the first filter circuit and the driver chip respectively, and is used for performing pull-down processing on the first input conditioned signal and then outputting the signal to the driver chip.

[0016] Optionally, the second signal conditioning unit includes:

[0017] a second filtering circuit, electrically connected to the second input terminal and the driver chip, for filtering the control signal input from the second input terminal and outputting a second input conditioning signal;

[0018] The second pull-down circuit is electrically connected to the second filter circuit and the driver chip respectively, and is used for performing pull-down processing on the second input conditioned signal and then outputting the signal to the driver chip.

[0019] Optionally, the output signal conditioning circuit includes:

[0020] a time adjustment circuit, electrically connected to the driver chip, for adjusting the rise time and fall time of the drive signal;

[0021] The speed adjustment circuit is configured to be electrically connected to the time adjustment circuit and the power tube respectively, and is used to adjust the rising speed and falling speed of the driving signal.

[0022] Optionally, the driving unit further includes a first voltage stabilizing circuit;

[0023] The first voltage stabilizing circuit is configured to be electrically connected to the power supply and the driver chip respectively, and is used to stabilize the power supply and then provide the power supply to the driver chip.

[0024] Optionally, the driving unit further includes a second voltage stabilizing circuit;

[0025] The second voltage stabilizing circuit is configured to be electrically connected to the positive driving power supply and the driving chip respectively, and is used to stabilize the positive driving power supply and then provide the voltage to the driving chip.

[0026] Optionally, the driving unit further includes a third voltage stabilizing circuit;

[0027] The third voltage stabilizing circuit is configured to be electrically connected to the negative driving power supply and the driving chip respectively, and is used to stabilize the negative driving power supply and then provide it to the driving chip.

[0028] Optionally, the driving unit further includes a voltage clamping circuit;

[0029] The voltage clamping circuit is configured to be electrically connected to the output signal conditioning circuit and the power tube respectively, and is used to clamp the conditioned driving signal.

[0030] Optionally, the driving unit further includes an oscillation suppression circuit;

[0031] The oscillation suppression circuit is configured to be electrically connected to the output signal conditioning circuit and the power tube respectively, and is used to suppress high-frequency parasitic oscillation.

[0032] Optionally, the driving unit further includes an anti-interference circuit;

[0033] The anti-interference circuit is configured to be electrically connected to the output signal conditioning circuit and the power tube respectively, so as to prevent the power tube from being mis-conducted.

[0034] In a second aspect, an embodiment of the present invention provides a converter, comprising the driving circuit as described above.

[0035] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the converter as described above.

[0036] Compared with the prior art, the embodiments of the present invention provide a drive circuit, a converter, and an electronic device. The drive circuit includes two drive units, each drive unit is configured to drive a power tube, and each drive unit includes a first input terminal and a second input terminal. The first input terminal of one drive unit and the second input terminal of the other drive unit are configured to input a first control signal, and the second input terminal of one drive unit and the first input terminal of the other drive unit are configured to input a second control signal. When the level of the first control signal is complementary to the second control signal, the drive unit drives the power tubes to be complementary and conductive. When the level of the first control signal is the same as the second control signal, the drive unit drives the power tubes to be simultaneously disconnected. Therefore, no matter what level the two control signals input to the drive circuit are, the two power tubes that need to be complementary and conductive will not be directly turned on. Interlocked drive is achieved in hardware, thereby avoiding short circuits, thereby improving circuit reliability, and ensuring drive safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0038] Figure 1 A schematic structural diagram of a conversion circuit provided in an embodiment of the present utility model;

[0039] Figure 2 A schematic structural diagram of a conversion circuit provided in another embodiment of the present utility model;

[0040] Figure 3 A schematic structural diagram of a conversion circuit provided in yet another embodiment of the present utility model;

[0041] Figure 4 A schematic structural diagram of a driving module provided in an embodiment of the present utility model;

[0042] Figure 5 A schematic structural diagram of a drive unit provided in an embodiment of the present utility model;

[0043] Figure 6 A schematic structural diagram of a driving unit provided in another embodiment of the present utility model;

[0044] Figure 7A schematic diagram of the circuit structure of a driving unit provided in an embodiment of the utility model.

[0045] Explanation of Figure Numbers

[0046]

[0047] DETAILED DESCRIPTION

[0048] To facilitate understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intervening elements can exist between them. In addition, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance.

[0049] Unless otherwise defined, all technical and scientific terms used in this specification have the same meanings as those commonly understood by those skilled in the art to which this utility model belongs. The terms used in this specification and in the description of this utility model are only for the purpose of describing specific embodiments and are not intended to limit this utility model. The term "and / or" used in this specification includes any and all combinations of one or more of the relevant listed items.

[0050] The converter provided in the embodiment of the present invention may be any type of voltage converter, including but not limited to an AC / DC converter, a DC / DC converter, a DC / AC converter, and the like.

[0051] In some embodiments, the converter provided by the embodiments of the present invention includes a drive circuit and a conversion circuit. The drive circuit is electrically connected to the conversion circuit and is used to drive the conversion circuit to achieve voltage conversion.

[0052] In some embodiments, the conversion circuit includes a three-level topology conversion circuit, wherein the topology can be simplified to a one-way topology or a three-phase topology.

[0053] See also Figure 1 For example, the three-level topology conversion circuit includes a first power tube Q1, a second power tube Q2, a third power tube Q3, a fourth power tube Q4, a fifth power tube Q5, a sixth power tube Q6, a seventh power tube Q7, an eighth power tube Q8, a ninth power tube Q9, a tenth power tube Q10, an eleventh power tube Q11, a twelfth power tube Q12, a first capacitor C1, and a second capacitor C2.

[0054] One end of the first capacitor C1 is electrically connected to the DC bus positive electrode BUS+, the other end of the first capacitor C1 is electrically connected to one end of the second capacitor C2, the connection point between the first capacitor C1 and the second capacitor C2 is the center voltage node BUSN, the other end of the second capacitor C2 is electrically connected to the DC bus negative electrode BUS-, the drain of the first power tube Q1 is electrically connected to the DC bus positive electrode BUS+, the source of the first power tube Q1 is electrically connected to the drain of the fourth power tube Q4 and the source of the second power tube Q2 respectively, the drain of the second power tube Q2 is electrically connected to the drain of the third power tube Q3, and the third power tube Q4 is electrically connected to the drain of the fourth power tube Q4 and the source of the second power tube Q2 respectively. The source of the power tube Q3 is electrically connected to the node BUSN, the source of the fourth power tube Q4 is electrically connected to the negative electrode BUS- of the DC bus, the drain of the fifth power tube Q5 is electrically connected to the positive electrode BUS+ of the DC bus, the source of the fifth power tube Q5 is electrically connected to the drain of the eighth power tube Q8 and the source of the sixth power tube Q6, the drain of the sixth power tube Q6 is electrically connected to the drain of the seventh power tube Q7, the source of the seventh power tube Q7 is electrically connected to the central voltage node BUSN, the source of the eighth power tube Q8 is electrically connected to the negative electrode BUS- of the DC bus, the drain of the ninth power tube Q9 is electrically connected to the positive electrode BUS+ of the DC bus The positive electrode of the DC bus BUS+ is electrically connected to the ninth power tube Q9, the source of the ninth power tube Q9 is electrically connected to the drain of the twelfth power tube Q12 and the source of the tenth power tube Q10 respectively, the drain of the tenth power tube Q10 is electrically connected to the drain of the eleventh power tube Q11, the source of the eleventh power tube Q11 is electrically connected to the node BUSN, the source of the twelfth power tube Q12 is electrically connected to the negative electrode of the DC bus BUS-, the first power tube Q1, the second power tube Q2, the third power tube Q3, the fourth power tube Q4, the fifth power tube Q5, the sixth power tube Q6, the seventh power tube Q7, the eighth power tube Q8, the The gates of the ninth power tube Q9, the tenth power tube Q10, the eleventh power tube Q11, and the twelfth power tube Q12 are electrically connected to the drive circuit. The connection point between the first power tube Q1, the second power tube Q2, and the fourth power tube Q4 serves as a first output node A. The connection point between the fifth power tube Q5, the sixth power tube Q6, and the eighth power tube Q8 serves as a second output node B. The connection point between the ninth power tube Q9, the tenth power tube Q10, and the twelfth power tube Q12 serves as a third output node C. The first output node A, the second output node B, and the third output node C can output three-phase alternating current.

[0055] To reduce losses during voltage conversion, based on the characteristics of the power tubes, the first power tube Q1, the fourth power tube Q4, the fifth power tube Q5, the eighth power tube Q8, the ninth power tube Q9, and the twelfth power tube Q12 may be SiC (silicon carbide) MOS (Metal-Oxide-Semiconductor) tube devices. The second power tube Q2, the third power tube Q3, the sixth power tube Q6, the seventh power tube Q7, the tenth power tube Q10, and the eleventh power tube Q11 may be SiC MOS tube devices or IGBT (Insulated-Gate Bipolar Transistor) devices.

[0056] When the three-level topology conversion circuit is in operation, the drive circuit drives the first power tube Q1 and the third power tube Q3 to be complementary conductive, drives the second power tube Q2 and the fourth power tube Q4 to be complementary conductive, drives the fifth power tube Q5 and the seventh power tube Q7 to be complementary conductive, drives the sixth power tube Q6 and the eighth power tube Q8 to be complementary conductive, drives the ninth power tube Q9 and the eleventh power tube Q11 to be complementary conductive, and drives the tenth power tube Q10 and the twelfth power tube Q12 to be complementary conductive.

[0057] In some embodiments, the conversion circuit includes a full-bridge conversion circuit, wherein the full-bridge conversion circuit can be a single-phase full-bridge conversion circuit or a three-phase full-bridge conversion circuit.

[0058] See also Figure 2 For example, the full-bridge conversion circuit includes a third capacitor C3, a fourth capacitor C4, a thirteenth power tube Q13, a fourteenth power tube Q14, a fifteenth power tube Q15, a sixteenth power tube Q16, a seventeenth power tube Q17 and an eighteenth power tube Q18.

[0059] One end of the third capacitor C3 is electrically connected to the DC bus positive electrode BUS+, the other end of the third capacitor C3 is electrically connected to one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is electrically connected to the DC bus negative electrode BUS-, the drain of the thirteenth power tube Q13 is electrically connected to the DC bus positive electrode BUS+, the source of the thirteenth power tube Q13 is electrically connected to the drain of the fourteenth power tube Q14, the source of the fourteenth power tube Q14 is electrically connected to the DC bus negative electrode BUS-, the drain of the fifteenth power tube Q15 is electrically connected to the DC bus positive electrode BUS+, the source of the fifteenth power tube Q15 is electrically connected to the drain of the sixteenth power tube Q16, the source of the sixteenth power tube Q16 is electrically connected to the DC bus negative electrode BUS-, and the drain of the seventeenth power tube Q17 is electrically connected to the DC bus positive electrode BUS+. The source of the seventeenth power tube Q17 is electrically connected to the drain of the eighteenth power tube Q18, the source of the eighteenth power tube Q18 is electrically connected to the negative electrode BUS- of the DC bus, the gates of the thirteenth power tube Q13, the fourteenth power tube Q14, the fifteenth power tube Q15, the sixteenth power tube Q16, the seventeenth power tube Q17, and the eighteenth power tube Q18 are electrically connected to the drive circuit, the connection point between the thirteenth power tube Q13 and the fourteenth power tube Q14 is a fourth output node D, the connection point between the fifteenth power tube Q15 and the sixteenth power tube Q16 is a fifth output node E, and the connection point between the seventeenth power tube Q17 and the eighteenth power tube Q18 is a sixth output node F. The fourth output node D, the fifth output node E, and the sixth output node F can output three-phase AC power.

[0060] When the full-bridge converter circuit is working, the drive circuit drives the thirteenth power tube Q13 and the fourteenth power tube Q14 to be complementary conductive, drives the fifteenth power tube Q15 and the sixteenth power tube Q16 to be complementary conductive, and drives the seventeenth power tube Q17 and the eighteenth power tube Q18 to be complementary conductive.

[0061] In some embodiments, the conversion circuit includes a single-phase DC / DC conversion circuit.

[0062] See also Figure 3 For example, the single-phase DC / DC conversion circuit includes a first inductor L1, a fifth capacitor C5, a nineteenth power tube Q19, and a twentieth power tube Q20.

[0063] One end of the first inductor L1 is electrically connected to the drain of the nineteenth power tube Q19 and the source of the twentieth power tube Q20. The source of the twentieth power tube Q20 is electrically connected to one end of the fifth capacitor C5. The other end of the fifth capacitor C5 is electrically connected to the source of the nineteenth power tube Q19. The gates of the nineteenth power tube Q19 and the twentieth power tube Q20 are electrically connected to the driving circuit.

[0064] When the single-phase DC / DC conversion circuit is working, the driving circuit drives the nineteenth power tube Q19 and the twentieth power tube Q20 to be complementary and turned on.

[0065] In some embodiments, the driving circuit includes one or more driving modules, and one driving module is used to drive two power transistors that need to be complementary. Figure 1 In the embodiment shown, there are six pairs of two power transistors that need to be complementary conductive, so the driving circuit includes six driving modules. Similarly, for Figure 2 In the embodiment shown, the driving circuit includes three driving modules. Figure 3 In the embodiment shown, the driving circuit includes one driving module. It is also understandable that if the driving signal can be reused, the driving circuit may include fewer driving modules.

[0066] In some embodiments, see Figure 4 , each driving module 100 includes two driving units 10 .

[0067] Each driving unit 10 is configured to drive a power tube. Each driving unit 10 includes a first input end 10 a and a second input end 10 b.

[0068] One of the drive units 10 ( Figure 4 The first input terminal 10a and another driving unit 10 (denoted by reference numeral 10_1) Figure 4 The second input terminal 10b of the drive unit 10_1 (denoted by reference numeral 10_2) is configured to receive a first control signal EPWM1. The second input terminal 10b of one drive unit 10_1 and the first input terminal 10a of the other drive unit 10_2 are configured to receive a second control signal EPWM2. The first control signal EPWM1 ​​and the second control signal EPWM2 are PWM (Pulse Width Modulation) signals. Generally, a PWM signal is a pulse signal consisting of high and low levels.

[0069] When the level of the first control signal EPWM1 ​​is complementary to the second control signal EPWM2, the driving unit 10 drives the power transistors to be complementary and conductive. For example, for a driving module driving the first power transistor Q1 and the third power transistor Q3, the driving unit 10_1 is configured to drive the first power transistor Q1, and the driving unit 10_2 is configured to drive the third power transistor Q3. When the level of the first control signal EPWM1 ​​is high and the level of the second control signal EPWM2 is low, the driving unit 10_1 can drive the first power transistor Q1 to be conductive, and the driving unit 10_2 can drive the third power transistor Q3 to be disconnected. Alternatively, the driving unit 10_1 can drive the first power transistor Q1 to be disconnected, and the driving unit 10_2 can drive the third power transistor Q3 to be conductive, thereby achieving complementary conduction between the first power transistor Q1 and the third power transistor Q3.

[0070] When the level of the first control signal EPWM1 ​​is the same as the level of the second control signal EPWM2, the driver unit drives the power transistors to be simultaneously turned off. For example, in a driver module driving the first power transistor Q1 and the third power transistor Q3, the driver unit 10_1 is configured to drive the first power transistor Q1, and the driver unit 10_2 is configured to drive the third power transistor Q3. When the levels of the first control signal EPWM1 ​​and the second control signal EPWM2 are both high or low, the driver unit 10_1 can drive the first power transistor Q1 to be turned off, and the driver unit 10_2 can drive the third power transistor Q3 to be turned off. In other words, the first power transistor Q1 and the third power transistor Q3 are turned off simultaneously.

[0071] Since at a certain moment, regardless of whether the levels of the first control signal EPWM1 ​​and the second control signal EPWM2 are high or low, the first power transistor Q1 and the third power transistor Q3, which need to be complementary turned on, will not be turned on at the same time, even if the levels of the first control signal EPWM1 ​​and the second control signal EPWM2 are high at the same time due to interference, this is also the case. Therefore, this embodiment can prevent the two power transistors that need to be complementary turned on from being directly turned on, and realizes interlocked driving in hardware, thereby avoiding short circuits, thereby improving circuit reliability, and ensuring driving safety.

[0072] In some embodiments, see Figure 5 The driving unit 10 further includes an input signal conditioning circuit 11 , a driving chip 12 and an output signal conditioning circuit 13 .

[0073] The input signal conditioning circuit 11 is electrically connected to the first input terminal 10a and the second input terminal 10b, and is used for conditioning the control signals input from the first input terminal 10a and the second input terminal 10b and outputting a first input conditioning signal and a second input conditioning signal respectively.

[0074] The driving chip 12 is electrically connected to the input signal conditioning circuit 11 and is configured to output a driving signal in response to the first input conditioning signal and the second input conditioning signal.

[0075] The output signal conditioning circuit 13 is electrically connected to the driver chip 12 and is configured to be electrically connected to the power tube, and is used to condition the driving signal and then output the conditioned driving signal to the power tube.

[0076] Therefore, this embodiment can improve driving stability and reliability by conditioning the signals input to the driver chip 12 and the signals output from the driver chip 12 .

[0077] In some embodiments, see Figure 6 The input signal conditioning circuit 11 includes a first signal conditioning unit 111 and a second signal conditioning unit 112 .

[0078] The first signal conditioning unit 111 is electrically connected to the first input terminal 10 a and the driver chip 12 , and is configured to condition the control signal input from the first input terminal 10 a and output a first input conditioning signal to the driver chip 12 .

[0079] In some embodiments, as Figure 6 As shown, the first signal conditioning unit 111 includes a first filtering circuit 1111 and a first pull-down circuit 1112 .

[0080] The first filter circuit 1111 is electrically connected to the first input terminal 10 a and the driver chip 12 , and is configured to filter the control signal input from the first input terminal 10 a and output a first input conditioned signal.

[0081] In some embodiments, see Figure 7 The first filtering circuit 1111 includes a first resistor R1 and a sixth capacitor C6.

[0082] One end of the first resistor R1 is configured to input a control signal. The other end of the first resistor R1 is electrically connected to one end of the sixth capacitor C6 and the driving chip 12 , respectively. The other end of the sixth capacitor C6 is grounded.

[0083] In this embodiment, the first resistor R1 and the sixth capacitor C6 form a low-pass filter, which can reduce interference from glitches in the control signal input from the first input terminal 10 a and improve the integrity of the control signal.

[0084] The first pull-down circuit 1112 is electrically connected to the first filter circuit 1111 and the driver chip 12 , respectively, and is configured to perform pull-down processing on the first input conditioned signal and then output the signal to the driver chip 12 .

[0085] In some embodiments, as Figure 7As shown, the first pull-down circuit 1112 includes a second resistor R2.

[0086] One end of the second resistor R2 is electrically connected to the first filter circuit 1111 and the driver chip 12 , respectively. The other end of the second resistor R2 is grounded.

[0087] The second resistor R2 is a large grounding resistor with a resistance of approximately 10 kΩ. The second resistor R2 can pull the level of the first input conditioning signal to a reliable low level when the level is between a low level and a high level.

[0088] The second signal conditioning unit 112 is electrically connected to the second input terminal 10 b and the driving chip 12 , and is configured to condition the control signal input from the second input terminal 10 b and output a second input conditioned signal.

[0089] In some embodiments, as Figure 6 As shown, the second signal conditioning unit 112 includes a second filtering circuit 1121 and a second pull-down circuit 1122 .

[0090] The second filtering circuit 1121 is electrically connected to the second input terminal 10 b and the driving chip 12 , and is configured to filter the control signal input from the second input terminal 10 b and then output a second input conditioned signal.

[0091] In some embodiments, as Figure 7 As shown, the second filtering circuit 1121 includes a third resistor R3 and a seventh capacitor C7.

[0092] One end of the third resistor R3 is configured to input a control signal, the other end of the third resistor R3 is electrically connected to one end of the seventh capacitor C7 and the driving chip 12 respectively, and the other end of the seventh capacitor C7 is grounded.

[0093] In this embodiment, the third resistor R3 and the seventh capacitor C7 form a low-pass filter, which can reduce interference from glitches in the control signal input from the second input terminal 10 b and improve the integrity of the control signal.

[0094] The second pull-down circuit 1122 is electrically connected to the second filter circuit 1121 and the driver chip 12 , respectively, and is configured to perform pull-down processing on the second input conditioned signal and then output the signal to the driver chip 12 .

[0095] In some embodiments, as Figure 7 As shown, the second pull-down circuit 1122 includes a fourth resistor R4.

[0096] One end of the fourth resistor R4 is electrically connected to the second filter circuit 1121 and the driver chip 12 , respectively, and the other end of the fourth resistor R4 is grounded.

[0097] The fourth resistor R4 is a large grounding resistor with a resistance of approximately 10 kΩ. The fourth resistor R4 can pull the level of the second input conditioned signal to a reliable low level when the level is between a low level and a high level.

[0098] In some embodiments, as Figure 7 As shown, the driver chip 12 includes a power supply pin VCC1 , a first input pin IN+, a second input pin IN−, a ground pin GND1 , a positive driving voltage pin VCC2 , a negative driving voltage pin VEE2 , an output pin OUT and a clamp pin CLAMP.

[0099] The power supply pin VCC1 is configured to input the power supply V1, the first input pin IN+ is electrically connected to the first signal conditioning unit 111, the second input pin IN+ is electrically connected to the second signal conditioning unit 112, the ground pin GND1 is grounded, the positive drive voltage pin VCC2 is configured to input the positive drive power V2, the negative drive voltage pin VEE2 is configured to input the negative drive power V3, the output pin OUT is electrically connected to the output signal conditioning circuit 13, and the clamp pin CLAMP is configured to be electrically connected to the power tube.

[0100] In some embodiments, the driver chip 12 is of model UCC530MCD / STGAP2SICS. This driver chip is a single-channel isolated driver chip with the following functions:

[0101] Undervoltage Protection: Undervoltage protection is implemented between the power supply pin VCC1 and the ground pin GND1, as well as between the positive drive voltage pin VCC2 and the negative drive voltage pin VEE2, to prevent underdrive conditions on the power transistors. If the voltage between the power supply pin VCC1 and the ground pin GND1 falls below a default value 1 during device startup or below a default value 2 after startup, the voltage source undervoltage protection will hold the output pin OUT at a low level. The voltage source undervoltage protection has hysteresis to prevent chattering when ground noise is generated by the voltage source. This allows the device to tolerate small drops in bias voltage, which can occur when the device begins switching and the operating current consumption suddenly increases.

[0102] Active Pull-Down: When no power is connected to the positive drive voltage pin VCC2 and the negative drive voltage pin VEE2, the active pull-down function pulls the gate of the power transistor to a low state. This function prevents the power transistor from being accidentally turned on by clamping the output pin OUT and the clamp pin CLAMP to approximately 2V. When the driver output stage is unbiased or in undervoltage protection, the driver output is held low by the active clamp circuit, which limits the voltage rise at the driver output.

[0103] Short-Circuit Clamping: The short-circuit clamping function clamps the voltage at the driver output and pulls the active Miller clamp pin slightly above the positive drive voltage pin, VCC2, during a short-circuit condition. This helps protect the gate of the power transistor from overvoltage breakdown or degradation. This function is implemented by adding a diode connected between a dedicated pin inside the driver and the positive drive voltage pin, VCC2. The internal diode can conduct up to 500mA for a duration of 10μs and 20mA continuously. An external Schottky diode can be used to increase this current capability as needed.

[0104] Active Miller Clamp: The active Miller clamp function prevents false turn-on of the power transistor due to Miller current in single-supply applications. This function is implemented by adding a low-impedance path between the power transistor gate terminal and the negative drive voltage pin VEE2 to absorb the Miller current. This Miller clamp function clamps the power transistor gate voltage to less than 2V in the off state.

[0105] In some embodiments, the truth table of the driver chip 12 is as follows:

[0106] Table 1

[0107] IN+ IN- OUT Low level X Low level X High level Low level High level Low level High level

[0108] In Table 1 above, X represents a high level or a low level. As can be seen from Table 1 above, when a low level is input to the first input pin IN+ of the driver chip 12, the output pin OUT of the driver chip 12 outputs a low level regardless of whether a low level or a high level is input to the second input pin IN- of the driver chip 12. When a high level is input to the second input pin IN- of the driver chip 12, the output pin OUT of the driver chip 12 outputs a low level regardless of whether a low level or a high level is input to the first input pin IN+ of the driver chip 12. When a high level is input to the first input pin IN+ of the driver chip 12 and a low level is input to the second input pin IN- of the driver chip 12, the output pin OUT of the driver chip 12 outputs a high level.

[0109] It is understandable that, as described above, assuming that a high level is input to the first input pin IN+ of the driver chip 12 in the driver unit 10_1 and the second input pin IN- of the driver chip 12 in the driver unit 10_2, and a low level is input to the second input pin IN- of the driver chip 12 in the driver unit 10_1 and the first input pin IN+ of the driver chip 12 in the driver unit 10_2, according to the truth table of the driver chip 12, the drive signal output by the output pin OUT of the driver chip 12 in the driver unit 10_1 is a high level, and the drive signal output by the output pin OUT of the driver chip 12 in the driver unit 10_2 is a low level.

[0110] Assume that a low level is input to the first input pin IN+ of the driver chip 12 in the driver unit 10_1 and a high level is input to the second input pin IN- of the driver chip 12 in the driver unit 10_2. According to the truth table of the driver chip 12, the drive signal outputted by the output pin OUT of the driver chip 12 in the driver unit 10_1 is a low level, while the drive signal outputted by the output pin OUT of the driver chip 12 in the driver unit 10_2 is a high level.

[0111] Assume that the first input pin IN+ and the second input pin IN- of the driver chip 12 in the driver unit 10_1 and the first input pin IN+ and the second input pin IN- of the driver chip 12 in the driver unit 10_2 are both inputted with a low level. According to the truth table of the driver chip 12, the driving signals outputted by the output pin OUT of the driver chip 12 in the driver unit 10_1 and the driver chip 12 in the driver unit 10_2 are both at a low level.

[0112] Assume that the first input pin IN+ and the second input pin IN- of the driver chip 12 in the driver unit 10_1 and the first input pin IN+ and the second input pin IN- of the driver chip 12 in the driver unit 10_2 are both input with a high level. According to the truth table of the driver chip 12, the driving signals outputted by the output pin OUT of the driver chip 12 in the driver unit 10_1 and the driver chip 12 in the driver unit 10_2 are both at a low level.

[0113] Therefore, no matter whether a high level or a low level is input to the first input pin IN+ and the second input pin IN− of the driver chip 12 in the driver unit 10_1 or the driver chip 12 in the driver unit 10_2, the driving signal outputted from the output pin OUT of the driver chip 12 in the driver unit 10_1 or the driver chip 12 in the driver unit 10_2 will not be a high level, thereby achieving interlocking of the driving signals in hardware.

[0114] In some embodiments, as Figure 6 As shown, the output signal processing circuit 13 includes a time adjustment circuit 131 and a speed adjustment circuit 132 .

[0115] The time adjustment circuit 131 is electrically connected to the driving chip 12 and is used to adjust the rising time and falling time of the driving signal.

[0116] Rise time refers to the time required for a signal to change from a low level to a high level, and fall time refers to the time required for a signal to change from a high level to a low level.

[0117] The speed adjustment circuit 132 is configured to be electrically connected to the time adjustment circuit and the power tube respectively, and is used to adjust the rising speed and falling speed of the driving signal.

[0118] The rise rate refers to the speed at which the signal changes from a low level to a high level, and the fall rate refers to the speed at which the signal changes from a high level to a low level.

[0119] In some embodiments, as Figure 7 As shown, the time adjustment circuit 131 includes a fifth resistor R5, a sixth resistor R6 and a first diode D1.

[0120] One end of the fifth resistor R5 is electrically connected to one end of the sixth resistor R6, the driving chip 12 and the speed adjustment circuit 132. The other end of the fifth resistor R5 is electrically connected to the anode of the first diode D1. The cathode of the first diode D1 is electrically connected to the other end of the sixth resistor R6.

[0121] When the drive signal is high, the high level output by the driver chip 12 passes through the sixth resistor R6 and the speed adjustment circuit 132 and enters the gate-source terminals of the power tube. At this time, the power tube is turned on, and the driving resistance is the sixth resistor R6. When the drive signal is low, the charge at the gate-source terminals of the power tube is discharged through the speed adjustment circuit 132, the fifth resistor R5, the sixth resistor R6, and the first diode D1, so that the output pin OUT of the driver chip 12 outputs a low level. At this time, the power tube is turned off, and the driving resistance is approximately the parallel resistance value of the fifth resistor R5 and the sixth resistor R6. This connection method has a long rise time and a short fall time. According to the driving requirements, the resistance values ​​of the fifth resistor R5 and the sixth resistor R6 can be adjusted to adjust the rise time and fall time.

[0122] In some embodiments, the time adjustment circuit 131 includes a seventh resistor R7 , an eighth resistor R8 , and a second diode D2 (not shown).

[0123] One end of the seventh resistor R7 is electrically connected to one end of the eighth resistor R8, the driving chip 12 and the speed adjustment circuit 132 respectively. The other end of the seventh resistor R7 is electrically connected to the cathode of the second diode D2. The anode of the second diode D2 is electrically connected to the other end of the eighth resistor R8.

[0124] When the drive signal is high, the high level output by the driver chip 12 first passes through the parallel resistor (the resistor formed by the seventh resistor R7, the eighth resistor R8, and the second diode D2 in parallel), and then passes through the speed adjustment circuit 132 to the gate and source of the power tube. At this time, the power tube is turned on, and the driving resistance is approximately the parallel resistance value of the seventh resistor R7 and the eighth resistor R8. When the drive signal is low, the charge at the gate and source of the power tube is discharged after passing through the speed adjustment circuit 132 and the sixth resistor R6, so that the output pin OUT of the driver chip outputs a low level, and the power tube is turned off. The driving resistance is the seventh resistor R7. This connection method has a short rise time and a long fall time. According to the driving requirements, the resistance values ​​of the seventh resistor R7 and the eighth resistor R8 can be adjusted to adjust the rise time and fall time.

[0125] In some embodiments, as Figure 7 As shown, the speed regulation circuit 132 includes magnetic components.

[0126] Magnetic components are used to absorb high-frequency signals. Because the gate of a power transistor has lead inductance, magnetic components can slow the rise and fall of high-frequency signals, thereby preventing high-frequency oscillations caused by the lead inductance during the rise and fall of the drive signal. This helps prevent high-frequency ringing in the positive and negative levels of the drive signal, thereby improving the stability of the drive signal.

[0127] In some embodiments, the magnetic component is a chip-type magnetic bead, which can be placed near the gate of the power tube. At the same time, it can also be directly mechanically welded with other mounted components. Compared with the traditional method of manually placing the magnetic bead on the gate of the power tube during perforation, it can prevent the magnetic bead from falling off.

[0128] In some embodiments, as Figure 6 As shown, the driving unit 10 further includes a first voltage stabilizing circuit 14 .

[0129] The first voltage stabilizing circuit 14 is configured to be electrically connected to the power supply V1 and the driver chip 12 , and is configured to stabilize the power supply V1 and then provide the voltage to the driver chip 12 .

[0130] Since the power supply V1 is used to supply power to the driver chip 12 , the normal power supply to the driver chip 12 can be ensured by performing voltage stabilization on the power supply V1 .

[0131] In some embodiments, as Figure 7 As shown, the first voltage stabilizing circuit 14 includes an eighth capacitor C8 and a ninth capacitor C9.

[0132] One end of the eighth capacitor C8 is configured to be electrically connected to one end of the ninth capacitor C9, the driving chip 12 and the power supply V1 respectively, and the other end of the eighth capacitor C8 and the other end of the ninth capacitor C9 are grounded.

[0133] The eighth capacitor C8 plays a supporting and bypassing role to stabilize the voltage of the power supply V1. The capacitance value of the eighth capacitor C8 is generally greater than 1uF. The ninth capacitor C9 mainly plays a filtering role. The capacitance value of the ninth capacitor C9 is generally 0.1uF.

[0134] In some embodiments, as Figure 6 As shown, the driving unit 10 further includes a second voltage stabilizing circuit 15 .

[0135] The second voltage stabilizing circuit 15 is configured to be electrically connected to the positive driving power source and the driving chip 12 respectively, and is used to stabilize the positive driving power source V2 and then provide the voltage to the driving chip 12 .

[0136] The positive driving power supply V2 is a power supply for providing a positive voltage value recommended by the power tube. By performing voltage stabilization processing on the positive driving power supply V2, the positive driving power supply V2 can be kept stable.

[0137] In some embodiments, as Figure 7 As shown, the second voltage stabilizing circuit 15 includes a tenth capacitor C10 and an eleventh capacitor C11.

[0138] One end of the tenth capacitor C10 is configured to be electrically connected to one end of the eleventh capacitor C11 , the driving chip 12 and the positive driving power supply V2 , respectively. The other ends of the tenth capacitor C10 and the other ends of the eleventh capacitor C11 are grounded.

[0139] The tenth capacitor C10 plays a supporting and bypassing role to stabilize the voltage of the positive driving power supply V2. The capacitance value of the tenth capacitor C10 is generally greater than 1uF. The eleventh capacitor C11 mainly plays a filtering role. The capacitance value of the eleventh capacitor C11 is generally 0.1uF.

[0140] In some embodiments, as Figure 6 As shown, the driving unit 10 further includes a third voltage stabilizing circuit 16 .

[0141] The third voltage stabilizing circuit 16 is configured to be electrically connected to the negative driving power source V3 and the driving chip 12 , and is configured to stabilize the negative driving power source V3 and then provide the voltage to the driving chip 12 .

[0142] The negative driving power supply V3 is a power supply for providing a negative voltage value recommended by the power tube. By performing voltage stabilization processing on the negative driving power supply V3, the negative driving power supply V3 can be kept stable.

[0143] In some embodiments, as Figure 7As shown, the third voltage stabilizing circuit 16 includes a twelfth capacitor C12 and a thirteenth capacitor C13.

[0144] One end of the twelfth capacitor C12 is configured to be electrically connected to one end of the thirteenth capacitor C13 , the driving chip 12 and the negative driving power supply V3 , respectively. The other ends of the twelfth capacitor C12 and the other ends of the thirteenth capacitor C13 are grounded.

[0145] The twelfth capacitor C12 plays a supporting and bypassing role to stabilize the voltage of the negative driving power supply V3. The capacitance value of the twelfth capacitor C12 is generally greater than 1uF. The thirteenth capacitor C13 mainly plays a filtering role. The capacitance value of the thirteenth capacitor C13 is generally 0.1uF.

[0146] In some embodiments, see Figure 6 The driving unit 10 further includes a voltage clamping circuit 17 .

[0147] The voltage clamping circuit 17 is configured to be electrically connected to the output signal conditioning circuit 13 and the power tube respectively, and is used to clamp the conditioned driving signal.

[0148] By clamping the conditioned drive signal, it is possible to ensure that the drive voltage of the power tube is within the drive voltage range specified by the power tube, thereby preventing the drive voltage from being too high or too low, thereby protecting the power tube.

[0149] In some embodiments, as Figure 6 As shown, the voltage clamping circuit 17 includes a third diode D3 and a fourth diode D4.

[0150] The cathode of the third diode D3 is electrically connected to the positive driving power supply V2, the anode of the third diode D3 is configured to be electrically connected to the cathode of the fourth diode D4 and the power tube respectively, and the anode of the fourth diode D4 is electrically connected to the negative driving power supply V3.

[0151] By utilizing the unidirectional conduction characteristics of diodes, the third diode D3 and the fourth diode D4 can clamp the gate-source voltage of the power transistor to between the voltage of the positive drive power supply V2 and the voltage of the negative drive power supply V3. It is understood that the third diode D3 and the fourth diode D4 can be separate diode devices or a diode unit packaged in a single device.

[0152] In some embodiments, as Figure 6 As shown, the driving unit 10 further includes an oscillation suppression circuit 18 .

[0153] The oscillation suppression circuit 18 is configured to be electrically connected to the output signal conditioning circuit 13 and the power tube respectively, for suppressing high-frequency parasitic oscillation.

[0154] By suppressing high-frequency parasitic oscillations, the influence of high-frequency parasitic oscillations on the power tube drive can be reduced.

[0155] In some embodiments, as Figure 7 As shown, the oscillation suppression circuit 18 includes a ninth resistor R9 and a fourteenth capacitor C14.

[0156] One end of the fourteenth capacitor C14 is electrically connected to the output signal conditioning circuit 13 and the gate of the power transistor, respectively. The other end of the fourteenth capacitor C14 is electrically connected to one end of the ninth resistor R9. The other end of the ninth resistor R9 is electrically connected to the source of the power transistor and is applied with a reference voltage V4. It is worth noting that for a four-pin power transistor, the source of the power transistor is the anti-source pin.

[0157] Since the driving signal between the gate and source of the power tube may have parasitic inductance during the PCB routing process, and the driving signal is a high-frequency signal, parasitic oscillation may exist between the high-frequency signal and the parasitic inductance. Connecting the fourteenth capacitor C14 and the ninth resistor R9 in series between the gate and source of the power tube can suppress the influence of the high-frequency parasitic oscillation in the routing on the power tube drive.

[0158] The difference between the voltage of the positive driving power supply V2 and the reference voltage V4 is a positive voltage, which is generally the positive voltage value recommended for power tube driving. The difference between the voltage of the negative driving power supply V3 and the reference voltage V4 is a negative voltage, which is generally the negative voltage value recommended for power tube driving.

[0159] In some embodiments, as Figure 6 As shown, the driving unit 10 further includes an anti-interference circuit 19 .

[0160] The anti-interference circuit 19 is configured to be electrically connected to the output signal conditioning circuit 13 and the power tube, respectively, to prevent the power tube from being mis-conducted.

[0161] In some embodiments, as Figure 7 As shown, the anti-interference circuit 19 includes a tenth resistor R10.

[0162] One end of the tenth resistor R10 is configured to be electrically connected to the gate of the power tube, and the other end of the tenth resistor R10 is configured to be electrically connected to the source of the power tube.

[0163] When the module is in the initial state, the module is not powered, or the module is powered, the gate of the power tube may be input with an interference level or an uncertain level. By connecting the tenth resistor R10 in parallel between the gate and the source of the power tube, the tenth resistor R10 can pull the interference level or the uncertain level input to the gate of the power tube to a low level state, thereby preventing the power tube from being mis-turned on.

[0164] Finally, it should be noted that the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. These embodiments cannot serve as additional limitations to the content of the present invention. The purpose of providing these implementation methods is to enable a more thorough and comprehensive understanding of the disclosure of the present invention. Furthermore, under the concept of the present invention, the above-mentioned technical features continue to be combined with each other, and there are many other variations of the different aspects of the present invention as described above, all of which are considered to be within the scope of the description of the present invention; further, it is obvious to those skilled in the art that improvements or modifications can be made based on the above description, and all such improvements and modifications should fall within the scope of protection of the claims appended to the present invention.

Claims

1. A driving circuit, characterized in that: The invention comprises two driving units, each of which is configured to drive a power tube, and each of which comprises a first input end and a second input end, wherein the first input end of one of the driving units and the second input end of the other driving unit are configured to input a first control signal, and the second input end of one of the driving units and the first input end of the other driving unit are configured to input a second control signal, when the level of the first control signal is complementary to the second control signal, the driving unit drives the power tubes to be complementary and turned on, and when the level of the first control signal is the same as the second control signal, the driving unit drives the power tubes to be turned off simultaneously.

2. The driving circuit according to claim 1, wherein: The driving unit further includes: an input signal conditioning circuit electrically connected to the first input terminal and the second input terminal, configured to condition the control signals input from the first input terminal and the second input terminal and output a first input conditioning signal and a second input conditioning signal respectively; a driver chip, electrically connected to the input signal conditioning circuit, and configured to output a driving signal in response to the first input conditioning signal and the second input conditioning signal; The output signal conditioning circuit is electrically connected to the driver chip and is configured to be electrically connected to the power tube, and is used for conditioning the drive signal and outputting the conditioned drive signal to the power tube.

3. The driving circuit according to claim 2, wherein: The input signal conditioning circuit comprises: a first signal conditioning unit, electrically connected to the first input terminal and the driver chip, for conditioning the control signal input from the first input terminal and outputting a first input conditioning signal to the driver chip; The second signal conditioning unit is electrically connected to the second input terminal and the driver chip respectively, and is used for conditioning the control signal input from the second input terminal and outputting a second input conditioning signal to the driver chip.

4. The driving circuit according to claim 3, wherein: The first signal conditioning unit includes: a first filtering circuit, electrically connected to the first input terminal and the driver chip, for filtering the control signal input from the first input terminal and outputting a first input conditioning signal; The first pull-down circuit is electrically connected to the first filter circuit and the driver chip respectively, and is used for performing pull-down processing on the first input conditioned signal and then outputting the signal to the driver chip.

5. The driving circuit according to claim 3, wherein: The second signal conditioning unit includes: a second filtering circuit, electrically connected to the second input terminal and the driver chip, for filtering the control signal input from the second input terminal and outputting a second input conditioning signal; The second pull-down circuit is electrically connected to the second filter circuit and the driver chip respectively, and is used for performing pull-down processing on the second input conditioned signal and then outputting the signal to the driver chip.

6. The driving circuit according to claim 2, wherein: The output signal conditioning circuit comprises: a time adjustment circuit, electrically connected to the driver chip, for adjusting the rise time and fall time of the drive signal; The speed adjustment circuit is configured to be electrically connected to the time adjustment circuit and the power tube respectively, and is used to adjust the rising speed and falling speed of the driving signal.

7. The driving circuit according to claim 2, wherein: The driving unit further includes a first voltage stabilizing circuit; The first voltage stabilizing circuit is configured to be electrically connected to the power supply and the driver chip respectively, and is used to stabilize the power supply and then provide the power supply to the driver chip.

8. The driving circuit according to claim 2, wherein: The driving unit further includes a second voltage stabilizing circuit; The second voltage stabilizing circuit is configured to be electrically connected to the positive driving power supply and the driving chip respectively, and is used to stabilize the positive driving power supply and then provide the voltage to the driving chip.

9. The driving circuit according to claim 2, wherein: The driving unit further includes a third voltage stabilizing circuit; The third voltage stabilizing circuit is configured to be electrically connected to the negative driving power supply and the driving chip respectively, and is used to stabilize the negative driving power supply and then provide it to the driving chip.

10. The driving circuit according to claim 2, wherein: The driving unit further includes a voltage clamping circuit; The voltage clamping circuit is configured to be electrically connected to the output signal conditioning circuit and the power tube respectively, and is used to clamp the conditioned driving signal.

11. The driving circuit according to claim 2, wherein: The driving unit further includes an oscillation suppression circuit; The oscillation suppression circuit is configured to be electrically connected to the output signal conditioning circuit and the power tube respectively, and is used to suppress high-frequency parasitic oscillation.

12. The driving circuit according to claim 2, wherein: The driving unit further includes an anti-interference circuit; The anti-interference circuit is configured to be electrically connected to the output signal conditioning circuit and the power tube respectively, so as to prevent the power tube from being mis-conducted.

13. A converter, characterized in that: The drive circuit comprises the drive circuit according to any one of claims 1 to 12.

14. An electronic device, characterized in that: Comprising the converter as claimed in claim 13.

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