Surface-mounted bare chip PCB structure and semiconductor device
Through the combined structure of tapered vias and heat dissipation materials, the problems of low heat conduction efficiency and poor reliability are solved, and efficient heat dissipation and reliability are improved, which simplifies the process and reduces costs.
Patent Information
- Application Number
- CN202422506481.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-16
- Publication Date
- 2025-08-29
- Estimated Expiration
- 2034-10-16
AI Technical Summary
In the prior art, during the process of conducting heat through vias, the heat conduction efficiency is low, the bare chip is prone to heat accumulation, and the reliability of embedded copper blocks or ceramic materials is poor, and displacement and fall off are prone to occur, affecting the reliability of the device and wiring density.
The combined structure of tapered vias and heat dissipation materials is adopted. The vias gradually shrink from top to bottom, connect to multi-layer PCB substrates, and a heat dissipation material is installed in the accommodating groove below the vias. The heat dissipation material is used to export heat to avoid heat accumulation and maintain wiring density.
It improves heat conduction efficiency, reduces the risk of heat source accumulation, enhances the reliability and wiring density of the device, and has a simple process and cost-effective control.
Smart Images
Figure CN223286001U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a surface-mounted bare chip PCB structure and a semiconductor device. Background Art
[0002] With the development of data centers and wireless access networks, the use of high-speed optical modules is becoming more and more widespread. As the integration of modules increases, the demand for heat dissipation is also increasing. Therefore, it is of great significance to study the internal thermal field distribution of the module when it is working in a high-speed data stream transmission state, as well as to carry out thermal design and thermal management of the optical module packaging components and component layout. In related technologies, mechanical or laser vias are used inside the PCB board under the chip to conduct heat to the back of the PCB board through the vias. However, since PCBs are often made of multi-layer structures made of materials such as copper foil-clad resin and glass fiber, the thermal resistance of the multi-layer resin and glass fiber is very large. Therefore, in the process of conducting heat through the vias, the heat conduction efficiency is low due to the influence of the via density and the thickness of the via copper plating, and the bare chip is prone to heat accumulation, resulting in abnormal operation.
[0003] Based on this existing technology, a copper block or ceramic is embedded inside the PCB board below the chip, and heat is conducted to the back side of the PCB board through the copper block or ceramic.
[0004] However, while embedding copper blocks or highly conductive materials like ceramics achieves efficient heat conduction, it requires hollowing out the PCB beneath the chip to accommodate the heat sink. Due to the inconsistent expansion and contraction of different materials, this solution suffers from poor reliability and the risk of block displacement or even fallout over long-term use. Furthermore, the hollowed-out area makes it impossible to route wiring, reducing wiring density. Utility Model Content
[0005] In view of this, the purpose of the present invention is to provide a surface mount bare chip PCB structure and a semiconductor device.
[0006] In a first aspect, an embodiment of the present invention provides a surface-mount bare chip PCB structure, the surface-mount bare chip PCB structure comprising:
[0007] The PCB body includes a multi-layer PCB substrate stacked in a height direction;
[0008] Vias, extending downward from the top of the PCB body, are used to connect two or more PCB substrates;
[0009] Heat dissipation material is disposed within the PCB body, with the top surface of the heat dissipation material being close to the via;
[0010] The bare chip is placed on the PCB body, and the bottom surface of the bare chip is connected to the top surface of the via hole, and the heat of the bare chip is conducted to the heat dissipation material through the via hole.
[0011] In combination with the first aspect, the aperture of the via hole gradually decreases from top to bottom.
[0012] In combination with the first aspect, the via holes are opened in the PCB body for connecting the first to N-th layers of PCB substrates from top to bottom, where N≥3.
[0013] In combination with the first aspect, there are multiple via holes, and the multiple via holes are arranged at equal intervals.
[0014] Combined with the first aspect, the surface mount bare chip PCB structure also includes:
[0015] The receiving groove is opened at the lower part of the PCB body and is located below the via hole; the heat dissipation material is installed in the receiving groove.
[0016] In combination with the first aspect, the sidewall of the receiving groove is provided with an electroplating layer.
[0017] In combination with the first aspect, an inner layer is provided between two adjacent PCB substrates, and an inner layer circuit is arranged in the inner layer for connecting the two adjacent PCB substrates.
[0018] In combination with the first aspect, the bottom surface of the heat dissipation material extends downward along the bottom surface of the PCB body.
[0019] In combination with the first aspect, the bottom surface of the heat dissipation material is connected to the external metal shell.
[0020] In a second aspect, the present application provides a semiconductor device comprising the above-mentioned surface-mounted bare chip PCB structure.
[0021] The embodiments of the present invention bring the following beneficial effects:
[0022] The surface-mount bare chip PCB structure provided in this application dissipates the heat of the bare chip through the thermal conductivity of vias and heat dissipation materials. The heat dissipation capacity is sufficient to prevent heat accumulation. At the same time, there is no need to embed copper blocks or ceramics for electroplating. The process is relatively simple, the cost is effectively controlled, and the reliability is improved.
[0023] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The objectives and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.
[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.
[0026] Figure 1 Schematic diagram of the surface-mount bare chip PCB structure provided in an embodiment of the present application.
[0027] The reference numerals are as follows:
[0028] 1-PCB body, 2-via, 3-heat dissipation material, 4-bare chip, 5-receiving groove, 6-electroplating layer. DETAILED DESCRIPTION
[0029] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.
[0030] After introducing the technical terms involved in this application, the application scenarios and design concepts of the embodiments of this application are briefly introduced.
[0031] The rapid development of modern electronics is closely linked to the continuous advancement of thermal control technology. Thermal design has become a crucial component in the design of optoelectronic components, devices, and modules. The choice of thermal control solution has a profound impact on performance, reliability, and cost. PCBs are often constructed from a multilayer structure of materials such as copper-clad resin and fiberglass. Simply relying on vias or embedding copper blocks or ceramics with high thermal conductivity leads to low heat transfer efficiency, and bare chips are prone to heat accumulation, leading to malfunctions. Furthermore, due to the inconsistent expansion and contraction of different materials, embedding copper blocks or ceramics with highly thermally conductive materials poses a risk of block displacement and dislodging.
[0032] Based on this, an embodiment of the present application provides a surface-mount bare chip PCB structure and a semiconductor device.
[0033] Example 1
[0034] This application provides a surface mount bare chip PCB structure, combined with Figure 1 As shown, the surface-mount bare chip PCB structure includes: a PCB body 1, vias 2, heat dissipation material 3 and a bare chip 4.
[0035] The PCB body 1 includes a plurality of PCB substrates stacked in a height direction.
[0036] The via hole 2 extends downward from the top of the PCB body 1 and is used to connect two or more PCB substrates.
[0037] The heat dissipation material 3 is disposed in the PCB body 1 , and the top surface of the heat dissipation material 3 is close to the bottom surface of the via 2 .
[0038] The bare chip 4 is disposed on the PCB body 1 , and the bottom surface of the bare chip 4 is in contact with the top surface of the via 2 , so that the heat of the bare chip 4 is conducted to the heat dissipation material 3 through the via 2 .
[0039] In the present application, the bottom surface of the bare chip 4 is connected to the top surface of the via 2, and the bottom surface of the via 2 is close to the heat dissipation material 3. The heat of the bare chip 4 is dissipated to the external environment through the hole 2 and the heat dissipation material 3, which can effectively avoid abnormal operation caused by heat accumulation. In addition, the heat dissipation material 3 is used instead of embedded copper blocks or ceramics for electroplating, the process is relatively simple, the cost is effectively controlled, and the reliability is improved.
[0040] In combination with the first aspect, the aperture of the via hole 2 gradually decreases from top to bottom.
[0041] The side of the via 2 with a larger aperture contacts the bare chip 4, which is beneficial for quickly cooling the hot bare chip. As the aperture gradually decreases, the speed at which heat moves to the heat dissipation material 3 increases, thereby accelerating the heat conduction speed.
[0042] In combination with the first aspect, the via hole 2 is opened in the PCB body 1 for connecting the first to N-th layers of PCB substrates from top to bottom, where N≥3.
[0043] In this embodiment, the PCB body 1 includes at least four PCBs. Vias 2 extend downward from the top first PCB to at least one of the second or third PCBs. Heat dissipation material 3 is disposed within the bottom PCB. Heat dissipation material 3 can be metal or a heat dissipation pad. This material allows for flexible selection and ease of assembly. By selecting a heat dissipation material 3 of appropriate thickness and placing it in contact with the semiconductor device housing, efficient thermal conductivity is achieved.
[0044] Combine Figure 1 As shown, in this embodiment, N≥5, the via 2 is opened in the first to second PCB boards (combined with L1 and L2 in the figure); and the heat dissipation material 3 is provided in the third to Nth PCB substrates (combined with L3, L4...LN in the figure).
[0045] In combination with the first aspect, there are multiple via holes 2, and the multiple via holes 2 are arranged at equal intervals.
[0046] It can be understood that as the diameter of the contact surface between the via 2 and the bare chip increases, and as the number of the vias 2 increases, the contact area between the via 2 and the bare chip 4 increases, thereby improving the heat dissipation effect.
[0047] In combination with the first aspect, the surface-mount bare chip PCB structure further includes a receiving groove 5 . The receiving groove 5 is provided at the lower portion of the PCB body 1 and is located below the via 2 . The heat dissipation material 3 is installed in the receiving groove 5 .
[0048] In this application, a receiving groove 5 is milled deep into the PCB body 1 along the bottom PCB substrate, and the top surface of the receiving groove 5 is connected to the bottom surface of the via 2. The receiving groove 5 is connected to the via 2 to facilitate the heat transfer channel.
[0049] In combination with the first aspect, the side wall of the receiving groove 5 is provided with an electroplating layer 6 .
[0050] The electroplating layer 6 can increase the heat dissipation area and further reduce the thermal resistance.
[0051] In combination with the first aspect, an inner layer is provided between two adjacent PCB substrates, and an inner layer circuit is arranged in the inner layer for connecting the two adjacent PCB substrates.
[0052] It is understandable that there is a gap between each PCB substrate, through which heat can be transferred and the inner layer circuits can be accommodated to simplify the external structure.
[0053] In combination with the first aspect, the bottom surface of the heat dissipation material 3 extends downward along the bottom surface of the PCB body 1 .
[0054] It can be understood that when the bottom surface of the heat dissipation material 3 extends downward along the bottom surface of the PCB body 1 , heat is dissipated to the external environment to reduce the local temperature of the bare chip 4 .
[0055] In combination with the first aspect, the bottom surface of the heat dissipation material 3 is connected to the external metal shell.
[0056] It can be understood that the metal shell can be a packaging shell for packaging the bare chip 4 above the PCB body 1. Based on the heat conduction ability of the metal shell, the heat is further conducted to the external environment to achieve heat dissipation of the bare chip 4.
[0057] In a second aspect, the present application provides a semiconductor device comprising the surface-mounted bare chip PCB structure as described above.
[0058] The semiconductor device prepared based on the above-mentioned surface-mounted bare chip PCB structure has a good heat dissipation effect.
[0059] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems and devices can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0060] In addition, in the description of the embodiments of this application, unless otherwise specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0061] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.
[0062] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0063] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art who is familiar with the technical field can still modify the technical solutions described in the above embodiments within the technical scope disclosed in the present application, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
Claims
1. A surface-mount bare chip PCB structure, characterized in that: The surface-mount bare chip PCB structure includes: The PCB body includes a multi-layer PCB substrate stacked in a height direction; a via extending downward from the top of the PCB body and used to connect two or more PCB substrates; a heat dissipation material disposed in the PCB body, wherein a top surface of the heat dissipation material is close to the via hole; A bare chip is arranged on the PCB body, the bottom surface of the bare chip is connected to the top surface of the via hole, and the heat of the bare chip is conducted to the heat dissipation material through the via hole.
2. The surface mount bare chip PCB structure according to claim 1, characterized in that: The aperture of the via hole gradually decreases from top to bottom.
3. The surface mount bare chip PCB structure according to claim 1, characterized in that: The via holes are opened in the PCB body and are used to connect the first to Nth layers of PCB substrates from top to bottom, wherein N≥3.
4. The surface mount bare chip PCB structure according to claim 1, characterized in that: There are a plurality of via holes, and the via holes are arranged at equal intervals.
5. The surface mount bare chip PCB structure according to claim 1, characterized in that: The surface-mount bare chip PCB structure further includes: The receiving groove is provided at the lower part of the PCB body and is located below the via hole; the heat dissipation material is installed in the receiving groove.
6. The surface mount bare chip PCB structure according to claim 5, characterized in that: The side wall of the receiving tank is provided with an electroplating layer.
7. The surface mount bare chip PCB structure according to claim 1, characterized in that: An inner layer is provided between two adjacent layers of the PCB substrates, and an inner layer circuit is arranged in the inner layer for connecting the two adjacent layers of the PCB substrates.
8. The surface mount bare chip PCB structure according to claim 1, characterized in that: The bottom surface of the heat dissipation material extends downward along the bottom surface of the PCB body.
9. The surface mount bare chip PCB structure according to claim 1, characterized in that: The bottom surface of the heat dissipation material is connected to the external metal shell.
10. A semiconductor device, characterized in that: It comprises the surface-mount bare chip PCB structure as described in any one of claims 1-9.